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vc4: Disable early Z with computed depth.
authorEric Anholt <eric@anholt.net>
Tue, 19 Jul 2016 18:10:36 +0000 (11:10 -0700)
committerEmil Velikov <emil.l.velikov@gmail.com>
Thu, 1 Sep 2016 10:39:44 +0000 (11:39 +0100)
We don't tell the hardware whether we're computing depth, so we need
to manage early Z state manually.  Fixes piglit early-z.

(cherry picked from commit ce8504d196291452b42ed755ed3830ecb16febcd)

src/gallium/drivers/vc4/vc4_context.h
src/gallium/drivers/vc4/vc4_emit.c
src/gallium/drivers/vc4/vc4_program.c

index c271a95..77013d9 100644 (file)
@@ -143,6 +143,8 @@ struct vc4_compiled_shader {
         /** bitmask of which inputs are color inputs, for flat shade handling. */
         uint32_t color_inputs;
 
+        bool disable_early_z;
+
         uint8_t num_inputs;
 
         /* Byte offsets for the start of the vertex attributes 0-7, and the
index 5d64797..8b192da 100644 (file)
@@ -71,7 +71,9 @@ vc4_emit_state(struct pipe_context *pctx)
                 vc4->draw_max_y = MAX2(vc4->draw_max_y, maxy);
         }
 
-        if (vc4->dirty & (VC4_DIRTY_RASTERIZER | VC4_DIRTY_ZSA)) {
+        if (vc4->dirty & (VC4_DIRTY_RASTERIZER |
+                          VC4_DIRTY_ZSA |
+                          VC4_DIRTY_COMPILED_FS)) {
                 uint8_t ez_enable_mask_out = ~0;
 
                 /* HW-2905: If the RCL ends up doing a full-res load when
@@ -83,7 +85,7 @@ vc4_emit_state(struct pipe_context *pctx)
                  * was seeing bad rendering on glxgears -samples 4 even in
                  * that case.
                  */
-                if (vc4->msaa)
+                if (vc4->msaa || vc4->prog.fs->disable_early_z)
                         ez_enable_mask_out &= ~VC4_CONFIG_BITS_EARLY_Z;
 
                 cl_u8(&bcl, VC4_PACKET_CONFIGURATION_BITS);
index 5d036eb..3572cf7 100644 (file)
@@ -2032,6 +2032,11 @@ vc4_get_compiled_shader(struct vc4_context *vc4, enum qstage stage,
                         shader->input_slots[shader->num_inputs] = *slot;
                         shader->num_inputs++;
                 }
+
+                /* Note: the temporary clone in c->s has been freed. */
+                nir_shader *orig_shader = key->shader_state->base.ir.nir;
+                if (orig_shader->info.outputs_written & (1 << FRAG_RESULT_DEPTH))
+                        shader->disable_early_z = true;
         } else {
                 shader->num_inputs = c->num_inputs;