static void
radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
- struct radv_pipeline *pipeline,
VkShaderStageFlags stages,
struct radv_descriptor_set *set,
unsigned idx)
{
- if (stages & VK_SHADER_STAGE_FRAGMENT_BIT)
- emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
- idx, set->va,
- MESA_SHADER_FRAGMENT);
+ if (cmd_buffer->state.pipeline) {
+ if (stages & VK_SHADER_STAGE_FRAGMENT_BIT)
+ emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline,
+ idx, set->va,
+ MESA_SHADER_FRAGMENT);
- if (stages & VK_SHADER_STAGE_VERTEX_BIT)
- emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
- idx, set->va,
- MESA_SHADER_VERTEX);
+ if (stages & VK_SHADER_STAGE_VERTEX_BIT)
+ emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline,
+ idx, set->va,
+ MESA_SHADER_VERTEX);
- if ((stages & VK_SHADER_STAGE_GEOMETRY_BIT) && radv_pipeline_has_gs(pipeline))
- emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
- idx, set->va,
- MESA_SHADER_GEOMETRY);
+ if ((stages & VK_SHADER_STAGE_GEOMETRY_BIT) && radv_pipeline_has_gs(cmd_buffer->state.pipeline))
+ emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline,
+ idx, set->va,
+ MESA_SHADER_GEOMETRY);
- if ((stages & VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT) && radv_pipeline_has_tess(pipeline))
- emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
- idx, set->va,
- MESA_SHADER_TESS_CTRL);
+ if ((stages & VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT) && radv_pipeline_has_tess(cmd_buffer->state.pipeline))
+ emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline,
+ idx, set->va,
+ MESA_SHADER_TESS_CTRL);
- if ((stages & VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT) && radv_pipeline_has_tess(pipeline))
- emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
- idx, set->va,
- MESA_SHADER_TESS_EVAL);
+ if ((stages & VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT) && radv_pipeline_has_tess(cmd_buffer->state.pipeline))
+ emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline,
+ idx, set->va,
+ MESA_SHADER_TESS_EVAL);
+ }
- if (stages & VK_SHADER_STAGE_COMPUTE_BIT)
- emit_stage_descriptor_set_userdata(cmd_buffer, pipeline,
+ if (cmd_buffer->state.compute_pipeline && (stages & VK_SHADER_STAGE_COMPUTE_BIT))
+ emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.compute_pipeline,
idx, set->va,
MESA_SHADER_COMPUTE);
}
static void
radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
- struct radv_pipeline *pipeline,
VkShaderStageFlags stages)
{
unsigned i;
if (!set)
continue;
- radv_emit_descriptor_set_userdata(cmd_buffer, pipeline, stages, set, i);
+ radv_emit_descriptor_set_userdata(cmd_buffer, stages, set, i);
}
cmd_buffer->state.descriptors_dirty = 0;
cmd_buffer->state.push_descriptors_dirty = false;
radv_emit_primitive_reset_state(cmd_buffer, indexed_draw);
- radv_flush_descriptors(cmd_buffer, cmd_buffer->state.pipeline,
- VK_SHADER_STAGE_ALL_GRAPHICS);
+ radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
VK_SHADER_STAGE_ALL_GRAPHICS);
radv_flush_compute_state(struct radv_cmd_buffer *cmd_buffer)
{
radv_emit_compute_pipeline(cmd_buffer);
- radv_flush_descriptors(cmd_buffer, cmd_buffer->state.compute_pipeline,
- VK_SHADER_STAGE_COMPUTE_BIT);
+ radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
VK_SHADER_STAGE_COMPUTE_BIT);
si_emit_cache_flush(cmd_buffer);