2 * Copyright 2016 The Chromium OS Authors. All rights reserved.
3 * Use of this source code is governed by a BSD-style license that can be
4 * found in the LICENSE file.
8 #include <amdgpu_drm.h>
16 #include "addrinterface.h"
21 #ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
22 #define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
26 #define mmCC_RB_BACKEND_DISABLE 0x263d
27 #define mmGB_TILE_MODE0 0x2644
28 #define mmGB_MACROTILE_MODE0 0x2664
29 #define mmGB_ADDR_CONFIG 0x263e
30 #define mmMC_ARB_RAMCFG 0x9d8
44 const static uint32_t render_target_formats[] = { DRM_FORMAT_ARGB8888, DRM_FORMAT_RGB565,
45 DRM_FORMAT_XBGR8888, DRM_FORMAT_XRGB8888 };
47 const static uint32_t texture_source_formats[] = { DRM_FORMAT_GR88, DRM_FORMAT_R8, DRM_FORMAT_NV21,
50 static int amdgpu_set_metadata(int fd, uint32_t handle, struct amdgpu_bo_metadata *info)
52 struct drm_amdgpu_gem_metadata args = { 0 };
58 args.op = AMDGPU_GEM_METADATA_OP_SET_METADATA;
59 args.data.flags = info->flags;
60 args.data.tiling_info = info->tiling_info;
62 if (info->size_metadata > sizeof(args.data.data))
65 if (info->size_metadata) {
66 args.data.data_size_bytes = info->size_metadata;
67 memcpy(args.data.data, info->umd_metadata, info->size_metadata);
70 return drmCommandWriteRead(fd, DRM_AMDGPU_GEM_METADATA, &args, sizeof(args));
73 static int amdgpu_read_mm_regs(int fd, unsigned dword_offset, unsigned count, uint32_t instance,
74 uint32_t flags, uint32_t *values)
76 struct drm_amdgpu_info request;
78 memset(&request, 0, sizeof(request));
79 request.return_pointer = (uintptr_t)values;
80 request.return_size = count * sizeof(uint32_t);
81 request.query = AMDGPU_INFO_READ_MMR_REG;
82 request.read_mmr_reg.dword_offset = dword_offset;
83 request.read_mmr_reg.count = count;
84 request.read_mmr_reg.instance = instance;
85 request.read_mmr_reg.flags = flags;
87 return drmCommandWrite(fd, DRM_AMDGPU_INFO, &request, sizeof(struct drm_amdgpu_info));
90 static int amdgpu_query_gpu(int fd, struct amdgpu_gpu_info *gpu_info)
98 instance = AMDGPU_INFO_MMR_SH_INDEX_MASK << AMDGPU_INFO_MMR_SH_INDEX_SHIFT;
100 ret = amdgpu_read_mm_regs(fd, mmCC_RB_BACKEND_DISABLE, 1, instance, 0,
101 &gpu_info->backend_disable[0]);
104 /* extract bitfield CC_RB_BACKEND_DISABLE.BACKEND_DISABLE */
105 gpu_info->backend_disable[0] = (gpu_info->backend_disable[0] >> 16) & 0xff;
107 ret = amdgpu_read_mm_regs(fd, mmGB_TILE_MODE0, 32, 0xffffffff, 0, gpu_info->gb_tile_mode);
111 ret = amdgpu_read_mm_regs(fd, mmGB_MACROTILE_MODE0, 16, 0xffffffff, 0,
112 gpu_info->gb_macro_tile_mode);
116 ret = amdgpu_read_mm_regs(fd, mmGB_ADDR_CONFIG, 1, 0xffffffff, 0, &gpu_info->gb_addr_cfg);
120 ret = amdgpu_read_mm_regs(fd, mmMC_ARB_RAMCFG, 1, 0xffffffff, 0, &gpu_info->mc_arb_ramcfg);
127 static void *ADDR_API alloc_sys_mem(const ADDR_ALLOCSYSMEM_INPUT *in)
129 return malloc(in->sizeInBytes);
132 static ADDR_E_RETURNCODE ADDR_API free_sys_mem(const ADDR_FREESYSMEM_INPUT *in)
138 static int amdgpu_addrlib_compute(void *addrlib, uint32_t width, uint32_t height, uint32_t format,
139 uint64_t use_flags, uint32_t *tiling_flags,
140 ADDR_COMPUTE_SURFACE_INFO_OUTPUT *addr_out)
142 ADDR_COMPUTE_SURFACE_INFO_INPUT addr_surf_info_in = { 0 };
143 ADDR_TILEINFO addr_tile_info = { 0 };
144 ADDR_TILEINFO addr_tile_info_out = { 0 };
145 uint32_t bits_per_pixel;
147 addr_surf_info_in.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_INPUT);
149 /* Set the requested tiling mode. */
150 addr_surf_info_in.tileMode = ADDR_TM_2D_TILED_THIN1;
152 (BO_USE_CURSOR | BO_USE_LINEAR | BO_USE_SW_READ_OFTEN | BO_USE_SW_WRITE_OFTEN))
153 addr_surf_info_in.tileMode = ADDR_TM_LINEAR_ALIGNED;
154 else if (width <= 16 || height <= 16)
155 addr_surf_info_in.tileMode = ADDR_TM_1D_TILED_THIN1;
157 bits_per_pixel = drv_stride_from_format(format, 1, 0) * 8;
158 /* Bits per pixel should be calculated from format*/
159 addr_surf_info_in.bpp = bits_per_pixel;
160 addr_surf_info_in.numSamples = 1;
161 addr_surf_info_in.width = width;
162 addr_surf_info_in.height = height;
163 addr_surf_info_in.numSlices = 1;
164 addr_surf_info_in.pTileInfo = &addr_tile_info;
165 addr_surf_info_in.tileIndex = -1;
167 /* This disables incorrect calculations (hacks) in addrlib. */
168 addr_surf_info_in.flags.noStencil = 1;
170 /* Set the micro tile type. */
171 if (use_flags & BO_USE_SCANOUT)
172 addr_surf_info_in.tileType = ADDR_DISPLAYABLE;
174 addr_surf_info_in.tileType = ADDR_NON_DISPLAYABLE;
176 addr_out->size = sizeof(ADDR_COMPUTE_SURFACE_INFO_OUTPUT);
177 addr_out->pTileInfo = &addr_tile_info_out;
179 if (AddrComputeSurfaceInfo(addrlib, &addr_surf_info_in, addr_out) != ADDR_OK)
182 ADDR_CONVERT_TILEINFOTOHW_INPUT s_in = { 0 };
183 ADDR_CONVERT_TILEINFOTOHW_OUTPUT s_out = { 0 };
184 ADDR_TILEINFO s_tile_hw_info_out = { 0 };
186 s_in.size = sizeof(ADDR_CONVERT_TILEINFOTOHW_INPUT);
187 /* Convert from real value to HW value */
189 s_in.pTileInfo = &addr_tile_info_out;
192 s_out.size = sizeof(ADDR_CONVERT_TILEINFOTOHW_OUTPUT);
193 s_out.pTileInfo = &s_tile_hw_info_out;
195 if (AddrConvertTileInfoToHW(addrlib, &s_in, &s_out) != ADDR_OK)
198 if (addr_out->tileMode >= ADDR_TM_2D_TILED_THIN1)
200 *tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 4);
201 else if (addr_out->tileMode >= ADDR_TM_1D_TILED_THIN1)
203 *tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 2);
206 *tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 1);
208 *tiling_flags |= AMDGPU_TILING_SET(BANK_WIDTH, drv_log_base2(addr_tile_info_out.bankWidth));
210 AMDGPU_TILING_SET(BANK_HEIGHT, drv_log_base2(addr_tile_info_out.bankHeight));
211 *tiling_flags |= AMDGPU_TILING_SET(TILE_SPLIT, s_tile_hw_info_out.tileSplitBytes);
212 *tiling_flags |= AMDGPU_TILING_SET(MACRO_TILE_ASPECT,
213 drv_log_base2(addr_tile_info_out.macroAspectRatio));
214 *tiling_flags |= AMDGPU_TILING_SET(PIPE_CONFIG, s_tile_hw_info_out.pipeConfig);
215 *tiling_flags |= AMDGPU_TILING_SET(NUM_BANKS, s_tile_hw_info_out.banks);
220 static void *amdgpu_addrlib_init(int fd)
223 ADDR_CREATE_INPUT addr_create_input = { 0 };
224 ADDR_CREATE_OUTPUT addr_create_output = { 0 };
225 ADDR_REGISTER_VALUE reg_value = { 0 };
226 ADDR_CREATE_FLAGS create_flags = { { 0 } };
227 ADDR_E_RETURNCODE addr_ret;
229 addr_create_input.size = sizeof(ADDR_CREATE_INPUT);
230 addr_create_output.size = sizeof(ADDR_CREATE_OUTPUT);
232 struct amdgpu_gpu_info gpu_info = { 0 };
234 ret = amdgpu_query_gpu(fd, &gpu_info);
237 fprintf(stderr, "[%s]failed with error =%d\n", __func__, ret);
241 reg_value.noOfBanks = gpu_info.mc_arb_ramcfg & 0x3;
242 reg_value.gbAddrConfig = gpu_info.gb_addr_cfg;
243 reg_value.noOfRanks = (gpu_info.mc_arb_ramcfg & 0x4) >> 2;
245 reg_value.backendDisables = gpu_info.backend_disable[0];
246 reg_value.pTileConfig = gpu_info.gb_tile_mode;
247 reg_value.noOfEntries = sizeof(gpu_info.gb_tile_mode) / sizeof(gpu_info.gb_tile_mode[0]);
248 reg_value.pMacroTileConfig = gpu_info.gb_macro_tile_mode;
249 reg_value.noOfMacroEntries =
250 sizeof(gpu_info.gb_macro_tile_mode) / sizeof(gpu_info.gb_macro_tile_mode[0]);
251 create_flags.value = 0;
252 create_flags.useTileIndex = 1;
254 addr_create_input.chipEngine = CIASICIDGFXENGINE_SOUTHERNISLAND;
256 addr_create_input.chipFamily = FAMILY_CZ;
257 addr_create_input.createFlags = create_flags;
258 addr_create_input.callbacks.allocSysMem = alloc_sys_mem;
259 addr_create_input.callbacks.freeSysMem = free_sys_mem;
260 addr_create_input.callbacks.debugPrint = 0;
261 addr_create_input.regValue = reg_value;
263 addr_ret = AddrCreate(&addr_create_input, &addr_create_output);
265 if (addr_ret != ADDR_OK) {
266 fprintf(stderr, "[%s]failed error =%d\n", __func__, addr_ret);
270 return addr_create_output.hLib;
273 static int amdgpu_init(struct driver *drv)
277 struct format_metadata metadata;
278 uint64_t use_flags = BO_USE_RENDER_MASK;
280 addrlib = amdgpu_addrlib_init(drv_get_fd(drv));
286 ret = drv_add_combinations(drv, texture_source_formats, ARRAY_SIZE(texture_source_formats),
287 &LINEAR_METADATA, BO_USE_TEXTURE_MASK);
291 drv_modify_combination(drv, DRM_FORMAT_NV21, &LINEAR_METADATA, BO_USE_SCANOUT);
292 drv_modify_combination(drv, DRM_FORMAT_NV12, &LINEAR_METADATA, BO_USE_SCANOUT);
294 metadata.tiling = ADDR_DISPLAYABLE << 16 | ADDR_TM_LINEAR_ALIGNED;
295 metadata.priority = 2;
296 metadata.modifier = DRM_FORMAT_MOD_LINEAR;
298 ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
299 &metadata, use_flags);
303 drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
304 drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
305 drv_modify_combination(drv, DRM_FORMAT_XBGR8888, &metadata, BO_USE_SCANOUT);
307 metadata.tiling = ADDR_NON_DISPLAYABLE << 16 | ADDR_TM_LINEAR_ALIGNED;
308 metadata.priority = 3;
309 metadata.modifier = DRM_FORMAT_MOD_LINEAR;
311 ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
312 &metadata, use_flags);
316 use_flags &= ~BO_USE_SW_WRITE_OFTEN;
317 use_flags &= ~BO_USE_SW_READ_OFTEN;
318 use_flags &= ~BO_USE_LINEAR;
320 metadata.tiling = ADDR_DISPLAYABLE << 16 | ADDR_TM_2D_TILED_THIN1;
321 metadata.priority = 4;
323 ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
324 &metadata, use_flags);
328 drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_SCANOUT);
329 drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_SCANOUT);
330 drv_modify_combination(drv, DRM_FORMAT_XBGR8888, &metadata, BO_USE_SCANOUT);
332 metadata.tiling = ADDR_NON_DISPLAYABLE << 16 | ADDR_TM_2D_TILED_THIN1;
333 metadata.priority = 5;
335 ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
336 &metadata, use_flags);
343 static void amdgpu_close(struct driver *drv)
345 AddrDestroy(drv->priv);
349 static int amdgpu_bo_create(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
352 void *addrlib = bo->drv->priv;
353 union drm_amdgpu_gem_create gem_create;
354 struct amdgpu_bo_metadata metadata = { 0 };
355 ADDR_COMPUTE_SURFACE_INFO_OUTPUT addr_out = { 0 };
356 uint32_t tiling_flags = 0;
360 if (format == DRM_FORMAT_NV12 || format == DRM_FORMAT_NV21) {
361 drv_bo_from_format(bo, ALIGN(width, 64), height, format);
363 if (amdgpu_addrlib_compute(addrlib, width, height, format, use_flags, &tiling_flags,
367 bo->tiling = tiling_flags;
368 /* RGB has 1 plane only */
370 bo->total_size = bo->sizes[0] = addr_out.surfSize;
371 bo->strides[0] = addr_out.pixelPitch * DIV_ROUND_UP(addr_out.pixelBits, 8);
374 memset(&gem_create, 0, sizeof(gem_create));
376 gem_create.in.bo_size = bo->total_size;
377 gem_create.in.alignment = addr_out.baseAlign;
378 /* Set the placement. */
379 gem_create.in.domains = AMDGPU_GEM_DOMAIN_VRAM;
380 gem_create.in.domain_flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
381 /* Allocate the buffer with the preferred heap. */
382 ret = drmCommandWriteRead(drv_get_fd(bo->drv), DRM_AMDGPU_GEM_CREATE, &gem_create,
388 metadata.tiling_info = tiling_flags;
390 for (plane = 0; plane < bo->num_planes; plane++)
391 bo->handles[plane].u32 = gem_create.out.handle;
393 ret = amdgpu_set_metadata(drv_get_fd(bo->drv), bo->handles[0].u32, &metadata);
398 static void *amdgpu_bo_map(struct bo *bo, struct map_info *data, size_t plane, uint32_t map_flags)
401 union drm_amdgpu_gem_mmap gem_map;
403 memset(&gem_map, 0, sizeof(gem_map));
404 gem_map.in.handle = bo->handles[plane].u32;
406 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_AMDGPU_GEM_MMAP, &gem_map);
408 fprintf(stderr, "drv: DRM_IOCTL_AMDGPU_GEM_MMAP failed\n");
412 data->length = bo->total_size;
414 return mmap(0, bo->total_size, drv_get_prot(map_flags), MAP_SHARED, bo->drv->fd,
415 gem_map.out.addr_ptr);
418 static uint32_t amdgpu_resolve_format(uint32_t format, uint64_t use_flags)
421 case DRM_FORMAT_FLEX_YCbCr_420_888:
422 return DRM_FORMAT_NV12;
428 struct backend backend_amdgpu = {
431 .close = amdgpu_close,
432 .bo_create = amdgpu_bo_create,
433 .bo_destroy = drv_gem_bo_destroy,
434 .bo_import = drv_prime_bo_import,
435 .bo_map = amdgpu_bo_map,
436 .bo_unmap = drv_bo_munmap,
437 .resolve_format = amdgpu_resolve_format,