amdgpu.c

   1 /*
   2  * Copyright (c) 2016 The Chromium OS Authors. All rights reserved.
   3  * Use of this source code is governed by a BSD-style license that can be
   4  * found in the LICENSE file.
   5  */
   6 #ifdef DRV_AMDGPU
   7 #include <errno.h>
   8 #include <stdio.h>
   9 #include <stdlib.h>
  10 #include <string.h>
  11 #include <xf86drm.h>
  12 #include <amdgpu_drm.h>
  13 #include <amdgpu.h>
  14
  15 #include "addrinterface.h"
  16 #include "drv_priv.h"
  17 #include "helpers.h"
  18 #include "util.h"
  19
  20 #ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
  21 #define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
  22 #endif
  23
  24 #define mmCC_RB_BACKEND_DISABLE         0x263d
  25 #define mmGB_TILE_MODE0                 0x2644
  26 #define mmGB_MACROTILE_MODE0            0x2664
  27 #define mmGB_ADDR_CONFIG                0x263e
  28 #define mmMC_ARB_RAMCFG                 0x9d8
  29
  30 enum {
  31         FAMILY_UNKNOWN,
  32         FAMILY_SI,
  33         FAMILY_CI,
  34         FAMILY_KV,
  35         FAMILY_VI,
  36         FAMILY_CZ,
  37         FAMILY_PI,
  38         FAMILY_LAST,
  39 };
  40
  41 static struct supported_combination combos[5] = {
  42         {DRM_FORMAT_ARGB8888, DRM_FORMAT_MOD_NONE, BO_USE_CURSOR | BO_USE_LINEAR},
  43         {DRM_FORMAT_ARGB8888, DRM_FORMAT_MOD_NONE, BO_USE_RENDERING},
  44         {DRM_FORMAT_XBGR8888, DRM_FORMAT_MOD_NONE, BO_USE_RENDERING},
  45         {DRM_FORMAT_XRGB8888, DRM_FORMAT_MOD_NONE, BO_USE_LINEAR},
  46         {DRM_FORMAT_XRGB8888, DRM_FORMAT_MOD_NONE, BO_USE_RENDERING},
  47 };
  48
  49 static int amdgpu_set_metadata(int fd, uint32_t handle,
  50                                struct amdgpu_bo_metadata *info)
  51 {
  52         struct drm_amdgpu_gem_metadata args = {0};
  53
  54         if (!info)
  55                 return -EINVAL;
  56
  57         args.handle = handle;
  58         args.op = AMDGPU_GEM_METADATA_OP_SET_METADATA;
  59         args.data.flags = info->flags;
  60         args.data.tiling_info = info->tiling_info;
  61
  62         if (info->size_metadata > sizeof(args.data.data))
  63                 return -EINVAL;
  64
  65         if (info->size_metadata) {
  66                 args.data.data_size_bytes = info->size_metadata;
  67                 memcpy(args.data.data, info->umd_metadata, info->size_metadata);
  68         }
  69
  70         return drmCommandWriteRead(fd, DRM_AMDGPU_GEM_METADATA, &args,
  71                                    sizeof(args));
  72 }
  73
  74 static int amdgpu_read_mm_regs(int fd, unsigned dword_offset,
  75                                unsigned count, uint32_t instance,
  76                                uint32_t flags, uint32_t *values)
  77 {
  78         struct drm_amdgpu_info request;
  79
  80         memset(&request, 0, sizeof(request));
  81         request.return_pointer = (uintptr_t) values;
  82         request.return_size = count * sizeof(uint32_t);
  83         request.query = AMDGPU_INFO_READ_MMR_REG;
  84         request.read_mmr_reg.dword_offset = dword_offset;
  85         request.read_mmr_reg.count = count;
  86         request.read_mmr_reg.instance = instance;
  87         request.read_mmr_reg.flags = flags;
  88
  89         return drmCommandWrite(fd, DRM_AMDGPU_INFO, &request,
  90                                sizeof(struct drm_amdgpu_info));
  91 }
  92
  93 static int amdgpu_query_gpu(int fd, struct amdgpu_gpu_info *gpu_info)
  94 {
  95         int ret;
  96         uint32_t instance;
  97
  98         if (!gpu_info)
  99                 return -EINVAL;
 100
 101         instance = AMDGPU_INFO_MMR_SH_INDEX_MASK <<
 102                         AMDGPU_INFO_MMR_SH_INDEX_SHIFT;
 103
 104         ret = amdgpu_read_mm_regs(fd, mmCC_RB_BACKEND_DISABLE, 1, instance, 0,
 105                                   &gpu_info->backend_disable[0]);
 106         if (ret)
 107                 return ret;
 108         /* extract bitfield CC_RB_BACKEND_DISABLE.BACKEND_DISABLE */
 109         gpu_info->backend_disable[0] =
 110                 (gpu_info->backend_disable[0] >> 16) & 0xff;
 111
 112         ret = amdgpu_read_mm_regs(fd, mmGB_TILE_MODE0, 32, 0xffffffff, 0,
 113                                   gpu_info->gb_tile_mode);
 114         if (ret)
 115                 return ret;
 116
 117         ret = amdgpu_read_mm_regs(fd, mmGB_MACROTILE_MODE0, 16, 0xffffffff, 0,
 118                                   gpu_info->gb_macro_tile_mode);
 119         if (ret)
 120                 return ret;
 121
 122         ret = amdgpu_read_mm_regs(fd, mmGB_ADDR_CONFIG, 1, 0xffffffff, 0,
 123                                   &gpu_info->gb_addr_cfg);
 124         if (ret)
 125                 return ret;
 126
 127         ret = amdgpu_read_mm_regs(fd, mmMC_ARB_RAMCFG, 1, 0xffffffff, 0,
 128                                   &gpu_info->mc_arb_ramcfg);
 129         if (ret)
 130                 return ret;
 131
 132         return 0;
 133 }
 134
 135 static void *ADDR_API alloc_sys_mem(const ADDR_ALLOCSYSMEM_INPUT *in)
 136 {
 137         return malloc(in->sizeInBytes);
 138 }
 139
 140 static ADDR_E_RETURNCODE ADDR_API free_sys_mem(const ADDR_FREESYSMEM_INPUT *in)
 141 {
 142         free(in->pVirtAddr);
 143         return ADDR_OK;
 144 }
 145
 146 static int amdgpu_addrlib_compute(void *addrlib, uint32_t width,
 147                                   uint32_t height, uint32_t format,
 148                                   uint32_t usage, uint32_t *tiling_flags,
 149                                   ADDR_COMPUTE_SURFACE_INFO_OUTPUT *addr_out)
 150 {
 151         ADDR_COMPUTE_SURFACE_INFO_INPUT addr_surf_info_in = {0};
 152         ADDR_TILEINFO addr_tile_info = {0};
 153         ADDR_TILEINFO addr_tile_info_out = {0};
 154
 155         addr_surf_info_in.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_INPUT);
 156
 157         /* Set the requested tiling mode. */
 158         addr_surf_info_in.tileMode = ADDR_TM_2D_TILED_THIN1;
 159         if (usage & (BO_USE_CURSOR | BO_USE_LINEAR))
 160                 addr_surf_info_in.tileMode = ADDR_TM_LINEAR_ALIGNED;
 161         if (width <= 16 || height <= 16)
 162                 addr_surf_info_in.tileMode = ADDR_TM_1D_TILED_THIN1;
 163
 164         /* Bits per pixel should be calculated from format*/
 165         addr_surf_info_in.bpp = drv_bpp_from_format(format, 0);
 166         addr_surf_info_in.numSamples = 1;
 167         addr_surf_info_in.width = width;
 168         addr_surf_info_in.height = height;
 169         addr_surf_info_in.numSlices = 1;
 170         addr_surf_info_in.pTileInfo = &addr_tile_info;
 171         addr_surf_info_in.tileIndex = -1;
 172
 173         /* This disables incorrect calculations (hacks) in addrlib. */
 174         addr_surf_info_in.flags.noStencil = 1;
 175
 176         /* Set the micro tile type. */
 177         if (usage & BO_USE_SCANOUT)
 178                 addr_surf_info_in.tileType = ADDR_DISPLAYABLE;
 179         else
 180                 addr_surf_info_in.tileType = ADDR_NON_DISPLAYABLE;
 181
 182         addr_out->size = sizeof(ADDR_COMPUTE_SURFACE_INFO_OUTPUT);
 183         addr_out->pTileInfo = &addr_tile_info_out;
 184
 185         if (AddrComputeSurfaceInfo(addrlib, &addr_surf_info_in,
 186                                    addr_out) != ADDR_OK)
 187                 return -EINVAL;
 188
 189         ADDR_CONVERT_TILEINFOTOHW_INPUT s_in = {0};
 190         ADDR_CONVERT_TILEINFOTOHW_OUTPUT s_out = {0};
 191         ADDR_TILEINFO s_tile_hw_info_out = {0};
 192
 193         s_in.size = sizeof(ADDR_CONVERT_TILEINFOTOHW_INPUT);
 194         /* Convert from real value to HW value */
 195         s_in.reverse = 0;
 196         s_in.pTileInfo = &addr_tile_info_out;
 197         s_in.tileIndex = -1;
 198
 199         s_out.size = sizeof(ADDR_CONVERT_TILEINFOTOHW_OUTPUT);
 200         s_out.pTileInfo = &s_tile_hw_info_out;
 201
 202         if (AddrConvertTileInfoToHW(addrlib, &s_in, &s_out) != ADDR_OK)
 203                 return -EINVAL;
 204
 205         if (addr_out->tileMode >= ADDR_TM_2D_TILED_THIN1)
 206                 /* 2D_TILED_THIN1 */
 207                 *tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 4);
 208         else if (addr_out->tileMode >= ADDR_TM_1D_TILED_THIN1)
 209                 /* 1D_TILED_THIN1 */
 210                 *tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 2);
 211         else
 212                 /* LINEAR_ALIGNED */
 213                 *tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 1);
 214
 215         *tiling_flags |= AMDGPU_TILING_SET(BANK_WIDTH,
 216                         drv_log_base2(addr_tile_info_out.bankWidth));
 217         *tiling_flags |= AMDGPU_TILING_SET(BANK_HEIGHT,
 218                         drv_log_base2(addr_tile_info_out.bankHeight));
 219         *tiling_flags |= AMDGPU_TILING_SET(TILE_SPLIT,
 220                         s_tile_hw_info_out.tileSplitBytes);
 221         *tiling_flags |= AMDGPU_TILING_SET(MACRO_TILE_ASPECT,
 222                         drv_log_base2(addr_tile_info_out.macroAspectRatio));
 223         *tiling_flags |= AMDGPU_TILING_SET(PIPE_CONFIG,
 224                                 s_tile_hw_info_out.pipeConfig);
 225         *tiling_flags |= AMDGPU_TILING_SET(NUM_BANKS, s_tile_hw_info_out.banks);
 226
 227         return 0;
 228 }
 229
 230 static void *amdgpu_addrlib_init(int fd)
 231 {
 232         int ret;
 233         ADDR_CREATE_INPUT addr_create_input = {0};
 234         ADDR_CREATE_OUTPUT addr_create_output = {0};
 235         ADDR_REGISTER_VALUE reg_value = {0};
 236         ADDR_CREATE_FLAGS create_flags = { {0} };
 237         ADDR_E_RETURNCODE addr_ret;
 238
 239         addr_create_input.size = sizeof(ADDR_CREATE_INPUT);
 240         addr_create_output.size = sizeof(ADDR_CREATE_OUTPUT);
 241
 242         struct amdgpu_gpu_info gpu_info = {0};
 243
 244         ret = amdgpu_query_gpu(fd, &gpu_info);
 245
 246         if (ret) {
 247                 fprintf(stderr, "[%s]failed with error =%d\n", __func__, ret);
 248                 return NULL;
 249         }
 250
 251         reg_value.noOfBanks = gpu_info.mc_arb_ramcfg & 0x3;
 252         reg_value.gbAddrConfig = gpu_info.gb_addr_cfg;
 253         reg_value.noOfRanks = (gpu_info.mc_arb_ramcfg & 0x4) >> 2;
 254
 255         reg_value.backendDisables = gpu_info.backend_disable[0];
 256         reg_value.pTileConfig = gpu_info.gb_tile_mode;
 257         reg_value.noOfEntries = sizeof(gpu_info.gb_tile_mode)
 258                         / sizeof(gpu_info.gb_tile_mode[0]);
 259         reg_value.pMacroTileConfig = gpu_info.gb_macro_tile_mode;
 260         reg_value.noOfMacroEntries = sizeof(gpu_info.gb_macro_tile_mode)
 261                         / sizeof(gpu_info.gb_macro_tile_mode[0]);
 262         create_flags.value = 0;
 263         create_flags.useTileIndex = 1;
 264
 265         addr_create_input.chipEngine = CIASICIDGFXENGINE_SOUTHERNISLAND;
 266
 267         addr_create_input.chipFamily = FAMILY_CZ;
 268         addr_create_input.createFlags = create_flags;
 269         addr_create_input.callbacks.allocSysMem = alloc_sys_mem;
 270         addr_create_input.callbacks.freeSysMem = free_sys_mem;
 271         addr_create_input.callbacks.debugPrint = 0;
 272         addr_create_input.regValue = reg_value;
 273
 274         addr_ret = AddrCreate(&addr_create_input, &addr_create_output);
 275
 276         if (addr_ret != ADDR_OK) {
 277                 fprintf(stderr, "[%s]failed error =%d\n", __func__, addr_ret);
 278                 return NULL;
 279         }
 280
 281         return addr_create_output.hLib;
 282 }
 283
 284 static int amdgpu_init(struct driver *drv)
 285 {
 286         void *addrlib;
 287
 288         addrlib = amdgpu_addrlib_init(drv_get_fd(drv));
 289         if (!addrlib)
 290                 return -1;
 291
 292         drv->priv = addrlib;
 293
 294         drv_insert_combinations(drv, combos, ARRAY_SIZE(combos));
 295         return drv_add_kms_flags(drv);
 296 }
 297
 298 static void amdgpu_close(struct driver *drv)
 299 {
 300         AddrDestroy(drv->priv);
 301         drv->priv = NULL;
 302 }
 303
 304 static int amdgpu_bo_create(struct bo *bo, uint32_t width, uint32_t height,
 305                             uint32_t format, uint32_t usage)
 306 {
 307         void *addrlib = bo->drv->priv;
 308         union drm_amdgpu_gem_create gem_create;
 309         struct amdgpu_bo_metadata metadata = {0};
 310         ADDR_COMPUTE_SURFACE_INFO_OUTPUT addr_out = {0};
 311         uint32_t tiling_flags = 0;
 312         int ret;
 313
 314         if (amdgpu_addrlib_compute(addrlib, width,
 315                                    height, format, usage,
 316                                    &tiling_flags,
 317                                    &addr_out) < 0)
 318                 return -EINVAL;
 319
 320         bo->tiling = tiling_flags;
 321         bo->offsets[0] = 0;
 322         bo->sizes[0] = addr_out.surfSize;
 323         bo->strides[0] = addr_out.pixelPitch
 324                 * DIV_ROUND_UP(addr_out.pixelBits, 8);
 325
 326         memset(&gem_create, 0, sizeof(gem_create));
 327         gem_create.in.bo_size = bo->sizes[0];
 328         gem_create.in.alignment = addr_out.baseAlign;
 329         /* Set the placement. */
 330         gem_create.in.domains = AMDGPU_GEM_DOMAIN_VRAM;
 331         gem_create.in.domain_flags = usage;
 332
 333         /* Allocate the buffer with the preferred heap. */
 334         ret = drmCommandWriteRead(drv_get_fd(bo->drv), DRM_AMDGPU_GEM_CREATE,
 335                                   &gem_create, sizeof(gem_create));
 336
 337         if (ret < 0)
 338                 return ret;
 339
 340         bo->handles[0].u32 = gem_create.out.handle;
 341
 342         metadata.tiling_info = tiling_flags;
 343
 344         ret = amdgpu_set_metadata(drv_get_fd(bo->drv),
 345                                   bo->handles[0].u32, &metadata);
 346
 347         return ret;
 348 }
 349
 350 struct backend backend_amdgpu = {
 351         .name = "amdgpu",
 352         .init = amdgpu_init,
 353         .close = amdgpu_close,
 354         .bo_create = amdgpu_bo_create,
 355         .bo_destroy = drv_gem_bo_destroy,
 356 };
 357
 358 #endif
 359