2 * Copyright 2016 The Chromium OS Authors. All rights reserved.
3 * Use of this source code is governed by a BSD-style license that can be
4 * found in the LICENSE file.
13 #include <amdgpu_drm.h>
16 #include "addrinterface.h"
21 #ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
22 #define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
25 #define mmCC_RB_BACKEND_DISABLE 0x263d
26 #define mmGB_TILE_MODE0 0x2644
27 #define mmGB_MACROTILE_MODE0 0x2664
28 #define mmGB_ADDR_CONFIG 0x263e
29 #define mmMC_ARB_RAMCFG 0x9d8
42 const static uint32_t supported_formats[] = {
43 DRM_FORMAT_ARGB8888, DRM_FORMAT_XBGR8888, DRM_FORMAT_XRGB8888
46 static int amdgpu_set_metadata(int fd, uint32_t handle,
47 struct amdgpu_bo_metadata *info)
49 struct drm_amdgpu_gem_metadata args = {0};
55 args.op = AMDGPU_GEM_METADATA_OP_SET_METADATA;
56 args.data.flags = info->flags;
57 args.data.tiling_info = info->tiling_info;
59 if (info->size_metadata > sizeof(args.data.data))
62 if (info->size_metadata) {
63 args.data.data_size_bytes = info->size_metadata;
64 memcpy(args.data.data, info->umd_metadata, info->size_metadata);
67 return drmCommandWriteRead(fd, DRM_AMDGPU_GEM_METADATA, &args,
71 static int amdgpu_read_mm_regs(int fd, unsigned dword_offset,
72 unsigned count, uint32_t instance,
73 uint32_t flags, uint32_t *values)
75 struct drm_amdgpu_info request;
77 memset(&request, 0, sizeof(request));
78 request.return_pointer = (uintptr_t) values;
79 request.return_size = count * sizeof(uint32_t);
80 request.query = AMDGPU_INFO_READ_MMR_REG;
81 request.read_mmr_reg.dword_offset = dword_offset;
82 request.read_mmr_reg.count = count;
83 request.read_mmr_reg.instance = instance;
84 request.read_mmr_reg.flags = flags;
86 return drmCommandWrite(fd, DRM_AMDGPU_INFO, &request,
87 sizeof(struct drm_amdgpu_info));
90 static int amdgpu_query_gpu(int fd, struct amdgpu_gpu_info *gpu_info)
98 instance = AMDGPU_INFO_MMR_SH_INDEX_MASK <<
99 AMDGPU_INFO_MMR_SH_INDEX_SHIFT;
101 ret = amdgpu_read_mm_regs(fd, mmCC_RB_BACKEND_DISABLE, 1, instance, 0,
102 &gpu_info->backend_disable[0]);
105 /* extract bitfield CC_RB_BACKEND_DISABLE.BACKEND_DISABLE */
106 gpu_info->backend_disable[0] =
107 (gpu_info->backend_disable[0] >> 16) & 0xff;
109 ret = amdgpu_read_mm_regs(fd, mmGB_TILE_MODE0, 32, 0xffffffff, 0,
110 gpu_info->gb_tile_mode);
114 ret = amdgpu_read_mm_regs(fd, mmGB_MACROTILE_MODE0, 16, 0xffffffff, 0,
115 gpu_info->gb_macro_tile_mode);
119 ret = amdgpu_read_mm_regs(fd, mmGB_ADDR_CONFIG, 1, 0xffffffff, 0,
120 &gpu_info->gb_addr_cfg);
124 ret = amdgpu_read_mm_regs(fd, mmMC_ARB_RAMCFG, 1, 0xffffffff, 0,
125 &gpu_info->mc_arb_ramcfg);
132 static void *ADDR_API alloc_sys_mem(const ADDR_ALLOCSYSMEM_INPUT *in)
134 return malloc(in->sizeInBytes);
137 static ADDR_E_RETURNCODE ADDR_API free_sys_mem(const ADDR_FREESYSMEM_INPUT *in)
143 static int amdgpu_addrlib_compute(void *addrlib, uint32_t width,
144 uint32_t height, uint32_t format,
145 uint32_t usage, uint32_t *tiling_flags,
146 ADDR_COMPUTE_SURFACE_INFO_OUTPUT *addr_out)
148 ADDR_COMPUTE_SURFACE_INFO_INPUT addr_surf_info_in = {0};
149 ADDR_TILEINFO addr_tile_info = {0};
150 ADDR_TILEINFO addr_tile_info_out = {0};
152 addr_surf_info_in.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_INPUT);
154 /* Set the requested tiling mode. */
155 addr_surf_info_in.tileMode = ADDR_TM_2D_TILED_THIN1;
156 if (usage & (BO_USE_CURSOR | BO_USE_LINEAR | BO_USE_SW_READ_OFTEN |
157 BO_USE_SW_WRITE_OFTEN))
158 addr_surf_info_in.tileMode = ADDR_TM_LINEAR_ALIGNED;
159 else if (width <= 16 || height <= 16)
160 addr_surf_info_in.tileMode = ADDR_TM_1D_TILED_THIN1;
162 /* Bits per pixel should be calculated from format*/
163 addr_surf_info_in.bpp = drv_bpp_from_format(format, 0);
164 addr_surf_info_in.numSamples = 1;
165 addr_surf_info_in.width = width;
166 addr_surf_info_in.height = height;
167 addr_surf_info_in.numSlices = 1;
168 addr_surf_info_in.pTileInfo = &addr_tile_info;
169 addr_surf_info_in.tileIndex = -1;
171 /* This disables incorrect calculations (hacks) in addrlib. */
172 addr_surf_info_in.flags.noStencil = 1;
174 /* Set the micro tile type. */
175 if (usage & BO_USE_SCANOUT)
176 addr_surf_info_in.tileType = ADDR_DISPLAYABLE;
178 addr_surf_info_in.tileType = ADDR_NON_DISPLAYABLE;
180 addr_out->size = sizeof(ADDR_COMPUTE_SURFACE_INFO_OUTPUT);
181 addr_out->pTileInfo = &addr_tile_info_out;
183 if (AddrComputeSurfaceInfo(addrlib, &addr_surf_info_in,
184 addr_out) != ADDR_OK)
187 ADDR_CONVERT_TILEINFOTOHW_INPUT s_in = {0};
188 ADDR_CONVERT_TILEINFOTOHW_OUTPUT s_out = {0};
189 ADDR_TILEINFO s_tile_hw_info_out = {0};
191 s_in.size = sizeof(ADDR_CONVERT_TILEINFOTOHW_INPUT);
192 /* Convert from real value to HW value */
194 s_in.pTileInfo = &addr_tile_info_out;
197 s_out.size = sizeof(ADDR_CONVERT_TILEINFOTOHW_OUTPUT);
198 s_out.pTileInfo = &s_tile_hw_info_out;
200 if (AddrConvertTileInfoToHW(addrlib, &s_in, &s_out) != ADDR_OK)
203 if (addr_out->tileMode >= ADDR_TM_2D_TILED_THIN1)
205 *tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 4);
206 else if (addr_out->tileMode >= ADDR_TM_1D_TILED_THIN1)
208 *tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 2);
211 *tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 1);
213 *tiling_flags |= AMDGPU_TILING_SET(BANK_WIDTH,
214 drv_log_base2(addr_tile_info_out.bankWidth));
215 *tiling_flags |= AMDGPU_TILING_SET(BANK_HEIGHT,
216 drv_log_base2(addr_tile_info_out.bankHeight));
217 *tiling_flags |= AMDGPU_TILING_SET(TILE_SPLIT,
218 s_tile_hw_info_out.tileSplitBytes);
219 *tiling_flags |= AMDGPU_TILING_SET(MACRO_TILE_ASPECT,
220 drv_log_base2(addr_tile_info_out.macroAspectRatio));
221 *tiling_flags |= AMDGPU_TILING_SET(PIPE_CONFIG,
222 s_tile_hw_info_out.pipeConfig);
223 *tiling_flags |= AMDGPU_TILING_SET(NUM_BANKS, s_tile_hw_info_out.banks);
228 static void *amdgpu_addrlib_init(int fd)
231 ADDR_CREATE_INPUT addr_create_input = {0};
232 ADDR_CREATE_OUTPUT addr_create_output = {0};
233 ADDR_REGISTER_VALUE reg_value = {0};
234 ADDR_CREATE_FLAGS create_flags = { {0} };
235 ADDR_E_RETURNCODE addr_ret;
237 addr_create_input.size = sizeof(ADDR_CREATE_INPUT);
238 addr_create_output.size = sizeof(ADDR_CREATE_OUTPUT);
240 struct amdgpu_gpu_info gpu_info = {0};
242 ret = amdgpu_query_gpu(fd, &gpu_info);
245 fprintf(stderr, "[%s]failed with error =%d\n", __func__, ret);
249 reg_value.noOfBanks = gpu_info.mc_arb_ramcfg & 0x3;
250 reg_value.gbAddrConfig = gpu_info.gb_addr_cfg;
251 reg_value.noOfRanks = (gpu_info.mc_arb_ramcfg & 0x4) >> 2;
253 reg_value.backendDisables = gpu_info.backend_disable[0];
254 reg_value.pTileConfig = gpu_info.gb_tile_mode;
255 reg_value.noOfEntries = sizeof(gpu_info.gb_tile_mode)
256 / sizeof(gpu_info.gb_tile_mode[0]);
257 reg_value.pMacroTileConfig = gpu_info.gb_macro_tile_mode;
258 reg_value.noOfMacroEntries = sizeof(gpu_info.gb_macro_tile_mode)
259 / sizeof(gpu_info.gb_macro_tile_mode[0]);
260 create_flags.value = 0;
261 create_flags.useTileIndex = 1;
263 addr_create_input.chipEngine = CIASICIDGFXENGINE_SOUTHERNISLAND;
265 addr_create_input.chipFamily = FAMILY_CZ;
266 addr_create_input.createFlags = create_flags;
267 addr_create_input.callbacks.allocSysMem = alloc_sys_mem;
268 addr_create_input.callbacks.freeSysMem = free_sys_mem;
269 addr_create_input.callbacks.debugPrint = 0;
270 addr_create_input.regValue = reg_value;
272 addr_ret = AddrCreate(&addr_create_input, &addr_create_output);
274 if (addr_ret != ADDR_OK) {
275 fprintf(stderr, "[%s]failed error =%d\n", __func__, addr_ret);
279 return addr_create_output.hLib;
282 static int amdgpu_init(struct driver *drv)
286 struct format_metadata metadata;
287 uint32_t flags = BO_COMMON_USE_MASK;
289 addrlib = amdgpu_addrlib_init(drv_get_fd(drv));
295 metadata.tiling = ADDR_DISPLAYABLE << 16 | ADDR_TM_LINEAR_ALIGNED;
296 metadata.priority = 1;
297 metadata.modifier = DRM_FORMAT_MOD_NONE;
299 ret = drv_add_combinations(drv, supported_formats,
300 ARRAY_SIZE(supported_formats), &metadata,
305 drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata,
306 BO_USE_CURSOR | BO_USE_SCANOUT);
307 drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata,
308 BO_USE_CURSOR | BO_USE_SCANOUT);
309 drv_modify_combination(drv, DRM_FORMAT_XBGR8888, &metadata,
312 metadata.tiling = ADDR_NON_DISPLAYABLE << 16 | ADDR_TM_LINEAR_ALIGNED;
313 metadata.priority = 2;
314 metadata.modifier = DRM_FORMAT_MOD_NONE;
316 ret = drv_add_combinations(drv, supported_formats,
317 ARRAY_SIZE(supported_formats), &metadata,
322 flags &= ~BO_USE_SW_WRITE_OFTEN;
323 flags &= ~BO_USE_SW_READ_OFTEN;
324 flags &= ~BO_USE_LINEAR;
326 metadata.tiling = ADDR_DISPLAYABLE << 16 | ADDR_TM_2D_TILED_THIN1;
327 metadata.priority = 3;
329 ret = drv_add_combinations(drv, supported_formats,
330 ARRAY_SIZE(supported_formats), &metadata,
335 drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata,
337 drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata,
339 drv_modify_combination(drv, DRM_FORMAT_XBGR8888, &metadata,
342 metadata.tiling = ADDR_NON_DISPLAYABLE << 16 | ADDR_TM_2D_TILED_THIN1;
343 metadata.priority = 4;
345 ret = drv_add_combinations(drv, supported_formats,
346 ARRAY_SIZE(supported_formats), &metadata,
354 static void amdgpu_close(struct driver *drv)
356 AddrDestroy(drv->priv);
360 static int amdgpu_bo_create(struct bo *bo, uint32_t width, uint32_t height,
361 uint32_t format, uint32_t usage)
363 void *addrlib = bo->drv->priv;
364 union drm_amdgpu_gem_create gem_create;
365 struct amdgpu_bo_metadata metadata = {0};
366 ADDR_COMPUTE_SURFACE_INFO_OUTPUT addr_out = {0};
367 uint32_t tiling_flags = 0;
368 uint32_t gem_create_flags = 0;
371 if (amdgpu_addrlib_compute(addrlib, width,
372 height, format, usage,
377 bo->tiling = tiling_flags;
379 bo->sizes[0] = addr_out.surfSize;
380 bo->strides[0] = addr_out.pixelPitch
381 * DIV_ROUND_UP(addr_out.pixelBits, 8);
382 if (usage & (BO_USE_CURSOR | BO_USE_LINEAR | BO_USE_SW_READ_OFTEN |
383 BO_USE_SW_WRITE_OFTEN | BO_USE_SW_WRITE_RARELY |
384 BO_USE_SW_READ_RARELY))
385 gem_create_flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
387 gem_create_flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
389 memset(&gem_create, 0, sizeof(gem_create));
390 gem_create.in.bo_size = bo->sizes[0];
391 gem_create.in.alignment = addr_out.baseAlign;
392 /* Set the placement. */
393 gem_create.in.domains = AMDGPU_GEM_DOMAIN_VRAM;
394 gem_create.in.domain_flags = gem_create_flags;
396 /* Allocate the buffer with the preferred heap. */
397 ret = drmCommandWriteRead(drv_get_fd(bo->drv), DRM_AMDGPU_GEM_CREATE,
398 &gem_create, sizeof(gem_create));
403 bo->handles[0].u32 = gem_create.out.handle;
405 metadata.tiling_info = tiling_flags;
407 ret = amdgpu_set_metadata(drv_get_fd(bo->drv),
408 bo->handles[0].u32, &metadata);
413 static void *amdgpu_bo_map(struct bo *bo, struct map_info *data, size_t plane)
416 union drm_amdgpu_gem_mmap gem_map;
418 memset(&gem_map, 0, sizeof(gem_map));
419 gem_map.in.handle = bo->handles[0].u32;
421 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_AMDGPU_GEM_MMAP, &gem_map);
423 fprintf(stderr, "drv: DRM_IOCTL_AMDGPU_GEM_MMAP failed\n");
426 data->length = bo->sizes[0];
428 return mmap(0, bo->sizes[0], PROT_READ | PROT_WRITE, MAP_SHARED,
429 bo->drv->fd, gem_map.out.addr_ptr);
432 struct backend backend_amdgpu = {
435 .close = amdgpu_close,
436 .bo_create = amdgpu_bo_create,
437 .bo_destroy = drv_gem_bo_destroy,
438 .bo_import = drv_prime_bo_import,
439 .bo_map = amdgpu_bo_map,