amdgpu.c

   1 /*
   2  * Copyright 2016 The Chromium OS Authors. All rights reserved.
   3  * Use of this source code is governed by a BSD-style license that can be
   4  * found in the LICENSE file.
   5  */
   6 #ifdef DRV_AMDGPU
   7 #include <amdgpu.h>
   8 #include <amdgpu_drm.h>
   9 #include <errno.h>
  10 #include <stdio.h>
  11 #include <stdlib.h>
  12 #include <string.h>
  13 #include <sys/mman.h>
  14 #include <xf86drm.h>
  15
  16 #include "dri.h"
  17 #include "drv_priv.h"
  18 #include "helpers.h"
  19 #include "util.h"
  20
  21 // clang-format off
  22 #define DRI_PATH STRINGIZE(DRI_DRIVER_DIR/radeonsi_dri.so)
  23 // clang-format on
  24
  25 #define TILE_TYPE_LINEAR 0
  26 /* DRI backend decides tiling in this case. */
  27 #define TILE_TYPE_DRI 1
  28
  29 /* Height alignement for Encoder/Decoder buffers */
  30 #define CHROME_HEIGHT_ALIGN 16
  31
  32 struct amdgpu_priv {
  33         struct dri_driver dri;
  34         int drm_version;
  35
  36         /* sdma */
  37         struct drm_amdgpu_info_device dev_info;
  38         uint32_t sdma_ctx;
  39         uint32_t sdma_cmdbuf_bo;
  40         uint64_t sdma_cmdbuf_addr;
  41         uint64_t sdma_cmdbuf_size;
  42         uint32_t *sdma_cmdbuf_map;
  43 };
  44
  45 struct amdgpu_linear_vma_priv {
  46         uint32_t handle;
  47         uint32_t map_flags;
  48 };
  49
  50 const static uint32_t render_target_formats[] = {
  51         DRM_FORMAT_ABGR8888,    DRM_FORMAT_ARGB8888,    DRM_FORMAT_RGB565,
  52         DRM_FORMAT_XBGR8888,    DRM_FORMAT_XRGB8888,    DRM_FORMAT_ABGR2101010,
  53         DRM_FORMAT_ARGB2101010, DRM_FORMAT_XBGR2101010, DRM_FORMAT_XRGB2101010,
  54 };
  55
  56 const static uint32_t texture_source_formats[] = { DRM_FORMAT_GR88,           DRM_FORMAT_R8,
  57                                                    DRM_FORMAT_NV21,           DRM_FORMAT_NV12,
  58                                                    DRM_FORMAT_YVU420_ANDROID, DRM_FORMAT_YVU420 };
  59
  60 static int query_dev_info(int fd, struct drm_amdgpu_info_device *dev_info)
  61 {
  62         struct drm_amdgpu_info info_args = { 0 };
  63
  64         info_args.return_pointer = (uintptr_t)dev_info;
  65         info_args.return_size = sizeof(*dev_info);
  66         info_args.query = AMDGPU_INFO_DEV_INFO;
  67
  68         return drmCommandWrite(fd, DRM_AMDGPU_INFO, &info_args, sizeof(info_args));
  69 }
  70
  71 static int sdma_init(struct amdgpu_priv *priv, int fd)
  72 {
  73         union drm_amdgpu_ctx ctx_args = { { 0 } };
  74         union drm_amdgpu_gem_create gem_create = { { 0 } };
  75         struct drm_amdgpu_gem_va va_args = { 0 };
  76         union drm_amdgpu_gem_mmap gem_map = { { 0 } };
  77         struct drm_gem_close gem_close = { 0 };
  78         int ret;
  79
  80         /* Ensure we can make a submission without BO lists. */
  81         if (priv->drm_version < 27)
  82                 return 0;
  83
  84         /* Anything outside this range needs adjustments to the SDMA copy commands */
  85         if (priv->dev_info.family < AMDGPU_FAMILY_CI || priv->dev_info.family > AMDGPU_FAMILY_NV)
  86                 return 0;
  87
  88         ctx_args.in.op = AMDGPU_CTX_OP_ALLOC_CTX;
  89
  90         ret = drmCommandWriteRead(fd, DRM_AMDGPU_CTX, &ctx_args, sizeof(ctx_args));
  91         if (ret < 0)
  92                 return ret;
  93
  94         priv->sdma_ctx = ctx_args.out.alloc.ctx_id;
  95
  96         priv->sdma_cmdbuf_size = ALIGN(4096, priv->dev_info.virtual_address_alignment);
  97         gem_create.in.bo_size = priv->sdma_cmdbuf_size;
  98         gem_create.in.alignment = 4096;
  99         gem_create.in.domains = AMDGPU_GEM_DOMAIN_GTT;
 100
 101         ret = drmCommandWriteRead(fd, DRM_AMDGPU_GEM_CREATE, &gem_create, sizeof(gem_create));
 102         if (ret < 0)
 103                 goto fail_ctx;
 104
 105         priv->sdma_cmdbuf_bo = gem_create.out.handle;
 106
 107         priv->sdma_cmdbuf_addr =
 108             ALIGN(priv->dev_info.virtual_address_offset, priv->dev_info.virtual_address_alignment);
 109
 110         /* Map the buffer into the GPU address space so we can use it from the GPU */
 111         va_args.handle = priv->sdma_cmdbuf_bo;
 112         va_args.operation = AMDGPU_VA_OP_MAP;
 113         va_args.flags = AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_EXECUTABLE;
 114         va_args.va_address = priv->sdma_cmdbuf_addr;
 115         va_args.offset_in_bo = 0;
 116         va_args.map_size = priv->sdma_cmdbuf_size;
 117
 118         ret = drmCommandWrite(fd, DRM_AMDGPU_GEM_VA, &va_args, sizeof(va_args));
 119         if (ret)
 120                 goto fail_bo;
 121
 122         gem_map.in.handle = priv->sdma_cmdbuf_bo;
 123         ret = drmIoctl(fd, DRM_IOCTL_AMDGPU_GEM_MMAP, &gem_map);
 124         if (ret)
 125                 goto fail_va;
 126
 127         priv->sdma_cmdbuf_map = mmap(0, priv->sdma_cmdbuf_size, PROT_READ | PROT_WRITE, MAP_SHARED,
 128                                      fd, gem_map.out.addr_ptr);
 129         if (priv->sdma_cmdbuf_map == MAP_FAILED) {
 130                 priv->sdma_cmdbuf_map = NULL;
 131                 ret = -ENOMEM;
 132                 goto fail_va;
 133         }
 134
 135         return 0;
 136 fail_va:
 137         va_args.operation = AMDGPU_VA_OP_UNMAP;
 138         va_args.flags = 0;
 139         drmCommandWrite(fd, DRM_AMDGPU_GEM_VA, &va_args, sizeof(va_args));
 140 fail_bo:
 141         gem_close.handle = priv->sdma_cmdbuf_bo;
 142         drmIoctl(fd, DRM_IOCTL_GEM_CLOSE, &gem_close);
 143 fail_ctx:
 144         memset(&ctx_args, 0, sizeof(ctx_args));
 145         ctx_args.in.op = AMDGPU_CTX_OP_FREE_CTX;
 146         ctx_args.in.ctx_id = priv->sdma_ctx;
 147         drmCommandWriteRead(fd, DRM_AMDGPU_CTX, &ctx_args, sizeof(ctx_args));
 148         return ret;
 149 }
 150
 151 static void sdma_finish(struct amdgpu_priv *priv, int fd)
 152 {
 153         union drm_amdgpu_ctx ctx_args = { { 0 } };
 154         struct drm_amdgpu_gem_va va_args = { 0 };
 155         struct drm_gem_close gem_close = { 0 };
 156
 157         if (!priv->sdma_cmdbuf_map)
 158                 return;
 159
 160         va_args.handle = priv->sdma_cmdbuf_bo;
 161         va_args.operation = AMDGPU_VA_OP_UNMAP;
 162         va_args.flags = 0;
 163         va_args.va_address = priv->sdma_cmdbuf_addr;
 164         va_args.offset_in_bo = 0;
 165         va_args.map_size = priv->sdma_cmdbuf_size;
 166         drmCommandWrite(fd, DRM_AMDGPU_GEM_VA, &va_args, sizeof(va_args));
 167
 168         gem_close.handle = priv->sdma_cmdbuf_bo;
 169         drmIoctl(fd, DRM_IOCTL_GEM_CLOSE, &gem_close);
 170
 171         ctx_args.in.op = AMDGPU_CTX_OP_FREE_CTX;
 172         ctx_args.in.ctx_id = priv->sdma_ctx;
 173         drmCommandWriteRead(fd, DRM_AMDGPU_CTX, &ctx_args, sizeof(ctx_args));
 174 }
 175
 176 static int sdma_copy(struct amdgpu_priv *priv, int fd, uint32_t src_handle, uint32_t dst_handle,
 177                      uint64_t size)
 178 {
 179         const uint64_t max_size_per_cmd = 0x3fff00;
 180         const uint32_t cmd_size = 7 * sizeof(uint32_t); /* 7 dwords, see loop below. */
 181         const uint64_t max_commands = priv->sdma_cmdbuf_size / cmd_size;
 182         uint64_t src_addr = priv->sdma_cmdbuf_addr + priv->sdma_cmdbuf_size;
 183         uint64_t dst_addr = src_addr + size;
 184         struct drm_amdgpu_gem_va va_args = { 0 };
 185         unsigned cmd = 0;
 186         uint64_t remaining_size = size;
 187         uint64_t cur_src_addr = src_addr;
 188         uint64_t cur_dst_addr = dst_addr;
 189         struct drm_amdgpu_cs_chunk_ib ib = { 0 };
 190         struct drm_amdgpu_cs_chunk chunks[2] = { { 0 } };
 191         uint64_t chunk_ptrs[2];
 192         union drm_amdgpu_cs cs = { { 0 } };
 193         struct drm_amdgpu_bo_list_in bo_list = { 0 };
 194         struct drm_amdgpu_bo_list_entry bo_list_entries[3] = { { 0 } };
 195         union drm_amdgpu_wait_cs wait_cs = { { 0 } };
 196         int ret = 0;
 197
 198         if (size > UINT64_MAX - max_size_per_cmd ||
 199             DIV_ROUND_UP(size, max_size_per_cmd) > max_commands)
 200                 return -ENOMEM;
 201
 202         /* Map both buffers into the GPU address space so we can access them from the GPU. */
 203         va_args.handle = src_handle;
 204         va_args.operation = AMDGPU_VA_OP_MAP;
 205         va_args.flags = AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_DELAY_UPDATE;
 206         va_args.va_address = src_addr;
 207         va_args.map_size = size;
 208
 209         ret = drmCommandWrite(fd, DRM_AMDGPU_GEM_VA, &va_args, sizeof(va_args));
 210         if (ret)
 211                 return ret;
 212
 213         va_args.handle = dst_handle;
 214         va_args.flags = AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE | AMDGPU_VM_DELAY_UPDATE;
 215         va_args.va_address = dst_addr;
 216
 217         ret = drmCommandWrite(fd, DRM_AMDGPU_GEM_VA, &va_args, sizeof(va_args));
 218         if (ret)
 219                 goto unmap_src;
 220
 221         while (remaining_size) {
 222                 uint64_t cur_size = remaining_size;
 223                 if (cur_size > max_size_per_cmd)
 224                         cur_size = max_size_per_cmd;
 225
 226                 priv->sdma_cmdbuf_map[cmd++] = 0x01; /* linear copy */
 227                 priv->sdma_cmdbuf_map[cmd++] =
 228                     priv->dev_info.family >= AMDGPU_FAMILY_AI ? (cur_size - 1) : cur_size;
 229                 priv->sdma_cmdbuf_map[cmd++] = 0;
 230                 priv->sdma_cmdbuf_map[cmd++] = cur_src_addr;
 231                 priv->sdma_cmdbuf_map[cmd++] = cur_src_addr >> 32;
 232                 priv->sdma_cmdbuf_map[cmd++] = cur_dst_addr;
 233                 priv->sdma_cmdbuf_map[cmd++] = cur_dst_addr >> 32;
 234
 235                 remaining_size -= cur_size;
 236                 cur_src_addr += cur_size;
 237                 cur_dst_addr += cur_size;
 238         }
 239
 240         ib.va_start = priv->sdma_cmdbuf_addr;
 241         ib.ib_bytes = cmd * 4;
 242         ib.ip_type = AMDGPU_HW_IP_DMA;
 243
 244         chunks[1].chunk_id = AMDGPU_CHUNK_ID_IB;
 245         chunks[1].length_dw = sizeof(ib) / 4;
 246         chunks[1].chunk_data = (uintptr_t)&ib;
 247
 248         bo_list_entries[0].bo_handle = priv->sdma_cmdbuf_bo;
 249         bo_list_entries[0].bo_priority = 8; /* Middle of range, like RADV. */
 250         bo_list_entries[1].bo_handle = src_handle;
 251         bo_list_entries[1].bo_priority = 8;
 252         bo_list_entries[2].bo_handle = dst_handle;
 253         bo_list_entries[2].bo_priority = 8;
 254
 255         bo_list.bo_number = 3;
 256         bo_list.bo_info_size = sizeof(bo_list_entries[0]);
 257         bo_list.bo_info_ptr = (uintptr_t)bo_list_entries;
 258
 259         chunks[0].chunk_id = AMDGPU_CHUNK_ID_BO_HANDLES;
 260         chunks[0].length_dw = sizeof(bo_list) / 4;
 261         chunks[0].chunk_data = (uintptr_t)&bo_list;
 262
 263         chunk_ptrs[0] = (uintptr_t)&chunks[0];
 264         chunk_ptrs[1] = (uintptr_t)&chunks[1];
 265
 266         cs.in.ctx_id = priv->sdma_ctx;
 267         cs.in.num_chunks = 2;
 268         cs.in.chunks = (uintptr_t)chunk_ptrs;
 269
 270         ret = drmCommandWriteRead(fd, DRM_AMDGPU_CS, &cs, sizeof(cs));
 271         if (ret) {
 272                 drv_log("SDMA copy command buffer submission failed %d\n", ret);
 273                 goto unmap_dst;
 274         }
 275
 276         wait_cs.in.handle = cs.out.handle;
 277         wait_cs.in.ip_type = AMDGPU_HW_IP_DMA;
 278         wait_cs.in.ctx_id = priv->sdma_ctx;
 279         wait_cs.in.timeout = INT64_MAX;
 280
 281         ret = drmCommandWriteRead(fd, DRM_AMDGPU_WAIT_CS, &wait_cs, sizeof(wait_cs));
 282         if (ret) {
 283                 drv_log("Could not wait for CS to finish\n");
 284         } else if (wait_cs.out.status) {
 285                 drv_log("Infinite wait timed out, likely GPU hang.\n");
 286                 ret = -ENODEV;
 287         }
 288
 289 unmap_dst:
 290         va_args.handle = dst_handle;
 291         va_args.operation = AMDGPU_VA_OP_UNMAP;
 292         va_args.flags = AMDGPU_VM_DELAY_UPDATE;
 293         va_args.va_address = dst_addr;
 294         drmCommandWrite(fd, DRM_AMDGPU_GEM_VA, &va_args, sizeof(va_args));
 295
 296 unmap_src:
 297         va_args.handle = src_handle;
 298         va_args.operation = AMDGPU_VA_OP_UNMAP;
 299         va_args.flags = AMDGPU_VM_DELAY_UPDATE;
 300         va_args.va_address = src_addr;
 301         drmCommandWrite(fd, DRM_AMDGPU_GEM_VA, &va_args, sizeof(va_args));
 302
 303         return ret;
 304 }
 305
 306 static int amdgpu_init(struct driver *drv)
 307 {
 308         struct amdgpu_priv *priv;
 309         drmVersionPtr drm_version;
 310         struct format_metadata metadata;
 311         uint64_t use_flags = BO_USE_RENDER_MASK;
 312
 313         priv = calloc(1, sizeof(struct amdgpu_priv));
 314         if (!priv)
 315                 return -ENOMEM;
 316
 317         drm_version = drmGetVersion(drv_get_fd(drv));
 318         if (!drm_version) {
 319                 free(priv);
 320                 return -ENODEV;
 321         }
 322
 323         priv->drm_version = drm_version->version_minor;
 324         drmFreeVersion(drm_version);
 325
 326         drv->priv = priv;
 327
 328         if (query_dev_info(drv_get_fd(drv), &priv->dev_info)) {
 329                 free(priv);
 330                 drv->priv = NULL;
 331                 return -ENODEV;
 332         }
 333         if (dri_init(drv, DRI_PATH, "radeonsi")) {
 334                 free(priv);
 335                 drv->priv = NULL;
 336                 return -ENODEV;
 337         }
 338
 339         if (sdma_init(priv, drv_get_fd(drv))) {
 340                 drv_log("SDMA init failed\n");
 341
 342                 /* Continue, as we can still succesfully map things without SDMA. */
 343         }
 344
 345         metadata.tiling = TILE_TYPE_LINEAR;
 346         metadata.priority = 1;
 347         metadata.modifier = DRM_FORMAT_MOD_LINEAR;
 348
 349         drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
 350                              &metadata, use_flags);
 351
 352         drv_add_combinations(drv, texture_source_formats, ARRAY_SIZE(texture_source_formats),
 353                              &metadata, BO_USE_TEXTURE_MASK);
 354
 355         /* NV12 format for camera, display, decoding and encoding. */
 356         drv_modify_combination(drv, DRM_FORMAT_NV12, &metadata,
 357                                BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE | BO_USE_SCANOUT |
 358                                    BO_USE_HW_VIDEO_DECODER | BO_USE_HW_VIDEO_ENCODER);
 359
 360         /* Android CTS tests require this. */
 361         drv_add_combination(drv, DRM_FORMAT_BGR888, &metadata, BO_USE_SW_MASK);
 362
 363         /* Linear formats supported by display. */
 364         drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
 365         drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
 366         drv_modify_combination(drv, DRM_FORMAT_ABGR8888, &metadata, BO_USE_SCANOUT);
 367         drv_modify_combination(drv, DRM_FORMAT_XBGR8888, &metadata, BO_USE_SCANOUT);
 368
 369         drv_modify_combination(drv, DRM_FORMAT_ABGR2101010, &metadata, BO_USE_SCANOUT);
 370         drv_modify_combination(drv, DRM_FORMAT_ARGB2101010, &metadata, BO_USE_SCANOUT);
 371         drv_modify_combination(drv, DRM_FORMAT_XBGR2101010, &metadata, BO_USE_SCANOUT);
 372         drv_modify_combination(drv, DRM_FORMAT_XRGB2101010, &metadata, BO_USE_SCANOUT);
 373
 374         drv_modify_combination(drv, DRM_FORMAT_NV21, &metadata, BO_USE_SCANOUT);
 375
 376         /*
 377          * R8 format is used for Android's HAL_PIXEL_FORMAT_BLOB and is used for JPEG snapshots
 378          * from camera and input/output from hardware decoder/encoder.
 379          */
 380         drv_modify_combination(drv, DRM_FORMAT_R8, &metadata,
 381                                BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE | BO_USE_HW_VIDEO_DECODER |
 382                                    BO_USE_HW_VIDEO_ENCODER);
 383
 384         /*
 385          * The following formats will be allocated by the DRI backend and may be potentially tiled.
 386          * Since format modifier support hasn't been implemented fully yet, it's not
 387          * possible to enumerate the different types of buffers (like i915 can).
 388          */
 389         use_flags &= ~BO_USE_RENDERSCRIPT;
 390         use_flags &= ~BO_USE_SW_WRITE_OFTEN;
 391         use_flags &= ~BO_USE_SW_READ_OFTEN;
 392         use_flags &= ~BO_USE_LINEAR;
 393
 394         metadata.tiling = TILE_TYPE_DRI;
 395         metadata.priority = 2;
 396
 397         drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
 398                              &metadata, use_flags);
 399
 400         /* Potentially tiled formats supported by display. */
 401         drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
 402         drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
 403         drv_modify_combination(drv, DRM_FORMAT_ABGR8888, &metadata, BO_USE_SCANOUT);
 404         drv_modify_combination(drv, DRM_FORMAT_XBGR8888, &metadata, BO_USE_SCANOUT);
 405
 406         drv_modify_combination(drv, DRM_FORMAT_ABGR2101010, &metadata, BO_USE_SCANOUT);
 407         drv_modify_combination(drv, DRM_FORMAT_ARGB2101010, &metadata, BO_USE_SCANOUT);
 408         drv_modify_combination(drv, DRM_FORMAT_XBGR2101010, &metadata, BO_USE_SCANOUT);
 409         drv_modify_combination(drv, DRM_FORMAT_XRGB2101010, &metadata, BO_USE_SCANOUT);
 410         return 0;
 411 }
 412
 413 static void amdgpu_close(struct driver *drv)
 414 {
 415         sdma_finish(drv->priv, drv_get_fd(drv));
 416         dri_close(drv);
 417         free(drv->priv);
 418         drv->priv = NULL;
 419 }
 420
 421 static int amdgpu_create_bo_linear(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
 422                                    uint64_t use_flags)
 423 {
 424         int ret;
 425         size_t num_planes;
 426         uint32_t plane, stride;
 427         union drm_amdgpu_gem_create gem_create = { { 0 } };
 428         struct amdgpu_priv *priv = bo->drv->priv;
 429
 430         stride = drv_stride_from_format(format, width, 0);
 431         num_planes = drv_num_planes_from_format(format);
 432
 433         /*
 434          * For multiplane formats, align the stride to 512 to ensure that subsample strides are 256
 435          * aligned. This uses more memory than necessary since the first plane only needs to be
 436          * 256 aligned, but it's acceptable for a short-term fix. It's probably safe for other gpu
 437          * families, but let's restrict it to Raven for now (b/171013552).
 438          * */
 439         if (priv->dev_info.family == AMDGPU_FAMILY_RV && num_planes > 1)
 440                 stride = ALIGN(stride, 512);
 441         else
 442                 stride = ALIGN(stride, 256);
 443
 444         /*
 445          * Currently, allocator used by chrome aligns the height for Encoder/
 446          * Decoder buffers while allocator used by android(gralloc/minigbm)
 447          * doesn't provide any aligment.
 448          *
 449          * See b/153130069
 450          */
 451         if (use_flags & (BO_USE_HW_VIDEO_DECODER | BO_USE_HW_VIDEO_ENCODER))
 452                 height = ALIGN(height, CHROME_HEIGHT_ALIGN);
 453
 454         drv_bo_from_format(bo, stride, height, format);
 455
 456         gem_create.in.bo_size =
 457             ALIGN(bo->meta.total_size, priv->dev_info.virtual_address_alignment);
 458         gem_create.in.alignment = 256;
 459         gem_create.in.domain_flags = 0;
 460
 461         if (use_flags & (BO_USE_LINEAR | BO_USE_SW_MASK))
 462                 gem_create.in.domain_flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 463
 464         gem_create.in.domains = AMDGPU_GEM_DOMAIN_GTT;
 465
 466         /* Scanout in GTT requires USWC, otherwise try to use cachable memory
 467          * for buffers that are read often, because uncacheable reads can be
 468          * very slow. USWC should be faster on the GPU though. */
 469         if ((use_flags & BO_USE_SCANOUT) || !(use_flags & BO_USE_SW_READ_OFTEN))
 470                 gem_create.in.domain_flags |= AMDGPU_GEM_CREATE_CPU_GTT_USWC;
 471
 472         /* Allocate the buffer with the preferred heap. */
 473         ret = drmCommandWriteRead(drv_get_fd(bo->drv), DRM_AMDGPU_GEM_CREATE, &gem_create,
 474                                   sizeof(gem_create));
 475         if (ret < 0)
 476                 return ret;
 477
 478         for (plane = 0; plane < bo->meta.num_planes; plane++)
 479                 bo->handles[plane].u32 = gem_create.out.handle;
 480
 481         bo->meta.format_modifiers[0] = DRM_FORMAT_MOD_LINEAR;
 482
 483         return 0;
 484 }
 485
 486 static int amdgpu_create_bo(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
 487                             uint64_t use_flags)
 488 {
 489         struct combination *combo;
 490
 491         combo = drv_get_combination(bo->drv, format, use_flags);
 492         if (!combo)
 493                 return -EINVAL;
 494
 495         if (combo->metadata.tiling == TILE_TYPE_DRI) {
 496                 bool needs_alignment = false;
 497 #ifdef __ANDROID__
 498                 /*
 499                  * Currently, the gralloc API doesn't differentiate between allocation time and map
 500                  * time strides. A workaround for amdgpu DRI buffers is to always to align to 256 at
 501                  * allocation time.
 502                  *
 503                  * See b/115946221,b/117942643
 504                  */
 505                 if (use_flags & (BO_USE_SW_MASK))
 506                         needs_alignment = true;
 507 #endif
 508                 // See b/122049612
 509                 if (use_flags & (BO_USE_SCANOUT))
 510                         needs_alignment = true;
 511
 512                 if (needs_alignment) {
 513                         uint32_t bytes_per_pixel = drv_bytes_per_pixel_from_format(format, 0);
 514                         width = ALIGN(width, 256 / bytes_per_pixel);
 515                 }
 516
 517                 return dri_bo_create(bo, width, height, format, use_flags);
 518         }
 519
 520         return amdgpu_create_bo_linear(bo, width, height, format, use_flags);
 521 }
 522
 523 static int amdgpu_create_bo_with_modifiers(struct bo *bo, uint32_t width, uint32_t height,
 524                                            uint32_t format, const uint64_t *modifiers,
 525                                            uint32_t count)
 526 {
 527         bool only_use_linear = true;
 528
 529         for (uint32_t i = 0; i < count; ++i)
 530                 if (modifiers[i] != DRM_FORMAT_MOD_LINEAR)
 531                         only_use_linear = false;
 532
 533         if (only_use_linear)
 534                 return amdgpu_create_bo_linear(bo, width, height, format, BO_USE_SCANOUT);
 535
 536         return dri_bo_create_with_modifiers(bo, width, height, format, modifiers, count);
 537 }
 538
 539 static int amdgpu_import_bo(struct bo *bo, struct drv_import_fd_data *data)
 540 {
 541         bool dri_tiling = data->format_modifiers[0] != DRM_FORMAT_MOD_LINEAR;
 542         if (data->format_modifiers[0] == DRM_FORMAT_MOD_INVALID) {
 543                 struct combination *combo;
 544                 combo = drv_get_combination(bo->drv, data->format, data->use_flags);
 545                 if (!combo)
 546                         return -EINVAL;
 547
 548                 dri_tiling = combo->metadata.tiling == TILE_TYPE_DRI;
 549         }
 550
 551         if (dri_tiling)
 552                 return dri_bo_import(bo, data);
 553         else
 554                 return drv_prime_bo_import(bo, data);
 555 }
 556
 557 static int amdgpu_destroy_bo(struct bo *bo)
 558 {
 559         if (bo->priv)
 560                 return dri_bo_destroy(bo);
 561         else
 562                 return drv_gem_bo_destroy(bo);
 563 }
 564
 565 static void *amdgpu_map_bo(struct bo *bo, struct vma *vma, size_t plane, uint32_t map_flags)
 566 {
 567         void *addr = MAP_FAILED;
 568         int ret;
 569         union drm_amdgpu_gem_mmap gem_map = { { 0 } };
 570         struct drm_amdgpu_gem_create_in bo_info = { 0 };
 571         struct drm_amdgpu_gem_op gem_op = { 0 };
 572         uint32_t handle = bo->handles[plane].u32;
 573         struct amdgpu_linear_vma_priv *priv = NULL;
 574         struct amdgpu_priv *drv_priv;
 575
 576         if (bo->priv)
 577                 return dri_bo_map(bo, vma, plane, map_flags);
 578
 579         drv_priv = bo->drv->priv;
 580         gem_op.handle = handle;
 581         gem_op.op = AMDGPU_GEM_OP_GET_GEM_CREATE_INFO;
 582         gem_op.value = (uintptr_t)&bo_info;
 583
 584         ret = drmCommandWriteRead(bo->drv->fd, DRM_AMDGPU_GEM_OP, &gem_op, sizeof(gem_op));
 585         if (ret)
 586                 return MAP_FAILED;
 587
 588         vma->length = bo_info.bo_size;
 589
 590         if (((bo_info.domains & AMDGPU_GEM_DOMAIN_VRAM) ||
 591              (bo_info.domain_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)) &&
 592             drv_priv->sdma_cmdbuf_map) {
 593                 union drm_amdgpu_gem_create gem_create = { { 0 } };
 594
 595                 priv = calloc(1, sizeof(struct amdgpu_linear_vma_priv));
 596                 if (!priv)
 597                         return MAP_FAILED;
 598
 599                 gem_create.in.bo_size = bo_info.bo_size;
 600                 gem_create.in.alignment = 4096;
 601                 gem_create.in.domains = AMDGPU_GEM_DOMAIN_GTT;
 602
 603                 ret = drmCommandWriteRead(bo->drv->fd, DRM_AMDGPU_GEM_CREATE, &gem_create,
 604                                           sizeof(gem_create));
 605                 if (ret < 0) {
 606                         drv_log("GEM create failed\n");
 607                         free(priv);
 608                         return MAP_FAILED;
 609                 }
 610
 611                 priv->map_flags = map_flags;
 612                 handle = priv->handle = gem_create.out.handle;
 613
 614                 ret = sdma_copy(bo->drv->priv, bo->drv->fd, bo->handles[0].u32, priv->handle,
 615                                 bo_info.bo_size);
 616                 if (ret) {
 617                         drv_log("SDMA copy for read failed\n");
 618                         goto fail;
 619                 }
 620         }
 621
 622         gem_map.in.handle = handle;
 623         ret = drmIoctl(bo->drv->fd, DRM_IOCTL_AMDGPU_GEM_MMAP, &gem_map);
 624         if (ret) {
 625                 drv_log("DRM_IOCTL_AMDGPU_GEM_MMAP failed\n");
 626                 goto fail;
 627         }
 628
 629         addr = mmap(0, bo->meta.total_size, drv_get_prot(map_flags), MAP_SHARED, bo->drv->fd,
 630                     gem_map.out.addr_ptr);
 631         if (addr == MAP_FAILED)
 632                 goto fail;
 633
 634         vma->priv = priv;
 635         return addr;
 636
 637 fail:
 638         if (priv) {
 639                 struct drm_gem_close gem_close = { 0 };
 640                 gem_close.handle = priv->handle;
 641                 drmIoctl(bo->drv->fd, DRM_IOCTL_GEM_CLOSE, &gem_close);
 642                 free(priv);
 643         }
 644         return MAP_FAILED;
 645 }
 646
 647 static int amdgpu_unmap_bo(struct bo *bo, struct vma *vma)
 648 {
 649         if (bo->priv)
 650                 return dri_bo_unmap(bo, vma);
 651         else {
 652                 int r = munmap(vma->addr, vma->length);
 653                 if (r)
 654                         return r;
 655
 656                 if (vma->priv) {
 657                         struct amdgpu_linear_vma_priv *priv = vma->priv;
 658                         struct drm_gem_close gem_close = { 0 };
 659
 660                         if (BO_MAP_WRITE & priv->map_flags) {
 661                                 r = sdma_copy(bo->drv->priv, bo->drv->fd, priv->handle,
 662                                               bo->handles[0].u32, vma->length);
 663                                 if (r)
 664                                         return r;
 665                         }
 666
 667                         gem_close.handle = priv->handle;
 668                         r = drmIoctl(bo->drv->fd, DRM_IOCTL_GEM_CLOSE, &gem_close);
 669                 }
 670
 671                 return 0;
 672         }
 673 }
 674
 675 static int amdgpu_bo_invalidate(struct bo *bo, struct mapping *mapping)
 676 {
 677         int ret;
 678         union drm_amdgpu_gem_wait_idle wait_idle = { { 0 } };
 679
 680         if (bo->priv)
 681                 return 0;
 682
 683         wait_idle.in.handle = bo->handles[0].u32;
 684         wait_idle.in.timeout = AMDGPU_TIMEOUT_INFINITE;
 685
 686         ret = drmCommandWriteRead(bo->drv->fd, DRM_AMDGPU_GEM_WAIT_IDLE, &wait_idle,
 687                                   sizeof(wait_idle));
 688
 689         if (ret < 0) {
 690                 drv_log("DRM_AMDGPU_GEM_WAIT_IDLE failed with %d\n", ret);
 691                 return ret;
 692         }
 693
 694         if (ret == 0 && wait_idle.out.status)
 695                 drv_log("DRM_AMDGPU_GEM_WAIT_IDLE BO is busy\n");
 696
 697         return 0;
 698 }
 699
 700 static uint32_t amdgpu_resolve_format(struct driver *drv, uint32_t format, uint64_t use_flags)
 701 {
 702         switch (format) {
 703         case DRM_FORMAT_FLEX_IMPLEMENTATION_DEFINED:
 704                 /* Camera subsystem requires NV12. */
 705                 if (use_flags & (BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE))
 706                         return DRM_FORMAT_NV12;
 707                 /*HACK: See b/28671744 */
 708                 return DRM_FORMAT_XBGR8888;
 709         case DRM_FORMAT_FLEX_YCbCr_420_888:
 710                 return DRM_FORMAT_NV12;
 711         default:
 712                 return format;
 713         }
 714 }
 715
 716 const struct backend backend_amdgpu = {
 717         .name = "amdgpu",
 718         .init = amdgpu_init,
 719         .close = amdgpu_close,
 720         .bo_create = amdgpu_create_bo,
 721         .bo_create_with_modifiers = amdgpu_create_bo_with_modifiers,
 722         .bo_destroy = amdgpu_destroy_bo,
 723         .bo_import = amdgpu_import_bo,
 724         .bo_map = amdgpu_map_bo,
 725         .bo_unmap = amdgpu_unmap_bo,
 726         .bo_invalidate = amdgpu_bo_invalidate,
 727         .resolve_format = amdgpu_resolve_format,
 728         .num_planes_from_modifier = dri_num_planes_from_modifier,
 729 };
 730
 731 #endif