amdgpu.c

   1 /*
   2  * Copyright 2016 The Chromium OS Authors. All rights reserved.
   3  * Use of this source code is governed by a BSD-style license that can be
   4  * found in the LICENSE file.
   5  */
   6 #ifdef DRV_AMDGPU
   7 #include <amdgpu.h>
   8 #include <amdgpu_drm.h>
   9 #include <errno.h>
  10 #include <stdio.h>
  11 #include <stdlib.h>
  12 #include <string.h>
  13 #include <sys/mman.h>
  14 #include <xf86drm.h>
  15
  16 #include "addrinterface.h"
  17 #include "drv_priv.h"
  18 #include "helpers.h"
  19 #include "util.h"
  20
  21 #ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
  22 #define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
  23 #endif
  24
  25 // clang-format off
  26 #define mmCC_RB_BACKEND_DISABLE         0x263d
  27 #define mmGB_TILE_MODE0                 0x2644
  28 #define mmGB_MACROTILE_MODE0            0x2664
  29 #define mmGB_ADDR_CONFIG                0x263e
  30 #define mmMC_ARB_RAMCFG                 0x9d8
  31
  32 enum {
  33         FAMILY_UNKNOWN,
  34         FAMILY_SI,
  35         FAMILY_CI,
  36         FAMILY_KV,
  37         FAMILY_VI,
  38         FAMILY_CZ,
  39         FAMILY_PI,
  40         FAMILY_LAST,
  41 };
  42 // clang-format on
  43
  44 const static uint32_t render_target_formats[] = { DRM_FORMAT_ABGR8888, DRM_FORMAT_ARGB8888,
  45                                                   DRM_FORMAT_RGB565, DRM_FORMAT_XBGR8888,
  46                                                   DRM_FORMAT_XRGB8888 };
  47
  48 const static uint32_t texture_source_formats[] = { DRM_FORMAT_GR88, DRM_FORMAT_R8, DRM_FORMAT_NV21,
  49                                                    DRM_FORMAT_NV12, DRM_FORMAT_YVU420_ANDROID };
  50
  51 static int amdgpu_set_metadata(int fd, uint32_t handle, struct amdgpu_bo_metadata *info)
  52 {
  53         struct drm_amdgpu_gem_metadata args = { 0 };
  54
  55         if (!info)
  56                 return -EINVAL;
  57
  58         args.handle = handle;
  59         args.op = AMDGPU_GEM_METADATA_OP_SET_METADATA;
  60         args.data.flags = info->flags;
  61         args.data.tiling_info = info->tiling_info;
  62
  63         if (info->size_metadata > sizeof(args.data.data))
  64                 return -EINVAL;
  65
  66         if (info->size_metadata) {
  67                 args.data.data_size_bytes = info->size_metadata;
  68                 memcpy(args.data.data, info->umd_metadata, info->size_metadata);
  69         }
  70
  71         return drmCommandWriteRead(fd, DRM_AMDGPU_GEM_METADATA, &args, sizeof(args));
  72 }
  73
  74 static int amdgpu_read_mm_regs(int fd, unsigned dword_offset, unsigned count, uint32_t instance,
  75                                uint32_t flags, uint32_t *values)
  76 {
  77         struct drm_amdgpu_info request;
  78
  79         memset(&request, 0, sizeof(request));
  80         request.return_pointer = (uintptr_t)values;
  81         request.return_size = count * sizeof(uint32_t);
  82         request.query = AMDGPU_INFO_READ_MMR_REG;
  83         request.read_mmr_reg.dword_offset = dword_offset;
  84         request.read_mmr_reg.count = count;
  85         request.read_mmr_reg.instance = instance;
  86         request.read_mmr_reg.flags = flags;
  87
  88         return drmCommandWrite(fd, DRM_AMDGPU_INFO, &request, sizeof(struct drm_amdgpu_info));
  89 }
  90
  91 static int amdgpu_query_gpu(int fd, struct amdgpu_gpu_info *gpu_info)
  92 {
  93         int ret;
  94         uint32_t instance;
  95
  96         if (!gpu_info)
  97                 return -EINVAL;
  98
  99         instance = AMDGPU_INFO_MMR_SH_INDEX_MASK << AMDGPU_INFO_MMR_SH_INDEX_SHIFT;
 100
 101         ret = amdgpu_read_mm_regs(fd, mmCC_RB_BACKEND_DISABLE, 1, instance, 0,
 102                                   &gpu_info->backend_disable[0]);
 103         if (ret)
 104                 return ret;
 105         /* extract bitfield CC_RB_BACKEND_DISABLE.BACKEND_DISABLE */
 106         gpu_info->backend_disable[0] = (gpu_info->backend_disable[0] >> 16) & 0xff;
 107
 108         ret = amdgpu_read_mm_regs(fd, mmGB_TILE_MODE0, 32, 0xffffffff, 0, gpu_info->gb_tile_mode);
 109         if (ret)
 110                 return ret;
 111
 112         ret = amdgpu_read_mm_regs(fd, mmGB_MACROTILE_MODE0, 16, 0xffffffff, 0,
 113                                   gpu_info->gb_macro_tile_mode);
 114         if (ret)
 115                 return ret;
 116
 117         ret = amdgpu_read_mm_regs(fd, mmGB_ADDR_CONFIG, 1, 0xffffffff, 0, &gpu_info->gb_addr_cfg);
 118         if (ret)
 119                 return ret;
 120
 121         ret = amdgpu_read_mm_regs(fd, mmMC_ARB_RAMCFG, 1, 0xffffffff, 0, &gpu_info->mc_arb_ramcfg);
 122         if (ret)
 123                 return ret;
 124
 125         return 0;
 126 }
 127
 128 static void *ADDR_API alloc_sys_mem(const ADDR_ALLOCSYSMEM_INPUT *in)
 129 {
 130         return malloc(in->sizeInBytes);
 131 }
 132
 133 static ADDR_E_RETURNCODE ADDR_API free_sys_mem(const ADDR_FREESYSMEM_INPUT *in)
 134 {
 135         free(in->pVirtAddr);
 136         return ADDR_OK;
 137 }
 138
 139 static int amdgpu_addrlib_compute(void *addrlib, uint32_t width, uint32_t height, uint32_t format,
 140                                   uint64_t use_flags, uint32_t *tiling_flags,
 141                                   ADDR_COMPUTE_SURFACE_INFO_OUTPUT *addr_out)
 142 {
 143         ADDR_COMPUTE_SURFACE_INFO_INPUT addr_surf_info_in = { 0 };
 144         ADDR_TILEINFO addr_tile_info = { 0 };
 145         ADDR_TILEINFO addr_tile_info_out = { 0 };
 146         uint32_t bits_per_pixel;
 147
 148         addr_surf_info_in.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_INPUT);
 149
 150         /* Set the requested tiling mode. */
 151         addr_surf_info_in.tileMode = ADDR_TM_2D_TILED_THIN1;
 152         if (use_flags &
 153             (BO_USE_CURSOR | BO_USE_LINEAR | BO_USE_SW_READ_OFTEN | BO_USE_SW_WRITE_OFTEN))
 154                 addr_surf_info_in.tileMode = ADDR_TM_LINEAR_ALIGNED;
 155         else if (width <= 16 || height <= 16)
 156                 addr_surf_info_in.tileMode = ADDR_TM_1D_TILED_THIN1;
 157
 158         bits_per_pixel = drv_stride_from_format(format, 1, 0) * 8;
 159         /* Bits per pixel should be calculated from format*/
 160         addr_surf_info_in.bpp = bits_per_pixel;
 161         addr_surf_info_in.numSamples = 1;
 162         addr_surf_info_in.width = width;
 163         addr_surf_info_in.height = height;
 164         addr_surf_info_in.numSlices = 1;
 165         addr_surf_info_in.pTileInfo = &addr_tile_info;
 166         addr_surf_info_in.tileIndex = -1;
 167
 168         /* This disables incorrect calculations (hacks) in addrlib. */
 169         addr_surf_info_in.flags.noStencil = 1;
 170
 171         /* Set the micro tile type. */
 172         if (use_flags & BO_USE_SCANOUT)
 173                 addr_surf_info_in.tileType = ADDR_DISPLAYABLE;
 174         else
 175                 addr_surf_info_in.tileType = ADDR_NON_DISPLAYABLE;
 176
 177         addr_out->size = sizeof(ADDR_COMPUTE_SURFACE_INFO_OUTPUT);
 178         addr_out->pTileInfo = &addr_tile_info_out;
 179
 180         if (AddrComputeSurfaceInfo(addrlib, &addr_surf_info_in, addr_out) != ADDR_OK)
 181                 return -EINVAL;
 182
 183         ADDR_CONVERT_TILEINFOTOHW_INPUT s_in = { 0 };
 184         ADDR_CONVERT_TILEINFOTOHW_OUTPUT s_out = { 0 };
 185         ADDR_TILEINFO s_tile_hw_info_out = { 0 };
 186
 187         s_in.size = sizeof(ADDR_CONVERT_TILEINFOTOHW_INPUT);
 188         /* Convert from real value to HW value */
 189         s_in.reverse = 0;
 190         s_in.pTileInfo = &addr_tile_info_out;
 191         s_in.tileIndex = -1;
 192
 193         s_out.size = sizeof(ADDR_CONVERT_TILEINFOTOHW_OUTPUT);
 194         s_out.pTileInfo = &s_tile_hw_info_out;
 195
 196         if (AddrConvertTileInfoToHW(addrlib, &s_in, &s_out) != ADDR_OK)
 197                 return -EINVAL;
 198
 199         if (addr_out->tileMode >= ADDR_TM_2D_TILED_THIN1)
 200                 /* 2D_TILED_THIN1 */
 201                 *tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 4);
 202         else if (addr_out->tileMode >= ADDR_TM_1D_TILED_THIN1)
 203                 /* 1D_TILED_THIN1 */
 204                 *tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 2);
 205         else
 206                 /* LINEAR_ALIGNED */
 207                 *tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 1);
 208
 209         *tiling_flags |= AMDGPU_TILING_SET(BANK_WIDTH, drv_log_base2(addr_tile_info_out.bankWidth));
 210         *tiling_flags |=
 211             AMDGPU_TILING_SET(BANK_HEIGHT, drv_log_base2(addr_tile_info_out.bankHeight));
 212         *tiling_flags |= AMDGPU_TILING_SET(TILE_SPLIT, s_tile_hw_info_out.tileSplitBytes);
 213         *tiling_flags |= AMDGPU_TILING_SET(MACRO_TILE_ASPECT,
 214                                            drv_log_base2(addr_tile_info_out.macroAspectRatio));
 215         *tiling_flags |= AMDGPU_TILING_SET(PIPE_CONFIG, s_tile_hw_info_out.pipeConfig);
 216         *tiling_flags |= AMDGPU_TILING_SET(NUM_BANKS, s_tile_hw_info_out.banks);
 217
 218         return 0;
 219 }
 220
 221 static void *amdgpu_addrlib_init(int fd)
 222 {
 223         int ret;
 224         ADDR_CREATE_INPUT addr_create_input = { 0 };
 225         ADDR_CREATE_OUTPUT addr_create_output = { 0 };
 226         ADDR_REGISTER_VALUE reg_value = { 0 };
 227         ADDR_CREATE_FLAGS create_flags = { { 0 } };
 228         ADDR_E_RETURNCODE addr_ret;
 229
 230         addr_create_input.size = sizeof(ADDR_CREATE_INPUT);
 231         addr_create_output.size = sizeof(ADDR_CREATE_OUTPUT);
 232
 233         struct amdgpu_gpu_info gpu_info = { 0 };
 234
 235         ret = amdgpu_query_gpu(fd, &gpu_info);
 236
 237         if (ret) {
 238                 fprintf(stderr, "[%s]failed with error =%d\n", __func__, ret);
 239                 return NULL;
 240         }
 241
 242         reg_value.noOfBanks = gpu_info.mc_arb_ramcfg & 0x3;
 243         reg_value.gbAddrConfig = gpu_info.gb_addr_cfg;
 244         reg_value.noOfRanks = (gpu_info.mc_arb_ramcfg & 0x4) >> 2;
 245
 246         reg_value.backendDisables = gpu_info.backend_disable[0];
 247         reg_value.pTileConfig = gpu_info.gb_tile_mode;
 248         reg_value.noOfEntries = sizeof(gpu_info.gb_tile_mode) / sizeof(gpu_info.gb_tile_mode[0]);
 249         reg_value.pMacroTileConfig = gpu_info.gb_macro_tile_mode;
 250         reg_value.noOfMacroEntries =
 251             sizeof(gpu_info.gb_macro_tile_mode) / sizeof(gpu_info.gb_macro_tile_mode[0]);
 252         create_flags.value = 0;
 253         create_flags.useTileIndex = 1;
 254
 255         addr_create_input.chipEngine = CIASICIDGFXENGINE_SOUTHERNISLAND;
 256
 257         addr_create_input.chipFamily = FAMILY_CZ;
 258         addr_create_input.createFlags = create_flags;
 259         addr_create_input.callbacks.allocSysMem = alloc_sys_mem;
 260         addr_create_input.callbacks.freeSysMem = free_sys_mem;
 261         addr_create_input.callbacks.debugPrint = 0;
 262         addr_create_input.regValue = reg_value;
 263
 264         addr_ret = AddrCreate(&addr_create_input, &addr_create_output);
 265
 266         if (addr_ret != ADDR_OK) {
 267                 fprintf(stderr, "[%s]failed error =%d\n", __func__, addr_ret);
 268                 return NULL;
 269         }
 270
 271         return addr_create_output.hLib;
 272 }
 273
 274 static int amdgpu_init(struct driver *drv)
 275 {
 276         void *addrlib;
 277         struct format_metadata metadata;
 278         uint64_t use_flags = BO_USE_RENDER_MASK;
 279
 280         addrlib = amdgpu_addrlib_init(drv_get_fd(drv));
 281         if (!addrlib)
 282                 return -1;
 283
 284         drv->priv = addrlib;
 285
 286         drv_add_combinations(drv, texture_source_formats, ARRAY_SIZE(texture_source_formats),
 287                              &LINEAR_METADATA, BO_USE_TEXTURE_MASK);
 288
 289         /* YUV format for camera */
 290         drv_modify_combination(drv, DRM_FORMAT_NV12, &LINEAR_METADATA,
 291                                BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE);
 292         /*
 293          * R8 format is used for Android's HAL_PIXEL_FORMAT_BLOB and is used for JPEG snapshots
 294          * from camera.
 295          */
 296         drv_modify_combination(drv, DRM_FORMAT_R8, &LINEAR_METADATA,
 297                                BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE);
 298
 299         drv_modify_combination(drv, DRM_FORMAT_NV21, &LINEAR_METADATA, BO_USE_SCANOUT);
 300         drv_modify_combination(drv, DRM_FORMAT_NV12, &LINEAR_METADATA, BO_USE_SCANOUT);
 301
 302         metadata.tiling = ADDR_DISPLAYABLE << 16 | ADDR_TM_LINEAR_ALIGNED;
 303         metadata.priority = 2;
 304         metadata.modifier = DRM_FORMAT_MOD_LINEAR;
 305
 306         drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
 307                              &metadata, use_flags);
 308
 309         drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
 310         drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
 311         drv_modify_combination(drv, DRM_FORMAT_XBGR8888, &metadata, BO_USE_SCANOUT);
 312
 313         metadata.tiling = ADDR_NON_DISPLAYABLE << 16 | ADDR_TM_LINEAR_ALIGNED;
 314         metadata.priority = 3;
 315         metadata.modifier = DRM_FORMAT_MOD_LINEAR;
 316
 317         drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
 318                              &metadata, use_flags);
 319
 320         use_flags &= ~BO_USE_SW_WRITE_OFTEN;
 321         use_flags &= ~BO_USE_SW_READ_OFTEN;
 322         use_flags &= ~BO_USE_LINEAR;
 323
 324         metadata.tiling = ADDR_DISPLAYABLE << 16 | ADDR_TM_2D_TILED_THIN1;
 325         metadata.priority = 4;
 326
 327         drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
 328                              &metadata, use_flags);
 329
 330         drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_SCANOUT);
 331         drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_SCANOUT);
 332         drv_modify_combination(drv, DRM_FORMAT_XBGR8888, &metadata, BO_USE_SCANOUT);
 333
 334         metadata.tiling = ADDR_NON_DISPLAYABLE << 16 | ADDR_TM_2D_TILED_THIN1;
 335         metadata.priority = 5;
 336
 337         drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
 338                              &metadata, use_flags);
 339
 340         return 0;
 341 }
 342
 343 static void amdgpu_close(struct driver *drv)
 344 {
 345         AddrDestroy(drv->priv);
 346         drv->priv = NULL;
 347 }
 348
 349 static int amdgpu_bo_create(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
 350                             uint64_t use_flags)
 351 {
 352         void *addrlib = bo->drv->priv;
 353         union drm_amdgpu_gem_create gem_create;
 354         struct amdgpu_bo_metadata metadata = { 0 };
 355         ADDR_COMPUTE_SURFACE_INFO_OUTPUT addr_out = { 0 };
 356         uint32_t tiling_flags = 0;
 357         size_t plane;
 358         int ret;
 359
 360         if (format == DRM_FORMAT_NV12 || format == DRM_FORMAT_NV21) {
 361                 drv_bo_from_format(bo, ALIGN(width, 64), height, format);
 362         } else if (format == DRM_FORMAT_YVU420_ANDROID) {
 363                 drv_bo_from_format(bo, ALIGN(width, 128), height, format);
 364         } else {
 365                 if (amdgpu_addrlib_compute(addrlib, width, height, format, use_flags, &tiling_flags,
 366                                            &addr_out) < 0)
 367                         return -EINVAL;
 368
 369                 bo->tiling = tiling_flags;
 370                 /* RGB has 1 plane only */
 371                 bo->offsets[0] = 0;
 372                 bo->total_size = bo->sizes[0] = addr_out.surfSize;
 373                 bo->strides[0] = addr_out.pixelPitch * DIV_ROUND_UP(addr_out.pixelBits, 8);
 374         }
 375
 376         memset(&gem_create, 0, sizeof(gem_create));
 377
 378         gem_create.in.bo_size = bo->total_size;
 379         gem_create.in.alignment = addr_out.baseAlign;
 380         /* Set the placement. */
 381
 382         gem_create.in.domain_flags = 0;
 383         if (use_flags & (BO_USE_LINEAR | BO_USE_SW))
 384                 gem_create.in.domain_flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 385
 386         if (use_flags & (BO_USE_SCANOUT | BO_USE_CURSOR)) {
 387                 /* TODO(dbehr) do not use VRAM after we enable display VM */
 388                 gem_create.in.domains = AMDGPU_GEM_DOMAIN_VRAM;
 389         } else {
 390                 gem_create.in.domains = AMDGPU_GEM_DOMAIN_GTT;
 391                 if (!(use_flags & BO_USE_SW_READ_OFTEN))
 392                         gem_create.in.domain_flags |= AMDGPU_GEM_CREATE_CPU_GTT_USWC;
 393         }
 394
 395         /* Allocate the buffer with the preferred heap. */
 396         ret = drmCommandWriteRead(drv_get_fd(bo->drv), DRM_AMDGPU_GEM_CREATE, &gem_create,
 397                                   sizeof(gem_create));
 398
 399         if (ret < 0)
 400                 return ret;
 401
 402         metadata.tiling_info = tiling_flags;
 403
 404         for (plane = 0; plane < bo->num_planes; plane++)
 405                 bo->handles[plane].u32 = gem_create.out.handle;
 406
 407         ret = amdgpu_set_metadata(drv_get_fd(bo->drv), bo->handles[0].u32, &metadata);
 408
 409         return ret;
 410 }
 411
 412 static void *amdgpu_bo_map(struct bo *bo, struct vma *vma, size_t plane, uint32_t map_flags)
 413 {
 414         int ret;
 415         union drm_amdgpu_gem_mmap gem_map;
 416
 417         memset(&gem_map, 0, sizeof(gem_map));
 418         gem_map.in.handle = bo->handles[plane].u32;
 419
 420         ret = drmIoctl(bo->drv->fd, DRM_IOCTL_AMDGPU_GEM_MMAP, &gem_map);
 421         if (ret) {
 422                 fprintf(stderr, "drv: DRM_IOCTL_AMDGPU_GEM_MMAP failed\n");
 423                 return MAP_FAILED;
 424         }
 425
 426         vma->length = bo->total_size;
 427
 428         return mmap(0, bo->total_size, drv_get_prot(map_flags), MAP_SHARED, bo->drv->fd,
 429                     gem_map.out.addr_ptr);
 430 }
 431
 432 static uint32_t amdgpu_resolve_format(uint32_t format, uint64_t use_flags)
 433 {
 434         switch (format) {
 435         case DRM_FORMAT_FLEX_IMPLEMENTATION_DEFINED:
 436                 /* Camera subsystem requires NV12. */
 437                 if (use_flags & (BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE))
 438                         return DRM_FORMAT_NV12;
 439                 /*HACK: See b/28671744 */
 440                 return DRM_FORMAT_XBGR8888;
 441         case DRM_FORMAT_FLEX_YCbCr_420_888:
 442                 return DRM_FORMAT_NV12;
 443         default:
 444                 return format;
 445         }
 446 }
 447
 448 const struct backend backend_amdgpu = {
 449         .name = "amdgpu",
 450         .init = amdgpu_init,
 451         .close = amdgpu_close,
 452         .bo_create = amdgpu_bo_create,
 453         .bo_destroy = drv_gem_bo_destroy,
 454         .bo_import = drv_prime_bo_import,
 455         .bo_map = amdgpu_bo_map,
 456         .bo_unmap = drv_bo_munmap,
 457         .resolve_format = amdgpu_resolve_format,
 458 };
 459
 460 #endif