2 * Copyright 2016 The Chromium OS Authors. All rights reserved.
3 * Use of this source code is governed by a BSD-style license that can be
4 * found in the LICENSE file.
8 #include <amdgpu_drm.h>
16 #include "addrinterface.h"
21 #ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
22 #define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
26 #define mmCC_RB_BACKEND_DISABLE 0x263d
27 #define mmGB_TILE_MODE0 0x2644
28 #define mmGB_MACROTILE_MODE0 0x2664
29 #define mmGB_ADDR_CONFIG 0x263e
30 #define mmMC_ARB_RAMCFG 0x9d8
44 const static uint32_t render_target_formats[] = { DRM_FORMAT_ARGB8888, DRM_FORMAT_XBGR8888,
45 DRM_FORMAT_XRGB8888 };
47 const static uint32_t texture_source_formats[] = { DRM_FORMAT_NV21, DRM_FORMAT_NV12 };
49 static int amdgpu_set_metadata(int fd, uint32_t handle, struct amdgpu_bo_metadata *info)
51 struct drm_amdgpu_gem_metadata args = { 0 };
57 args.op = AMDGPU_GEM_METADATA_OP_SET_METADATA;
58 args.data.flags = info->flags;
59 args.data.tiling_info = info->tiling_info;
61 if (info->size_metadata > sizeof(args.data.data))
64 if (info->size_metadata) {
65 args.data.data_size_bytes = info->size_metadata;
66 memcpy(args.data.data, info->umd_metadata, info->size_metadata);
69 return drmCommandWriteRead(fd, DRM_AMDGPU_GEM_METADATA, &args, sizeof(args));
72 static int amdgpu_read_mm_regs(int fd, unsigned dword_offset, unsigned count, uint32_t instance,
73 uint32_t flags, uint32_t *values)
75 struct drm_amdgpu_info request;
77 memset(&request, 0, sizeof(request));
78 request.return_pointer = (uintptr_t)values;
79 request.return_size = count * sizeof(uint32_t);
80 request.query = AMDGPU_INFO_READ_MMR_REG;
81 request.read_mmr_reg.dword_offset = dword_offset;
82 request.read_mmr_reg.count = count;
83 request.read_mmr_reg.instance = instance;
84 request.read_mmr_reg.flags = flags;
86 return drmCommandWrite(fd, DRM_AMDGPU_INFO, &request, sizeof(struct drm_amdgpu_info));
89 static int amdgpu_query_gpu(int fd, struct amdgpu_gpu_info *gpu_info)
97 instance = AMDGPU_INFO_MMR_SH_INDEX_MASK << AMDGPU_INFO_MMR_SH_INDEX_SHIFT;
99 ret = amdgpu_read_mm_regs(fd, mmCC_RB_BACKEND_DISABLE, 1, instance, 0,
100 &gpu_info->backend_disable[0]);
103 /* extract bitfield CC_RB_BACKEND_DISABLE.BACKEND_DISABLE */
104 gpu_info->backend_disable[0] = (gpu_info->backend_disable[0] >> 16) & 0xff;
106 ret = amdgpu_read_mm_regs(fd, mmGB_TILE_MODE0, 32, 0xffffffff, 0, gpu_info->gb_tile_mode);
110 ret = amdgpu_read_mm_regs(fd, mmGB_MACROTILE_MODE0, 16, 0xffffffff, 0,
111 gpu_info->gb_macro_tile_mode);
115 ret = amdgpu_read_mm_regs(fd, mmGB_ADDR_CONFIG, 1, 0xffffffff, 0, &gpu_info->gb_addr_cfg);
119 ret = amdgpu_read_mm_regs(fd, mmMC_ARB_RAMCFG, 1, 0xffffffff, 0, &gpu_info->mc_arb_ramcfg);
126 static void *ADDR_API alloc_sys_mem(const ADDR_ALLOCSYSMEM_INPUT *in)
128 return malloc(in->sizeInBytes);
131 static ADDR_E_RETURNCODE ADDR_API free_sys_mem(const ADDR_FREESYSMEM_INPUT *in)
137 static int amdgpu_addrlib_compute(void *addrlib, uint32_t width, uint32_t height, uint32_t format,
138 uint32_t usage, uint32_t *tiling_flags,
139 ADDR_COMPUTE_SURFACE_INFO_OUTPUT *addr_out)
141 ADDR_COMPUTE_SURFACE_INFO_INPUT addr_surf_info_in = { 0 };
142 ADDR_TILEINFO addr_tile_info = { 0 };
143 ADDR_TILEINFO addr_tile_info_out = { 0 };
144 uint32_t bits_per_pixel;
146 addr_surf_info_in.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_INPUT);
148 /* Set the requested tiling mode. */
149 addr_surf_info_in.tileMode = ADDR_TM_2D_TILED_THIN1;
150 if (usage & (BO_USE_CURSOR | BO_USE_LINEAR | BO_USE_SW_READ_OFTEN | BO_USE_SW_WRITE_OFTEN))
151 addr_surf_info_in.tileMode = ADDR_TM_LINEAR_ALIGNED;
152 else if (width <= 16 || height <= 16)
153 addr_surf_info_in.tileMode = ADDR_TM_1D_TILED_THIN1;
155 bits_per_pixel = drv_stride_from_format(format, 1, 0) * 8;
156 /* Bits per pixel should be calculated from format*/
157 addr_surf_info_in.bpp = bits_per_pixel;
158 addr_surf_info_in.numSamples = 1;
159 addr_surf_info_in.width = width;
160 addr_surf_info_in.height = height;
161 addr_surf_info_in.numSlices = 1;
162 addr_surf_info_in.pTileInfo = &addr_tile_info;
163 addr_surf_info_in.tileIndex = -1;
165 /* This disables incorrect calculations (hacks) in addrlib. */
166 addr_surf_info_in.flags.noStencil = 1;
168 /* Set the micro tile type. */
169 if (usage & BO_USE_SCANOUT)
170 addr_surf_info_in.tileType = ADDR_DISPLAYABLE;
172 addr_surf_info_in.tileType = ADDR_NON_DISPLAYABLE;
174 addr_out->size = sizeof(ADDR_COMPUTE_SURFACE_INFO_OUTPUT);
175 addr_out->pTileInfo = &addr_tile_info_out;
177 if (AddrComputeSurfaceInfo(addrlib, &addr_surf_info_in, addr_out) != ADDR_OK)
180 ADDR_CONVERT_TILEINFOTOHW_INPUT s_in = { 0 };
181 ADDR_CONVERT_TILEINFOTOHW_OUTPUT s_out = { 0 };
182 ADDR_TILEINFO s_tile_hw_info_out = { 0 };
184 s_in.size = sizeof(ADDR_CONVERT_TILEINFOTOHW_INPUT);
185 /* Convert from real value to HW value */
187 s_in.pTileInfo = &addr_tile_info_out;
190 s_out.size = sizeof(ADDR_CONVERT_TILEINFOTOHW_OUTPUT);
191 s_out.pTileInfo = &s_tile_hw_info_out;
193 if (AddrConvertTileInfoToHW(addrlib, &s_in, &s_out) != ADDR_OK)
196 if (addr_out->tileMode >= ADDR_TM_2D_TILED_THIN1)
198 *tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 4);
199 else if (addr_out->tileMode >= ADDR_TM_1D_TILED_THIN1)
201 *tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 2);
204 *tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 1);
206 *tiling_flags |= AMDGPU_TILING_SET(BANK_WIDTH, drv_log_base2(addr_tile_info_out.bankWidth));
208 AMDGPU_TILING_SET(BANK_HEIGHT, drv_log_base2(addr_tile_info_out.bankHeight));
209 *tiling_flags |= AMDGPU_TILING_SET(TILE_SPLIT, s_tile_hw_info_out.tileSplitBytes);
210 *tiling_flags |= AMDGPU_TILING_SET(MACRO_TILE_ASPECT,
211 drv_log_base2(addr_tile_info_out.macroAspectRatio));
212 *tiling_flags |= AMDGPU_TILING_SET(PIPE_CONFIG, s_tile_hw_info_out.pipeConfig);
213 *tiling_flags |= AMDGPU_TILING_SET(NUM_BANKS, s_tile_hw_info_out.banks);
218 static void *amdgpu_addrlib_init(int fd)
221 ADDR_CREATE_INPUT addr_create_input = { 0 };
222 ADDR_CREATE_OUTPUT addr_create_output = { 0 };
223 ADDR_REGISTER_VALUE reg_value = { 0 };
224 ADDR_CREATE_FLAGS create_flags = { { 0 } };
225 ADDR_E_RETURNCODE addr_ret;
227 addr_create_input.size = sizeof(ADDR_CREATE_INPUT);
228 addr_create_output.size = sizeof(ADDR_CREATE_OUTPUT);
230 struct amdgpu_gpu_info gpu_info = { 0 };
232 ret = amdgpu_query_gpu(fd, &gpu_info);
235 fprintf(stderr, "[%s]failed with error =%d\n", __func__, ret);
239 reg_value.noOfBanks = gpu_info.mc_arb_ramcfg & 0x3;
240 reg_value.gbAddrConfig = gpu_info.gb_addr_cfg;
241 reg_value.noOfRanks = (gpu_info.mc_arb_ramcfg & 0x4) >> 2;
243 reg_value.backendDisables = gpu_info.backend_disable[0];
244 reg_value.pTileConfig = gpu_info.gb_tile_mode;
245 reg_value.noOfEntries = sizeof(gpu_info.gb_tile_mode) / sizeof(gpu_info.gb_tile_mode[0]);
246 reg_value.pMacroTileConfig = gpu_info.gb_macro_tile_mode;
247 reg_value.noOfMacroEntries =
248 sizeof(gpu_info.gb_macro_tile_mode) / sizeof(gpu_info.gb_macro_tile_mode[0]);
249 create_flags.value = 0;
250 create_flags.useTileIndex = 1;
252 addr_create_input.chipEngine = CIASICIDGFXENGINE_SOUTHERNISLAND;
254 addr_create_input.chipFamily = FAMILY_CZ;
255 addr_create_input.createFlags = create_flags;
256 addr_create_input.callbacks.allocSysMem = alloc_sys_mem;
257 addr_create_input.callbacks.freeSysMem = free_sys_mem;
258 addr_create_input.callbacks.debugPrint = 0;
259 addr_create_input.regValue = reg_value;
261 addr_ret = AddrCreate(&addr_create_input, &addr_create_output);
263 if (addr_ret != ADDR_OK) {
264 fprintf(stderr, "[%s]failed error =%d\n", __func__, addr_ret);
268 return addr_create_output.hLib;
271 static int amdgpu_init(struct driver *drv)
275 struct format_metadata metadata;
276 uint32_t flags = BO_USE_RENDER_MASK;
278 addrlib = amdgpu_addrlib_init(drv_get_fd(drv));
284 ret = drv_add_combinations(drv, texture_source_formats, ARRAY_SIZE(texture_source_formats),
285 &LINEAR_METADATA, BO_USE_TEXTURE_MASK);
289 drv_modify_combination(drv, DRM_FORMAT_NV21, &LINEAR_METADATA, BO_USE_SCANOUT);
290 drv_modify_combination(drv, DRM_FORMAT_NV12, &LINEAR_METADATA, BO_USE_SCANOUT);
292 metadata.tiling = ADDR_DISPLAYABLE << 16 | ADDR_TM_LINEAR_ALIGNED;
293 metadata.priority = 2;
294 metadata.modifier = DRM_FORMAT_MOD_NONE;
296 ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
301 drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
302 drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
303 drv_modify_combination(drv, DRM_FORMAT_XBGR8888, &metadata, BO_USE_SCANOUT);
305 metadata.tiling = ADDR_NON_DISPLAYABLE << 16 | ADDR_TM_LINEAR_ALIGNED;
306 metadata.priority = 3;
307 metadata.modifier = DRM_FORMAT_MOD_NONE;
309 ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
314 flags &= ~BO_USE_SW_WRITE_OFTEN;
315 flags &= ~BO_USE_SW_READ_OFTEN;
316 flags &= ~BO_USE_LINEAR;
318 metadata.tiling = ADDR_DISPLAYABLE << 16 | ADDR_TM_2D_TILED_THIN1;
319 metadata.priority = 4;
321 ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
326 drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_SCANOUT);
327 drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_SCANOUT);
328 drv_modify_combination(drv, DRM_FORMAT_XBGR8888, &metadata, BO_USE_SCANOUT);
330 metadata.tiling = ADDR_NON_DISPLAYABLE << 16 | ADDR_TM_2D_TILED_THIN1;
331 metadata.priority = 5;
333 ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
341 static void amdgpu_close(struct driver *drv)
343 AddrDestroy(drv->priv);
347 static int amdgpu_bo_create(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
350 void *addrlib = bo->drv->priv;
351 union drm_amdgpu_gem_create gem_create;
352 struct amdgpu_bo_metadata metadata = { 0 };
353 ADDR_COMPUTE_SURFACE_INFO_OUTPUT addr_out = { 0 };
354 uint32_t tiling_flags = 0;
355 uint32_t gem_create_flags = 0;
359 if (format == DRM_FORMAT_NV12 || format == DRM_FORMAT_NV21) {
360 drv_bo_from_format(bo, ALIGN(width, 64), height, format);
362 if (amdgpu_addrlib_compute(addrlib, width, height, format, usage, &tiling_flags,
366 bo->tiling = tiling_flags;
367 /* RGB has 1 plane only */
369 bo->total_size = bo->sizes[0] = addr_out.surfSize;
370 bo->strides[0] = addr_out.pixelPitch * DIV_ROUND_UP(addr_out.pixelBits, 8);
373 if (usage & (BO_USE_CURSOR | BO_USE_LINEAR | BO_USE_SW_READ_OFTEN | BO_USE_SW_WRITE_OFTEN |
374 BO_USE_SW_WRITE_RARELY | BO_USE_SW_READ_RARELY))
375 gem_create_flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
377 gem_create_flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
379 memset(&gem_create, 0, sizeof(gem_create));
381 gem_create.in.bo_size = bo->total_size;
382 gem_create.in.alignment = addr_out.baseAlign;
383 /* Set the placement. */
384 gem_create.in.domains = AMDGPU_GEM_DOMAIN_VRAM;
385 gem_create.in.domain_flags = gem_create_flags;
386 /* Allocate the buffer with the preferred heap. */
387 ret = drmCommandWriteRead(drv_get_fd(bo->drv), DRM_AMDGPU_GEM_CREATE, &gem_create,
393 metadata.tiling_info = tiling_flags;
395 for (plane = 0; plane < bo->num_planes; plane++)
396 bo->handles[plane].u32 = gem_create.out.handle;
398 ret = amdgpu_set_metadata(drv_get_fd(bo->drv), bo->handles[0].u32, &metadata);
403 static void *amdgpu_bo_map(struct bo *bo, struct map_info *data, size_t plane, int prot)
406 union drm_amdgpu_gem_mmap gem_map;
408 memset(&gem_map, 0, sizeof(gem_map));
409 gem_map.in.handle = bo->handles[plane].u32;
411 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_AMDGPU_GEM_MMAP, &gem_map);
413 fprintf(stderr, "drv: DRM_IOCTL_AMDGPU_GEM_MMAP failed\n");
416 data->length = bo->total_size;
418 return mmap(0, bo->total_size, prot, MAP_SHARED, bo->drv->fd, gem_map.out.addr_ptr);
421 static uint32_t amdgpu_resolve_format(uint32_t format, uint64_t usage)
424 case DRM_FORMAT_FLEX_YCbCr_420_888:
425 return DRM_FORMAT_NV12;
431 struct backend backend_amdgpu = {
434 .close = amdgpu_close,
435 .bo_create = amdgpu_bo_create,
436 .bo_destroy = drv_gem_bo_destroy,
437 .bo_import = drv_prime_bo_import,
438 .bo_map = amdgpu_bo_map,
439 .resolve_format = amdgpu_resolve_format,