amdgpu.c

   1 /*
   2  * Copyright 2016 The Chromium OS Authors. All rights reserved.
   3  * Use of this source code is governed by a BSD-style license that can be
   4  * found in the LICENSE file.
   5  */
   6 #ifdef DRV_AMDGPU
   7 #include <amdgpu.h>
   8 #include <amdgpu_drm.h>
   9 #include <errno.h>
  10 #include <stdio.h>
  11 #include <stdlib.h>
  12 #include <string.h>
  13 #include <sys/mman.h>
  14 #include <xf86drm.h>
  15
  16 #include "addrinterface.h"
  17 #include "drv_priv.h"
  18 #include "helpers.h"
  19 #include "util.h"
  20
  21 #ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
  22 #define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
  23 #endif
  24
  25 // clang-format off
  26 #define mmCC_RB_BACKEND_DISABLE         0x263d
  27 #define mmGB_TILE_MODE0                 0x2644
  28 #define mmGB_MACROTILE_MODE0            0x2664
  29 #define mmGB_ADDR_CONFIG                0x263e
  30 #define mmMC_ARB_RAMCFG                 0x9d8
  31
  32 enum {
  33         FAMILY_UNKNOWN,
  34         FAMILY_SI,
  35         FAMILY_CI,
  36         FAMILY_KV,
  37         FAMILY_VI,
  38         FAMILY_CZ,
  39         FAMILY_PI,
  40         FAMILY_LAST,
  41 };
  42 // clang-format on
  43
  44 const static uint32_t render_target_formats[] = { DRM_FORMAT_ARGB8888, DRM_FORMAT_XBGR8888,
  45                                                   DRM_FORMAT_XRGB8888 };
  46
  47 const static uint32_t texture_source_formats[] = { DRM_FORMAT_NV21, DRM_FORMAT_NV12 };
  48
  49 static int amdgpu_set_metadata(int fd, uint32_t handle, struct amdgpu_bo_metadata *info)
  50 {
  51         struct drm_amdgpu_gem_metadata args = { 0 };
  52
  53         if (!info)
  54                 return -EINVAL;
  55
  56         args.handle = handle;
  57         args.op = AMDGPU_GEM_METADATA_OP_SET_METADATA;
  58         args.data.flags = info->flags;
  59         args.data.tiling_info = info->tiling_info;
  60
  61         if (info->size_metadata > sizeof(args.data.data))
  62                 return -EINVAL;
  63
  64         if (info->size_metadata) {
  65                 args.data.data_size_bytes = info->size_metadata;
  66                 memcpy(args.data.data, info->umd_metadata, info->size_metadata);
  67         }
  68
  69         return drmCommandWriteRead(fd, DRM_AMDGPU_GEM_METADATA, &args, sizeof(args));
  70 }
  71
  72 static int amdgpu_read_mm_regs(int fd, unsigned dword_offset, unsigned count, uint32_t instance,
  73                                uint32_t flags, uint32_t *values)
  74 {
  75         struct drm_amdgpu_info request;
  76
  77         memset(&request, 0, sizeof(request));
  78         request.return_pointer = (uintptr_t)values;
  79         request.return_size = count * sizeof(uint32_t);
  80         request.query = AMDGPU_INFO_READ_MMR_REG;
  81         request.read_mmr_reg.dword_offset = dword_offset;
  82         request.read_mmr_reg.count = count;
  83         request.read_mmr_reg.instance = instance;
  84         request.read_mmr_reg.flags = flags;
  85
  86         return drmCommandWrite(fd, DRM_AMDGPU_INFO, &request, sizeof(struct drm_amdgpu_info));
  87 }
  88
  89 static int amdgpu_query_gpu(int fd, struct amdgpu_gpu_info *gpu_info)
  90 {
  91         int ret;
  92         uint32_t instance;
  93
  94         if (!gpu_info)
  95                 return -EINVAL;
  96
  97         instance = AMDGPU_INFO_MMR_SH_INDEX_MASK << AMDGPU_INFO_MMR_SH_INDEX_SHIFT;
  98
  99         ret = amdgpu_read_mm_regs(fd, mmCC_RB_BACKEND_DISABLE, 1, instance, 0,
 100                                   &gpu_info->backend_disable[0]);
 101         if (ret)
 102                 return ret;
 103         /* extract bitfield CC_RB_BACKEND_DISABLE.BACKEND_DISABLE */
 104         gpu_info->backend_disable[0] = (gpu_info->backend_disable[0] >> 16) & 0xff;
 105
 106         ret = amdgpu_read_mm_regs(fd, mmGB_TILE_MODE0, 32, 0xffffffff, 0, gpu_info->gb_tile_mode);
 107         if (ret)
 108                 return ret;
 109
 110         ret = amdgpu_read_mm_regs(fd, mmGB_MACROTILE_MODE0, 16, 0xffffffff, 0,
 111                                   gpu_info->gb_macro_tile_mode);
 112         if (ret)
 113                 return ret;
 114
 115         ret = amdgpu_read_mm_regs(fd, mmGB_ADDR_CONFIG, 1, 0xffffffff, 0, &gpu_info->gb_addr_cfg);
 116         if (ret)
 117                 return ret;
 118
 119         ret = amdgpu_read_mm_regs(fd, mmMC_ARB_RAMCFG, 1, 0xffffffff, 0, &gpu_info->mc_arb_ramcfg);
 120         if (ret)
 121                 return ret;
 122
 123         return 0;
 124 }
 125
 126 static void *ADDR_API alloc_sys_mem(const ADDR_ALLOCSYSMEM_INPUT *in)
 127 {
 128         return malloc(in->sizeInBytes);
 129 }
 130
 131 static ADDR_E_RETURNCODE ADDR_API free_sys_mem(const ADDR_FREESYSMEM_INPUT *in)
 132 {
 133         free(in->pVirtAddr);
 134         return ADDR_OK;
 135 }
 136
 137 static int amdgpu_addrlib_compute(void *addrlib, uint32_t width, uint32_t height, uint32_t format,
 138                                   uint32_t usage, uint32_t *tiling_flags,
 139                                   ADDR_COMPUTE_SURFACE_INFO_OUTPUT *addr_out)
 140 {
 141         ADDR_COMPUTE_SURFACE_INFO_INPUT addr_surf_info_in = { 0 };
 142         ADDR_TILEINFO addr_tile_info = { 0 };
 143         ADDR_TILEINFO addr_tile_info_out = { 0 };
 144         uint32_t bits_per_pixel;
 145
 146         addr_surf_info_in.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_INPUT);
 147
 148         /* Set the requested tiling mode. */
 149         addr_surf_info_in.tileMode = ADDR_TM_2D_TILED_THIN1;
 150         if (usage & (BO_USE_CURSOR | BO_USE_LINEAR | BO_USE_SW_READ_OFTEN | BO_USE_SW_WRITE_OFTEN))
 151                 addr_surf_info_in.tileMode = ADDR_TM_LINEAR_ALIGNED;
 152         else if (width <= 16 || height <= 16)
 153                 addr_surf_info_in.tileMode = ADDR_TM_1D_TILED_THIN1;
 154
 155         bits_per_pixel = drv_stride_from_format(format, 1, 0) * 8;
 156         /* Bits per pixel should be calculated from format*/
 157         addr_surf_info_in.bpp = bits_per_pixel;
 158         addr_surf_info_in.numSamples = 1;
 159         addr_surf_info_in.width = width;
 160         addr_surf_info_in.height = height;
 161         addr_surf_info_in.numSlices = 1;
 162         addr_surf_info_in.pTileInfo = &addr_tile_info;
 163         addr_surf_info_in.tileIndex = -1;
 164
 165         /* This disables incorrect calculations (hacks) in addrlib. */
 166         addr_surf_info_in.flags.noStencil = 1;
 167
 168         /* Set the micro tile type. */
 169         if (usage & BO_USE_SCANOUT)
 170                 addr_surf_info_in.tileType = ADDR_DISPLAYABLE;
 171         else
 172                 addr_surf_info_in.tileType = ADDR_NON_DISPLAYABLE;
 173
 174         addr_out->size = sizeof(ADDR_COMPUTE_SURFACE_INFO_OUTPUT);
 175         addr_out->pTileInfo = &addr_tile_info_out;
 176
 177         if (AddrComputeSurfaceInfo(addrlib, &addr_surf_info_in, addr_out) != ADDR_OK)
 178                 return -EINVAL;
 179
 180         ADDR_CONVERT_TILEINFOTOHW_INPUT s_in = { 0 };
 181         ADDR_CONVERT_TILEINFOTOHW_OUTPUT s_out = { 0 };
 182         ADDR_TILEINFO s_tile_hw_info_out = { 0 };
 183
 184         s_in.size = sizeof(ADDR_CONVERT_TILEINFOTOHW_INPUT);
 185         /* Convert from real value to HW value */
 186         s_in.reverse = 0;
 187         s_in.pTileInfo = &addr_tile_info_out;
 188         s_in.tileIndex = -1;
 189
 190         s_out.size = sizeof(ADDR_CONVERT_TILEINFOTOHW_OUTPUT);
 191         s_out.pTileInfo = &s_tile_hw_info_out;
 192
 193         if (AddrConvertTileInfoToHW(addrlib, &s_in, &s_out) != ADDR_OK)
 194                 return -EINVAL;
 195
 196         if (addr_out->tileMode >= ADDR_TM_2D_TILED_THIN1)
 197                 /* 2D_TILED_THIN1 */
 198                 *tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 4);
 199         else if (addr_out->tileMode >= ADDR_TM_1D_TILED_THIN1)
 200                 /* 1D_TILED_THIN1 */
 201                 *tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 2);
 202         else
 203                 /* LINEAR_ALIGNED */
 204                 *tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 1);
 205
 206         *tiling_flags |= AMDGPU_TILING_SET(BANK_WIDTH, drv_log_base2(addr_tile_info_out.bankWidth));
 207         *tiling_flags |=
 208             AMDGPU_TILING_SET(BANK_HEIGHT, drv_log_base2(addr_tile_info_out.bankHeight));
 209         *tiling_flags |= AMDGPU_TILING_SET(TILE_SPLIT, s_tile_hw_info_out.tileSplitBytes);
 210         *tiling_flags |= AMDGPU_TILING_SET(MACRO_TILE_ASPECT,
 211                                            drv_log_base2(addr_tile_info_out.macroAspectRatio));
 212         *tiling_flags |= AMDGPU_TILING_SET(PIPE_CONFIG, s_tile_hw_info_out.pipeConfig);
 213         *tiling_flags |= AMDGPU_TILING_SET(NUM_BANKS, s_tile_hw_info_out.banks);
 214
 215         return 0;
 216 }
 217
 218 static void *amdgpu_addrlib_init(int fd)
 219 {
 220         int ret;
 221         ADDR_CREATE_INPUT addr_create_input = { 0 };
 222         ADDR_CREATE_OUTPUT addr_create_output = { 0 };
 223         ADDR_REGISTER_VALUE reg_value = { 0 };
 224         ADDR_CREATE_FLAGS create_flags = { { 0 } };
 225         ADDR_E_RETURNCODE addr_ret;
 226
 227         addr_create_input.size = sizeof(ADDR_CREATE_INPUT);
 228         addr_create_output.size = sizeof(ADDR_CREATE_OUTPUT);
 229
 230         struct amdgpu_gpu_info gpu_info = { 0 };
 231
 232         ret = amdgpu_query_gpu(fd, &gpu_info);
 233
 234         if (ret) {
 235                 fprintf(stderr, "[%s]failed with error =%d\n", __func__, ret);
 236                 return NULL;
 237         }
 238
 239         reg_value.noOfBanks = gpu_info.mc_arb_ramcfg & 0x3;
 240         reg_value.gbAddrConfig = gpu_info.gb_addr_cfg;
 241         reg_value.noOfRanks = (gpu_info.mc_arb_ramcfg & 0x4) >> 2;
 242
 243         reg_value.backendDisables = gpu_info.backend_disable[0];
 244         reg_value.pTileConfig = gpu_info.gb_tile_mode;
 245         reg_value.noOfEntries = sizeof(gpu_info.gb_tile_mode) / sizeof(gpu_info.gb_tile_mode[0]);
 246         reg_value.pMacroTileConfig = gpu_info.gb_macro_tile_mode;
 247         reg_value.noOfMacroEntries =
 248             sizeof(gpu_info.gb_macro_tile_mode) / sizeof(gpu_info.gb_macro_tile_mode[0]);
 249         create_flags.value = 0;
 250         create_flags.useTileIndex = 1;
 251
 252         addr_create_input.chipEngine = CIASICIDGFXENGINE_SOUTHERNISLAND;
 253
 254         addr_create_input.chipFamily = FAMILY_CZ;
 255         addr_create_input.createFlags = create_flags;
 256         addr_create_input.callbacks.allocSysMem = alloc_sys_mem;
 257         addr_create_input.callbacks.freeSysMem = free_sys_mem;
 258         addr_create_input.callbacks.debugPrint = 0;
 259         addr_create_input.regValue = reg_value;
 260
 261         addr_ret = AddrCreate(&addr_create_input, &addr_create_output);
 262
 263         if (addr_ret != ADDR_OK) {
 264                 fprintf(stderr, "[%s]failed error =%d\n", __func__, addr_ret);
 265                 return NULL;
 266         }
 267
 268         return addr_create_output.hLib;
 269 }
 270
 271 static int amdgpu_init(struct driver *drv)
 272 {
 273         int ret;
 274         void *addrlib;
 275         struct format_metadata metadata;
 276         uint32_t flags = BO_USE_RENDER_MASK;
 277
 278         addrlib = amdgpu_addrlib_init(drv_get_fd(drv));
 279         if (!addrlib)
 280                 return -1;
 281
 282         drv->priv = addrlib;
 283
 284         ret = drv_add_combinations(drv, texture_source_formats, ARRAY_SIZE(texture_source_formats),
 285                                    &LINEAR_METADATA, BO_USE_TEXTURE_MASK);
 286         if (ret)
 287                 return ret;
 288
 289         drv_modify_combination(drv, DRM_FORMAT_NV21, &LINEAR_METADATA, BO_USE_SCANOUT);
 290         drv_modify_combination(drv, DRM_FORMAT_NV12, &LINEAR_METADATA, BO_USE_SCANOUT);
 291
 292         metadata.tiling = ADDR_DISPLAYABLE << 16 | ADDR_TM_LINEAR_ALIGNED;
 293         metadata.priority = 2;
 294         metadata.modifier = DRM_FORMAT_MOD_NONE;
 295
 296         ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
 297                                    &metadata, flags);
 298         if (ret)
 299                 return ret;
 300
 301         drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
 302         drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
 303         drv_modify_combination(drv, DRM_FORMAT_XBGR8888, &metadata, BO_USE_SCANOUT);
 304
 305         metadata.tiling = ADDR_NON_DISPLAYABLE << 16 | ADDR_TM_LINEAR_ALIGNED;
 306         metadata.priority = 3;
 307         metadata.modifier = DRM_FORMAT_MOD_NONE;
 308
 309         ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
 310                                    &metadata, flags);
 311         if (ret)
 312                 return ret;
 313
 314         flags &= ~BO_USE_SW_WRITE_OFTEN;
 315         flags &= ~BO_USE_SW_READ_OFTEN;
 316         flags &= ~BO_USE_LINEAR;
 317
 318         metadata.tiling = ADDR_DISPLAYABLE << 16 | ADDR_TM_2D_TILED_THIN1;
 319         metadata.priority = 4;
 320
 321         ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
 322                                    &metadata, flags);
 323         if (ret)
 324                 return ret;
 325
 326         drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_SCANOUT);
 327         drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_SCANOUT);
 328         drv_modify_combination(drv, DRM_FORMAT_XBGR8888, &metadata, BO_USE_SCANOUT);
 329
 330         metadata.tiling = ADDR_NON_DISPLAYABLE << 16 | ADDR_TM_2D_TILED_THIN1;
 331         metadata.priority = 5;
 332
 333         ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
 334                                    &metadata, flags);
 335         if (ret)
 336                 return ret;
 337
 338         return ret;
 339 }
 340
 341 static void amdgpu_close(struct driver *drv)
 342 {
 343         AddrDestroy(drv->priv);
 344         drv->priv = NULL;
 345 }
 346
 347 static int amdgpu_bo_create(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
 348                             uint32_t usage)
 349 {
 350         void *addrlib = bo->drv->priv;
 351         union drm_amdgpu_gem_create gem_create;
 352         struct amdgpu_bo_metadata metadata = { 0 };
 353         ADDR_COMPUTE_SURFACE_INFO_OUTPUT addr_out = { 0 };
 354         uint32_t tiling_flags = 0;
 355         uint32_t gem_create_flags = 0;
 356         size_t plane;
 357         int ret;
 358
 359         if (format == DRM_FORMAT_NV12 || format == DRM_FORMAT_NV21) {
 360                 drv_bo_from_format(bo, ALIGN(width, 64), height, format);
 361         } else {
 362                 if (amdgpu_addrlib_compute(addrlib, width, height, format, usage, &tiling_flags,
 363                                            &addr_out) < 0)
 364                         return -EINVAL;
 365
 366                 bo->tiling = tiling_flags;
 367                 /* RGB has 1 plane only */
 368                 bo->offsets[0] = 0;
 369                 bo->total_size = bo->sizes[0] = addr_out.surfSize;
 370                 bo->strides[0] = addr_out.pixelPitch * DIV_ROUND_UP(addr_out.pixelBits, 8);
 371         }
 372
 373         if (usage & (BO_USE_CURSOR | BO_USE_LINEAR | BO_USE_SW_READ_OFTEN | BO_USE_SW_WRITE_OFTEN |
 374                      BO_USE_SW_WRITE_RARELY | BO_USE_SW_READ_RARELY))
 375                 gem_create_flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 376         else
 377                 gem_create_flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
 378
 379         memset(&gem_create, 0, sizeof(gem_create));
 380
 381         gem_create.in.bo_size = bo->total_size;
 382         gem_create.in.alignment = addr_out.baseAlign;
 383         /* Set the placement. */
 384         gem_create.in.domains = AMDGPU_GEM_DOMAIN_VRAM;
 385         gem_create.in.domain_flags = gem_create_flags;
 386         /* Allocate the buffer with the preferred heap. */
 387         ret = drmCommandWriteRead(drv_get_fd(bo->drv), DRM_AMDGPU_GEM_CREATE, &gem_create,
 388                                   sizeof(gem_create));
 389
 390         if (ret < 0)
 391                 return ret;
 392
 393         metadata.tiling_info = tiling_flags;
 394
 395         for (plane = 0; plane < bo->num_planes; plane++)
 396                 bo->handles[plane].u32 = gem_create.out.handle;
 397
 398         ret = amdgpu_set_metadata(drv_get_fd(bo->drv), bo->handles[0].u32, &metadata);
 399
 400         return ret;
 401 }
 402
 403 static void *amdgpu_bo_map(struct bo *bo, struct map_info *data, size_t plane, int prot)
 404 {
 405         int ret;
 406         union drm_amdgpu_gem_mmap gem_map;
 407
 408         memset(&gem_map, 0, sizeof(gem_map));
 409         gem_map.in.handle = bo->handles[plane].u32;
 410
 411         ret = drmIoctl(bo->drv->fd, DRM_IOCTL_AMDGPU_GEM_MMAP, &gem_map);
 412         if (ret) {
 413                 fprintf(stderr, "drv: DRM_IOCTL_AMDGPU_GEM_MMAP failed\n");
 414                 return MAP_FAILED;
 415         }
 416         data->length = bo->total_size;
 417
 418         return mmap(0, bo->total_size, prot, MAP_SHARED, bo->drv->fd, gem_map.out.addr_ptr);
 419 }
 420
 421 static uint32_t amdgpu_resolve_format(uint32_t format, uint64_t usage)
 422 {
 423         switch (format) {
 424         case DRM_FORMAT_FLEX_YCbCr_420_888:
 425                 return DRM_FORMAT_NV12;
 426         default:
 427                 return format;
 428         }
 429 }
 430
 431 struct backend backend_amdgpu = {
 432         .name = "amdgpu",
 433         .init = amdgpu_init,
 434         .close = amdgpu_close,
 435         .bo_create = amdgpu_bo_create,
 436         .bo_destroy = drv_gem_bo_destroy,
 437         .bo_import = drv_prime_bo_import,
 438         .bo_map = amdgpu_bo_map,
 439         .resolve_format = amdgpu_resolve_format,
 440 };
 441
 442 #endif