amdgpu.c

   1 /*
   2  * Copyright 2016 The Chromium OS Authors. All rights reserved.
   3  * Use of this source code is governed by a BSD-style license that can be
   4  * found in the LICENSE file.
   5  */
   6 #ifdef DRV_AMDGPU
   7 #include <amdgpu.h>
   8 #include <amdgpu_drm.h>
   9 #include <errno.h>
  10 #include <stdio.h>
  11 #include <stdlib.h>
  12 #include <string.h>
  13 #include <sys/mman.h>
  14 #include <xf86drm.h>
  15
  16 #include "addrinterface.h"
  17 #include "drv_priv.h"
  18 #include "helpers.h"
  19 #include "util.h"
  20
  21 #ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
  22 #define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
  23 #endif
  24
  25 // clang-format off
  26 #define mmCC_RB_BACKEND_DISABLE         0x263d
  27 #define mmGB_TILE_MODE0                 0x2644
  28 #define mmGB_MACROTILE_MODE0            0x2664
  29 #define mmGB_ADDR_CONFIG                0x263e
  30 #define mmMC_ARB_RAMCFG                 0x9d8
  31
  32 enum {
  33         FAMILY_UNKNOWN,
  34         FAMILY_SI,
  35         FAMILY_CI,
  36         FAMILY_KV,
  37         FAMILY_VI,
  38         FAMILY_CZ,
  39         FAMILY_PI,
  40         FAMILY_LAST,
  41 };
  42 // clang-format on
  43
  44 const static uint32_t supported_formats[] = { DRM_FORMAT_ARGB8888, DRM_FORMAT_XBGR8888,
  45                                               DRM_FORMAT_XRGB8888 };
  46
  47 static int amdgpu_set_metadata(int fd, uint32_t handle, struct amdgpu_bo_metadata *info)
  48 {
  49         struct drm_amdgpu_gem_metadata args = { 0 };
  50
  51         if (!info)
  52                 return -EINVAL;
  53
  54         args.handle = handle;
  55         args.op = AMDGPU_GEM_METADATA_OP_SET_METADATA;
  56         args.data.flags = info->flags;
  57         args.data.tiling_info = info->tiling_info;
  58
  59         if (info->size_metadata > sizeof(args.data.data))
  60                 return -EINVAL;
  61
  62         if (info->size_metadata) {
  63                 args.data.data_size_bytes = info->size_metadata;
  64                 memcpy(args.data.data, info->umd_metadata, info->size_metadata);
  65         }
  66
  67         return drmCommandWriteRead(fd, DRM_AMDGPU_GEM_METADATA, &args, sizeof(args));
  68 }
  69
  70 static int amdgpu_read_mm_regs(int fd, unsigned dword_offset, unsigned count, uint32_t instance,
  71                                uint32_t flags, uint32_t *values)
  72 {
  73         struct drm_amdgpu_info request;
  74
  75         memset(&request, 0, sizeof(request));
  76         request.return_pointer = (uintptr_t)values;
  77         request.return_size = count * sizeof(uint32_t);
  78         request.query = AMDGPU_INFO_READ_MMR_REG;
  79         request.read_mmr_reg.dword_offset = dword_offset;
  80         request.read_mmr_reg.count = count;
  81         request.read_mmr_reg.instance = instance;
  82         request.read_mmr_reg.flags = flags;
  83
  84         return drmCommandWrite(fd, DRM_AMDGPU_INFO, &request, sizeof(struct drm_amdgpu_info));
  85 }
  86
  87 static int amdgpu_query_gpu(int fd, struct amdgpu_gpu_info *gpu_info)
  88 {
  89         int ret;
  90         uint32_t instance;
  91
  92         if (!gpu_info)
  93                 return -EINVAL;
  94
  95         instance = AMDGPU_INFO_MMR_SH_INDEX_MASK << AMDGPU_INFO_MMR_SH_INDEX_SHIFT;
  96
  97         ret = amdgpu_read_mm_regs(fd, mmCC_RB_BACKEND_DISABLE, 1, instance, 0,
  98                                   &gpu_info->backend_disable[0]);
  99         if (ret)
 100                 return ret;
 101         /* extract bitfield CC_RB_BACKEND_DISABLE.BACKEND_DISABLE */
 102         gpu_info->backend_disable[0] = (gpu_info->backend_disable[0] >> 16) & 0xff;
 103
 104         ret = amdgpu_read_mm_regs(fd, mmGB_TILE_MODE0, 32, 0xffffffff, 0, gpu_info->gb_tile_mode);
 105         if (ret)
 106                 return ret;
 107
 108         ret = amdgpu_read_mm_regs(fd, mmGB_MACROTILE_MODE0, 16, 0xffffffff, 0,
 109                                   gpu_info->gb_macro_tile_mode);
 110         if (ret)
 111                 return ret;
 112
 113         ret = amdgpu_read_mm_regs(fd, mmGB_ADDR_CONFIG, 1, 0xffffffff, 0, &gpu_info->gb_addr_cfg);
 114         if (ret)
 115                 return ret;
 116
 117         ret = amdgpu_read_mm_regs(fd, mmMC_ARB_RAMCFG, 1, 0xffffffff, 0, &gpu_info->mc_arb_ramcfg);
 118         if (ret)
 119                 return ret;
 120
 121         return 0;
 122 }
 123
 124 static void *ADDR_API alloc_sys_mem(const ADDR_ALLOCSYSMEM_INPUT *in)
 125 {
 126         return malloc(in->sizeInBytes);
 127 }
 128
 129 static ADDR_E_RETURNCODE ADDR_API free_sys_mem(const ADDR_FREESYSMEM_INPUT *in)
 130 {
 131         free(in->pVirtAddr);
 132         return ADDR_OK;
 133 }
 134
 135 static int amdgpu_addrlib_compute(void *addrlib, uint32_t width, uint32_t height, uint32_t format,
 136                                   uint32_t usage, uint32_t *tiling_flags,
 137                                   ADDR_COMPUTE_SURFACE_INFO_OUTPUT *addr_out)
 138 {
 139         ADDR_COMPUTE_SURFACE_INFO_INPUT addr_surf_info_in = { 0 };
 140         ADDR_TILEINFO addr_tile_info = { 0 };
 141         ADDR_TILEINFO addr_tile_info_out = { 0 };
 142         uint32_t bits_per_pixel;
 143
 144         addr_surf_info_in.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_INPUT);
 145
 146         /* Set the requested tiling mode. */
 147         addr_surf_info_in.tileMode = ADDR_TM_2D_TILED_THIN1;
 148         if (usage & (BO_USE_CURSOR | BO_USE_LINEAR | BO_USE_SW_READ_OFTEN | BO_USE_SW_WRITE_OFTEN))
 149                 addr_surf_info_in.tileMode = ADDR_TM_LINEAR_ALIGNED;
 150         else if (width <= 16 || height <= 16)
 151                 addr_surf_info_in.tileMode = ADDR_TM_1D_TILED_THIN1;
 152
 153         bits_per_pixel = drv_stride_from_format(format, 1, 0) * 8;
 154         /* Bits per pixel should be calculated from format*/
 155         addr_surf_info_in.bpp = bits_per_pixel;
 156         addr_surf_info_in.numSamples = 1;
 157         addr_surf_info_in.width = width;
 158         addr_surf_info_in.height = height;
 159         addr_surf_info_in.numSlices = 1;
 160         addr_surf_info_in.pTileInfo = &addr_tile_info;
 161         addr_surf_info_in.tileIndex = -1;
 162
 163         /* This disables incorrect calculations (hacks) in addrlib. */
 164         addr_surf_info_in.flags.noStencil = 1;
 165
 166         /* Set the micro tile type. */
 167         if (usage & BO_USE_SCANOUT)
 168                 addr_surf_info_in.tileType = ADDR_DISPLAYABLE;
 169         else
 170                 addr_surf_info_in.tileType = ADDR_NON_DISPLAYABLE;
 171
 172         addr_out->size = sizeof(ADDR_COMPUTE_SURFACE_INFO_OUTPUT);
 173         addr_out->pTileInfo = &addr_tile_info_out;
 174
 175         if (AddrComputeSurfaceInfo(addrlib, &addr_surf_info_in, addr_out) != ADDR_OK)
 176                 return -EINVAL;
 177
 178         ADDR_CONVERT_TILEINFOTOHW_INPUT s_in = { 0 };
 179         ADDR_CONVERT_TILEINFOTOHW_OUTPUT s_out = { 0 };
 180         ADDR_TILEINFO s_tile_hw_info_out = { 0 };
 181
 182         s_in.size = sizeof(ADDR_CONVERT_TILEINFOTOHW_INPUT);
 183         /* Convert from real value to HW value */
 184         s_in.reverse = 0;
 185         s_in.pTileInfo = &addr_tile_info_out;
 186         s_in.tileIndex = -1;
 187
 188         s_out.size = sizeof(ADDR_CONVERT_TILEINFOTOHW_OUTPUT);
 189         s_out.pTileInfo = &s_tile_hw_info_out;
 190
 191         if (AddrConvertTileInfoToHW(addrlib, &s_in, &s_out) != ADDR_OK)
 192                 return -EINVAL;
 193
 194         if (addr_out->tileMode >= ADDR_TM_2D_TILED_THIN1)
 195                 /* 2D_TILED_THIN1 */
 196                 *tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 4);
 197         else if (addr_out->tileMode >= ADDR_TM_1D_TILED_THIN1)
 198                 /* 1D_TILED_THIN1 */
 199                 *tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 2);
 200         else
 201                 /* LINEAR_ALIGNED */
 202                 *tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 1);
 203
 204         *tiling_flags |= AMDGPU_TILING_SET(BANK_WIDTH, drv_log_base2(addr_tile_info_out.bankWidth));
 205         *tiling_flags |=
 206             AMDGPU_TILING_SET(BANK_HEIGHT, drv_log_base2(addr_tile_info_out.bankHeight));
 207         *tiling_flags |= AMDGPU_TILING_SET(TILE_SPLIT, s_tile_hw_info_out.tileSplitBytes);
 208         *tiling_flags |= AMDGPU_TILING_SET(MACRO_TILE_ASPECT,
 209                                            drv_log_base2(addr_tile_info_out.macroAspectRatio));
 210         *tiling_flags |= AMDGPU_TILING_SET(PIPE_CONFIG, s_tile_hw_info_out.pipeConfig);
 211         *tiling_flags |= AMDGPU_TILING_SET(NUM_BANKS, s_tile_hw_info_out.banks);
 212
 213         return 0;
 214 }
 215
 216 static void *amdgpu_addrlib_init(int fd)
 217 {
 218         int ret;
 219         ADDR_CREATE_INPUT addr_create_input = { 0 };
 220         ADDR_CREATE_OUTPUT addr_create_output = { 0 };
 221         ADDR_REGISTER_VALUE reg_value = { 0 };
 222         ADDR_CREATE_FLAGS create_flags = { { 0 } };
 223         ADDR_E_RETURNCODE addr_ret;
 224
 225         addr_create_input.size = sizeof(ADDR_CREATE_INPUT);
 226         addr_create_output.size = sizeof(ADDR_CREATE_OUTPUT);
 227
 228         struct amdgpu_gpu_info gpu_info = { 0 };
 229
 230         ret = amdgpu_query_gpu(fd, &gpu_info);
 231
 232         if (ret) {
 233                 fprintf(stderr, "[%s]failed with error =%d\n", __func__, ret);
 234                 return NULL;
 235         }
 236
 237         reg_value.noOfBanks = gpu_info.mc_arb_ramcfg & 0x3;
 238         reg_value.gbAddrConfig = gpu_info.gb_addr_cfg;
 239         reg_value.noOfRanks = (gpu_info.mc_arb_ramcfg & 0x4) >> 2;
 240
 241         reg_value.backendDisables = gpu_info.backend_disable[0];
 242         reg_value.pTileConfig = gpu_info.gb_tile_mode;
 243         reg_value.noOfEntries = sizeof(gpu_info.gb_tile_mode) / sizeof(gpu_info.gb_tile_mode[0]);
 244         reg_value.pMacroTileConfig = gpu_info.gb_macro_tile_mode;
 245         reg_value.noOfMacroEntries =
 246             sizeof(gpu_info.gb_macro_tile_mode) / sizeof(gpu_info.gb_macro_tile_mode[0]);
 247         create_flags.value = 0;
 248         create_flags.useTileIndex = 1;
 249
 250         addr_create_input.chipEngine = CIASICIDGFXENGINE_SOUTHERNISLAND;
 251
 252         addr_create_input.chipFamily = FAMILY_CZ;
 253         addr_create_input.createFlags = create_flags;
 254         addr_create_input.callbacks.allocSysMem = alloc_sys_mem;
 255         addr_create_input.callbacks.freeSysMem = free_sys_mem;
 256         addr_create_input.callbacks.debugPrint = 0;
 257         addr_create_input.regValue = reg_value;
 258
 259         addr_ret = AddrCreate(&addr_create_input, &addr_create_output);
 260
 261         if (addr_ret != ADDR_OK) {
 262                 fprintf(stderr, "[%s]failed error =%d\n", __func__, addr_ret);
 263                 return NULL;
 264         }
 265
 266         return addr_create_output.hLib;
 267 }
 268
 269 static int amdgpu_init(struct driver *drv)
 270 {
 271         int ret;
 272         void *addrlib;
 273         struct format_metadata metadata;
 274         uint32_t flags = BO_COMMON_USE_MASK;
 275
 276         addrlib = amdgpu_addrlib_init(drv_get_fd(drv));
 277         if (!addrlib)
 278                 return -1;
 279
 280         drv->priv = addrlib;
 281
 282         metadata.tiling = ADDR_DISPLAYABLE << 16 | ADDR_TM_LINEAR_ALIGNED;
 283         metadata.priority = 1;
 284         metadata.modifier = DRM_FORMAT_MOD_NONE;
 285
 286         ret = drv_add_combinations(drv, supported_formats, ARRAY_SIZE(supported_formats), &metadata,
 287                                    flags);
 288         if (ret)
 289                 return ret;
 290
 291         drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
 292         drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
 293         drv_modify_combination(drv, DRM_FORMAT_XBGR8888, &metadata, BO_USE_SCANOUT);
 294
 295         metadata.tiling = ADDR_NON_DISPLAYABLE << 16 | ADDR_TM_LINEAR_ALIGNED;
 296         metadata.priority = 2;
 297         metadata.modifier = DRM_FORMAT_MOD_NONE;
 298
 299         ret = drv_add_combinations(drv, supported_formats, ARRAY_SIZE(supported_formats), &metadata,
 300                                    flags);
 301         if (ret)
 302                 return ret;
 303
 304         flags &= ~BO_USE_SW_WRITE_OFTEN;
 305         flags &= ~BO_USE_SW_READ_OFTEN;
 306         flags &= ~BO_USE_LINEAR;
 307
 308         metadata.tiling = ADDR_DISPLAYABLE << 16 | ADDR_TM_2D_TILED_THIN1;
 309         metadata.priority = 3;
 310
 311         ret = drv_add_combinations(drv, supported_formats, ARRAY_SIZE(supported_formats), &metadata,
 312                                    flags);
 313         if (ret)
 314                 return ret;
 315
 316         drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_SCANOUT);
 317         drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_SCANOUT);
 318         drv_modify_combination(drv, DRM_FORMAT_XBGR8888, &metadata, BO_USE_SCANOUT);
 319
 320         metadata.tiling = ADDR_NON_DISPLAYABLE << 16 | ADDR_TM_2D_TILED_THIN1;
 321         metadata.priority = 4;
 322
 323         ret = drv_add_combinations(drv, supported_formats, ARRAY_SIZE(supported_formats), &metadata,
 324                                    flags);
 325         if (ret)
 326                 return ret;
 327
 328         return ret;
 329 }
 330
 331 static void amdgpu_close(struct driver *drv)
 332 {
 333         AddrDestroy(drv->priv);
 334         drv->priv = NULL;
 335 }
 336
 337 static int amdgpu_bo_create(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
 338                             uint32_t usage)
 339 {
 340         void *addrlib = bo->drv->priv;
 341         union drm_amdgpu_gem_create gem_create;
 342         struct amdgpu_bo_metadata metadata = { 0 };
 343         ADDR_COMPUTE_SURFACE_INFO_OUTPUT addr_out = { 0 };
 344         uint32_t tiling_flags = 0;
 345         uint32_t gem_create_flags = 0;
 346         int ret;
 347
 348         if (amdgpu_addrlib_compute(addrlib, width, height, format, usage, &tiling_flags,
 349                                    &addr_out) < 0)
 350                 return -EINVAL;
 351
 352         bo->tiling = tiling_flags;
 353         bo->offsets[0] = 0;
 354         bo->sizes[0] = addr_out.surfSize;
 355         bo->strides[0] = addr_out.pixelPitch * DIV_ROUND_UP(addr_out.pixelBits, 8);
 356         if (usage & (BO_USE_CURSOR | BO_USE_LINEAR | BO_USE_SW_READ_OFTEN | BO_USE_SW_WRITE_OFTEN |
 357                      BO_USE_SW_WRITE_RARELY | BO_USE_SW_READ_RARELY))
 358                 gem_create_flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 359         else
 360                 gem_create_flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
 361
 362         memset(&gem_create, 0, sizeof(gem_create));
 363         gem_create.in.bo_size = bo->sizes[0];
 364         gem_create.in.alignment = addr_out.baseAlign;
 365         /* Set the placement. */
 366         gem_create.in.domains = AMDGPU_GEM_DOMAIN_VRAM;
 367         gem_create.in.domain_flags = gem_create_flags;
 368
 369         /* Allocate the buffer with the preferred heap. */
 370         ret = drmCommandWriteRead(drv_get_fd(bo->drv), DRM_AMDGPU_GEM_CREATE, &gem_create,
 371                                   sizeof(gem_create));
 372
 373         if (ret < 0)
 374                 return ret;
 375
 376         bo->handles[0].u32 = gem_create.out.handle;
 377
 378         metadata.tiling_info = tiling_flags;
 379
 380         ret = amdgpu_set_metadata(drv_get_fd(bo->drv), bo->handles[0].u32, &metadata);
 381
 382         return ret;
 383 }
 384
 385 static void *amdgpu_bo_map(struct bo *bo, struct map_info *data, size_t plane)
 386 {
 387         int ret;
 388         union drm_amdgpu_gem_mmap gem_map;
 389
 390         memset(&gem_map, 0, sizeof(gem_map));
 391         gem_map.in.handle = bo->handles[0].u32;
 392
 393         ret = drmIoctl(bo->drv->fd, DRM_IOCTL_AMDGPU_GEM_MMAP, &gem_map);
 394         if (ret) {
 395                 fprintf(stderr, "drv: DRM_IOCTL_AMDGPU_GEM_MMAP failed\n");
 396                 return MAP_FAILED;
 397         }
 398         data->length = bo->sizes[0];
 399
 400         return mmap(0, bo->sizes[0], PROT_READ | PROT_WRITE, MAP_SHARED, bo->drv->fd,
 401                     gem_map.out.addr_ptr);
 402 }
 403
 404 struct backend backend_amdgpu = {
 405         .name = "amdgpu",
 406         .init = amdgpu_init,
 407         .close = amdgpu_close,
 408         .bo_create = amdgpu_bo_create,
 409         .bo_destroy = drv_gem_bo_destroy,
 410         .bo_import = drv_prime_bo_import,
 411         .bo_map = amdgpu_bo_map,
 412 };
 413
 414 #endif