amdgpu.c

   1 /*
   2  * Copyright 2016 The Chromium OS Authors. All rights reserved.
   3  * Use of this source code is governed by a BSD-style license that can be
   4  * found in the LICENSE file.
   5  */
   6 #ifdef DRV_AMDGPU
   7 #include <amdgpu.h>
   8 #include <amdgpu_drm.h>
   9 #include <errno.h>
  10 #include <stdio.h>
  11 #include <stdlib.h>
  12 #include <string.h>
  13 #include <sys/mman.h>
  14 #include <xf86drm.h>
  15
  16 #include "dri.h"
  17 #include "drv_priv.h"
  18 #include "helpers.h"
  19 #include "util.h"
  20
  21 #ifdef __ANDROID__
  22 #define DRI_PATH "/vendor/lib/dri/radeonsi_dri.so"
  23 #else
  24 #define DRI_PATH "/usr/lib64/dri/radeonsi_dri.so"
  25 #endif
  26
  27 #define TILE_TYPE_LINEAR 0
  28 /* DRI backend decides tiling in this case. */
  29 #define TILE_TYPE_DRI 1
  30
  31 struct amdgpu_priv {
  32         struct dri_driver dri;
  33         int drm_version;
  34 };
  35
  36 const static uint32_t render_target_formats[] = { DRM_FORMAT_ABGR8888, DRM_FORMAT_ARGB8888,
  37                                                   DRM_FORMAT_RGB565, DRM_FORMAT_XBGR8888,
  38                                                   DRM_FORMAT_XRGB8888 };
  39
  40 const static uint32_t texture_source_formats[] = { DRM_FORMAT_GR88, DRM_FORMAT_R8, DRM_FORMAT_NV21,
  41                                                    DRM_FORMAT_NV12, DRM_FORMAT_YVU420_ANDROID };
  42
  43 static int amdgpu_init(struct driver *drv)
  44 {
  45         struct amdgpu_priv *priv;
  46         drmVersionPtr drm_version;
  47         struct format_metadata metadata;
  48         uint64_t use_flags = BO_USE_RENDER_MASK;
  49
  50         priv = calloc(1, sizeof(struct amdgpu_priv));
  51         if (!priv)
  52                 return -ENOMEM;
  53
  54         drm_version = drmGetVersion(drv_get_fd(drv));
  55         if (!drm_version) {
  56                 free(priv);
  57                 return -ENODEV;
  58         }
  59
  60         priv->drm_version = drm_version->version_minor;
  61         drmFreeVersion(drm_version);
  62
  63         drv->priv = priv;
  64
  65         if (dri_init(drv, DRI_PATH, "radeonsi")) {
  66                 free(priv);
  67                 drv->priv = NULL;
  68                 return -ENODEV;
  69         }
  70
  71         metadata.tiling = TILE_TYPE_LINEAR;
  72         metadata.priority = 1;
  73         metadata.modifier = DRM_FORMAT_MOD_LINEAR;
  74
  75         drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
  76                              &metadata, use_flags);
  77
  78         drv_add_combinations(drv, texture_source_formats, ARRAY_SIZE(texture_source_formats),
  79                              &metadata, BO_USE_TEXTURE_MASK);
  80
  81         /* Android CTS tests require this. */
  82         drv_add_combination(drv, DRM_FORMAT_BGR888, &metadata, BO_USE_SW_MASK);
  83
  84         /* Linear formats supported by display. */
  85         drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
  86         drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
  87         drv_modify_combination(drv, DRM_FORMAT_ABGR8888, &metadata, BO_USE_SCANOUT);
  88         drv_modify_combination(drv, DRM_FORMAT_XBGR8888, &metadata, BO_USE_SCANOUT);
  89
  90         /* YUV formats for camera and display. */
  91         drv_modify_combination(drv, DRM_FORMAT_NV12, &metadata,
  92                                BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE | BO_USE_SCANOUT |
  93                                    BO_USE_HW_VIDEO_DECODER);
  94
  95         drv_modify_combination(drv, DRM_FORMAT_NV21, &metadata, BO_USE_SCANOUT);
  96
  97         /*
  98          * R8 format is used for Android's HAL_PIXEL_FORMAT_BLOB and is used for JPEG snapshots
  99          * from camera.
 100          */
 101         drv_modify_combination(drv, DRM_FORMAT_R8, &metadata,
 102                                BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE);
 103
 104         /*
 105          * The following formats will be allocated by the DRI backend and may be potentially tiled.
 106          * Since format modifier support hasn't been implemented fully yet, it's not
 107          * possible to enumerate the different types of buffers (like i915 can).
 108          */
 109         use_flags &= ~BO_USE_RENDERSCRIPT;
 110         use_flags &= ~BO_USE_SW_WRITE_OFTEN;
 111         use_flags &= ~BO_USE_SW_READ_OFTEN;
 112         use_flags &= ~BO_USE_LINEAR;
 113
 114         metadata.tiling = TILE_TYPE_DRI;
 115         metadata.priority = 2;
 116
 117         drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
 118                              &metadata, use_flags);
 119
 120         /* Potentially tiled formats supported by display. */
 121         drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
 122         drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
 123         drv_modify_combination(drv, DRM_FORMAT_ABGR8888, &metadata, BO_USE_SCANOUT);
 124         drv_modify_combination(drv, DRM_FORMAT_XBGR8888, &metadata, BO_USE_SCANOUT);
 125         return 0;
 126 }
 127
 128 static void amdgpu_close(struct driver *drv)
 129 {
 130         dri_close(drv);
 131         free(drv->priv);
 132         drv->priv = NULL;
 133 }
 134
 135 static int amdgpu_create_bo(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
 136                             uint64_t use_flags)
 137 {
 138         int ret;
 139         uint32_t plane, stride;
 140         struct combination *combo;
 141         union drm_amdgpu_gem_create gem_create;
 142
 143         combo = drv_get_combination(bo->drv, format, use_flags);
 144         if (!combo)
 145                 return -EINVAL;
 146
 147         if (combo->metadata.tiling == TILE_TYPE_DRI) {
 148                 bool needs_alignment = false;
 149 #ifdef __ANDROID__
 150                 /*
 151                  * Currently, the gralloc API doesn't differentiate between allocation time and map
 152                  * time strides. A workaround for amdgpu DRI buffers is to always to align to 256 at
 153                  * allocation time.
 154                  *
 155                  * See b/115946221,b/117942643
 156                  */
 157                 if (use_flags & (BO_USE_SW_MASK))
 158                         needs_alignment = true;
 159 #endif
 160                 // See b/122049612
 161                 if (use_flags & (BO_USE_SCANOUT))
 162                         needs_alignment = true;
 163
 164                 if (needs_alignment) {
 165                         uint32_t bytes_per_pixel = drv_bytes_per_pixel_from_format(format, 0);
 166                         width = ALIGN(width, 256 / bytes_per_pixel);
 167                 }
 168
 169                 return dri_bo_create(bo, width, height, format, use_flags);
 170         }
 171
 172         stride = drv_stride_from_format(format, width, 0);
 173         stride = ALIGN(stride, 256);
 174
 175         drv_bo_from_format(bo, stride, height, format);
 176
 177         memset(&gem_create, 0, sizeof(gem_create));
 178         gem_create.in.bo_size = bo->total_size;
 179         gem_create.in.alignment = 256;
 180         gem_create.in.domain_flags = 0;
 181
 182         if (use_flags & (BO_USE_LINEAR | BO_USE_SW_MASK))
 183                 gem_create.in.domain_flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 184
 185         gem_create.in.domains = AMDGPU_GEM_DOMAIN_GTT;
 186         if (!(use_flags & (BO_USE_SW_READ_OFTEN | BO_USE_SCANOUT)))
 187                 gem_create.in.domain_flags |= AMDGPU_GEM_CREATE_CPU_GTT_USWC;
 188
 189         /* Allocate the buffer with the preferred heap. */
 190         ret = drmCommandWriteRead(drv_get_fd(bo->drv), DRM_AMDGPU_GEM_CREATE, &gem_create,
 191                                   sizeof(gem_create));
 192         if (ret < 0)
 193                 return ret;
 194
 195         for (plane = 0; plane < bo->num_planes; plane++)
 196                 bo->handles[plane].u32 = gem_create.out.handle;
 197
 198         return 0;
 199 }
 200
 201 static int amdgpu_import_bo(struct bo *bo, struct drv_import_fd_data *data)
 202 {
 203         struct combination *combo;
 204         combo = drv_get_combination(bo->drv, data->format, data->use_flags);
 205         if (!combo)
 206                 return -EINVAL;
 207
 208         if (combo->metadata.tiling == TILE_TYPE_DRI)
 209                 return dri_bo_import(bo, data);
 210         else
 211                 return drv_prime_bo_import(bo, data);
 212 }
 213
 214 static int amdgpu_destroy_bo(struct bo *bo)
 215 {
 216         if (bo->priv)
 217                 return dri_bo_destroy(bo);
 218         else
 219                 return drv_gem_bo_destroy(bo);
 220 }
 221
 222 static void *amdgpu_map_bo(struct bo *bo, struct vma *vma, size_t plane, uint32_t map_flags)
 223 {
 224         int ret;
 225         union drm_amdgpu_gem_mmap gem_map;
 226
 227         if (bo->priv)
 228                 return dri_bo_map(bo, vma, plane, map_flags);
 229
 230         memset(&gem_map, 0, sizeof(gem_map));
 231         gem_map.in.handle = bo->handles[plane].u32;
 232
 233         ret = drmIoctl(bo->drv->fd, DRM_IOCTL_AMDGPU_GEM_MMAP, &gem_map);
 234         if (ret) {
 235                 drv_log("DRM_IOCTL_AMDGPU_GEM_MMAP failed\n");
 236                 return MAP_FAILED;
 237         }
 238
 239         vma->length = bo->total_size;
 240
 241         return mmap(0, bo->total_size, drv_get_prot(map_flags), MAP_SHARED, bo->drv->fd,
 242                     gem_map.out.addr_ptr);
 243 }
 244
 245 static int amdgpu_unmap_bo(struct bo *bo, struct vma *vma)
 246 {
 247         if (bo->priv)
 248                 return dri_bo_unmap(bo, vma);
 249         else
 250                 return munmap(vma->addr, vma->length);
 251 }
 252
 253 static int amdgpu_bo_invalidate(struct bo *bo, struct mapping *mapping)
 254 {
 255         int ret;
 256         union drm_amdgpu_gem_wait_idle wait_idle;
 257
 258         if (bo->priv)
 259                 return 0;
 260
 261         memset(&wait_idle, 0, sizeof(wait_idle));
 262         wait_idle.in.handle = bo->handles[0].u32;
 263         wait_idle.in.timeout = AMDGPU_TIMEOUT_INFINITE;
 264
 265         ret = drmCommandWriteRead(bo->drv->fd, DRM_AMDGPU_GEM_WAIT_IDLE, &wait_idle,
 266                                   sizeof(wait_idle));
 267
 268         if (ret < 0) {
 269                 drv_log("DRM_AMDGPU_GEM_WAIT_IDLE failed with %d\n", ret);
 270                 return ret;
 271         }
 272
 273         if (ret == 0 && wait_idle.out.status)
 274                 drv_log("DRM_AMDGPU_GEM_WAIT_IDLE BO is busy\n");
 275
 276         return 0;
 277 }
 278
 279 static uint32_t amdgpu_resolve_format(uint32_t format, uint64_t use_flags)
 280 {
 281         switch (format) {
 282         case DRM_FORMAT_FLEX_IMPLEMENTATION_DEFINED:
 283                 /* Camera subsystem requires NV12. */
 284                 if (use_flags & (BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE))
 285                         return DRM_FORMAT_NV12;
 286                 /*HACK: See b/28671744 */
 287                 return DRM_FORMAT_XBGR8888;
 288         case DRM_FORMAT_FLEX_YCbCr_420_888:
 289                 return DRM_FORMAT_NV12;
 290         default:
 291                 return format;
 292         }
 293 }
 294
 295 const struct backend backend_amdgpu = {
 296         .name = "amdgpu",
 297         .init = amdgpu_init,
 298         .close = amdgpu_close,
 299         .bo_create = amdgpu_create_bo,
 300         .bo_destroy = amdgpu_destroy_bo,
 301         .bo_import = amdgpu_import_bo,
 302         .bo_map = amdgpu_map_bo,
 303         .bo_unmap = amdgpu_unmap_bo,
 304         .bo_invalidate = amdgpu_bo_invalidate,
 305         .resolve_format = amdgpu_resolve_format,
 306 };
 307
 308 #endif