amdgpu.c

   1 /*
   2  * Copyright 2016 The Chromium OS Authors. All rights reserved.
   3  * Use of this source code is governed by a BSD-style license that can be
   4  * found in the LICENSE file.
   5  */
   6 #ifdef DRV_AMDGPU
   7 #include <errno.h>
   8 #include <stdio.h>
   9 #include <stdlib.h>
  10 #include <string.h>
  11 #include <xf86drm.h>
  12 #include <amdgpu_drm.h>
  13 #include <amdgpu.h>
  14
  15 #include "addrinterface.h"
  16 #include "drv_priv.h"
  17 #include "helpers.h"
  18 #include "util.h"
  19
  20 #ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
  21 #define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
  22 #endif
  23
  24 #define mmCC_RB_BACKEND_DISABLE         0x263d
  25 #define mmGB_TILE_MODE0                 0x2644
  26 #define mmGB_MACROTILE_MODE0            0x2664
  27 #define mmGB_ADDR_CONFIG                0x263e
  28 #define mmMC_ARB_RAMCFG                 0x9d8
  29
  30 enum {
  31         FAMILY_UNKNOWN,
  32         FAMILY_SI,
  33         FAMILY_CI,
  34         FAMILY_KV,
  35         FAMILY_VI,
  36         FAMILY_CZ,
  37         FAMILY_PI,
  38         FAMILY_LAST,
  39 };
  40
  41 static struct supported_combination combos[5] = {
  42         {DRM_FORMAT_ARGB8888, DRM_FORMAT_MOD_NONE,
  43                 BO_USE_CURSOR | BO_USE_LINEAR | BO_USE_SW_READ_OFTEN | BO_USE_SW_WRITE_OFTEN},
  44         {DRM_FORMAT_ARGB8888, DRM_FORMAT_MOD_NONE,
  45                 BO_USE_RENDERING | BO_USE_SW_READ_RARELY | BO_USE_SW_WRITE_RARELY},
  46         {DRM_FORMAT_XBGR8888, DRM_FORMAT_MOD_NONE,
  47                 BO_USE_RENDERING | BO_USE_SW_READ_RARELY | BO_USE_SW_WRITE_RARELY},
  48         {DRM_FORMAT_XRGB8888, DRM_FORMAT_MOD_NONE,
  49                 BO_USE_LINEAR | BO_USE_SW_READ_OFTEN | BO_USE_SW_WRITE_OFTEN},
  50         {DRM_FORMAT_XRGB8888, DRM_FORMAT_MOD_NONE,
  51                 BO_USE_RENDERING | BO_USE_SW_READ_RARELY | BO_USE_SW_WRITE_RARELY},
  52 };
  53
  54 static int amdgpu_set_metadata(int fd, uint32_t handle,
  55                                struct amdgpu_bo_metadata *info)
  56 {
  57         struct drm_amdgpu_gem_metadata args = {0};
  58
  59         if (!info)
  60                 return -EINVAL;
  61
  62         args.handle = handle;
  63         args.op = AMDGPU_GEM_METADATA_OP_SET_METADATA;
  64         args.data.flags = info->flags;
  65         args.data.tiling_info = info->tiling_info;
  66
  67         if (info->size_metadata > sizeof(args.data.data))
  68                 return -EINVAL;
  69
  70         if (info->size_metadata) {
  71                 args.data.data_size_bytes = info->size_metadata;
  72                 memcpy(args.data.data, info->umd_metadata, info->size_metadata);
  73         }
  74
  75         return drmCommandWriteRead(fd, DRM_AMDGPU_GEM_METADATA, &args,
  76                                    sizeof(args));
  77 }
  78
  79 static int amdgpu_read_mm_regs(int fd, unsigned dword_offset,
  80                                unsigned count, uint32_t instance,
  81                                uint32_t flags, uint32_t *values)
  82 {
  83         struct drm_amdgpu_info request;
  84
  85         memset(&request, 0, sizeof(request));
  86         request.return_pointer = (uintptr_t) values;
  87         request.return_size = count * sizeof(uint32_t);
  88         request.query = AMDGPU_INFO_READ_MMR_REG;
  89         request.read_mmr_reg.dword_offset = dword_offset;
  90         request.read_mmr_reg.count = count;
  91         request.read_mmr_reg.instance = instance;
  92         request.read_mmr_reg.flags = flags;
  93
  94         return drmCommandWrite(fd, DRM_AMDGPU_INFO, &request,
  95                                sizeof(struct drm_amdgpu_info));
  96 }
  97
  98 static int amdgpu_query_gpu(int fd, struct amdgpu_gpu_info *gpu_info)
  99 {
 100         int ret;
 101         uint32_t instance;
 102
 103         if (!gpu_info)
 104                 return -EINVAL;
 105
 106         instance = AMDGPU_INFO_MMR_SH_INDEX_MASK <<
 107                         AMDGPU_INFO_MMR_SH_INDEX_SHIFT;
 108
 109         ret = amdgpu_read_mm_regs(fd, mmCC_RB_BACKEND_DISABLE, 1, instance, 0,
 110                                   &gpu_info->backend_disable[0]);
 111         if (ret)
 112                 return ret;
 113         /* extract bitfield CC_RB_BACKEND_DISABLE.BACKEND_DISABLE */
 114         gpu_info->backend_disable[0] =
 115                 (gpu_info->backend_disable[0] >> 16) & 0xff;
 116
 117         ret = amdgpu_read_mm_regs(fd, mmGB_TILE_MODE0, 32, 0xffffffff, 0,
 118                                   gpu_info->gb_tile_mode);
 119         if (ret)
 120                 return ret;
 121
 122         ret = amdgpu_read_mm_regs(fd, mmGB_MACROTILE_MODE0, 16, 0xffffffff, 0,
 123                                   gpu_info->gb_macro_tile_mode);
 124         if (ret)
 125                 return ret;
 126
 127         ret = amdgpu_read_mm_regs(fd, mmGB_ADDR_CONFIG, 1, 0xffffffff, 0,
 128                                   &gpu_info->gb_addr_cfg);
 129         if (ret)
 130                 return ret;
 131
 132         ret = amdgpu_read_mm_regs(fd, mmMC_ARB_RAMCFG, 1, 0xffffffff, 0,
 133                                   &gpu_info->mc_arb_ramcfg);
 134         if (ret)
 135                 return ret;
 136
 137         return 0;
 138 }
 139
 140 static void *ADDR_API alloc_sys_mem(const ADDR_ALLOCSYSMEM_INPUT *in)
 141 {
 142         return malloc(in->sizeInBytes);
 143 }
 144
 145 static ADDR_E_RETURNCODE ADDR_API free_sys_mem(const ADDR_FREESYSMEM_INPUT *in)
 146 {
 147         free(in->pVirtAddr);
 148         return ADDR_OK;
 149 }
 150
 151 static int amdgpu_addrlib_compute(void *addrlib, uint32_t width,
 152                                   uint32_t height, uint32_t format,
 153                                   uint32_t usage, uint32_t *tiling_flags,
 154                                   ADDR_COMPUTE_SURFACE_INFO_OUTPUT *addr_out)
 155 {
 156         ADDR_COMPUTE_SURFACE_INFO_INPUT addr_surf_info_in = {0};
 157         ADDR_TILEINFO addr_tile_info = {0};
 158         ADDR_TILEINFO addr_tile_info_out = {0};
 159
 160         addr_surf_info_in.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_INPUT);
 161
 162         /* Set the requested tiling mode. */
 163         addr_surf_info_in.tileMode = ADDR_TM_2D_TILED_THIN1;
 164         if (usage & (BO_USE_CURSOR | BO_USE_LINEAR))
 165                 addr_surf_info_in.tileMode = ADDR_TM_LINEAR_ALIGNED;
 166         if (width <= 16 || height <= 16)
 167                 addr_surf_info_in.tileMode = ADDR_TM_1D_TILED_THIN1;
 168
 169         /* Bits per pixel should be calculated from format*/
 170         addr_surf_info_in.bpp = drv_bpp_from_format(format, 0);
 171         addr_surf_info_in.numSamples = 1;
 172         addr_surf_info_in.width = width;
 173         addr_surf_info_in.height = height;
 174         addr_surf_info_in.numSlices = 1;
 175         addr_surf_info_in.pTileInfo = &addr_tile_info;
 176         addr_surf_info_in.tileIndex = -1;
 177
 178         /* This disables incorrect calculations (hacks) in addrlib. */
 179         addr_surf_info_in.flags.noStencil = 1;
 180
 181         /* Set the micro tile type. */
 182         if (usage & BO_USE_SCANOUT)
 183                 addr_surf_info_in.tileType = ADDR_DISPLAYABLE;
 184         else
 185                 addr_surf_info_in.tileType = ADDR_NON_DISPLAYABLE;
 186
 187         addr_out->size = sizeof(ADDR_COMPUTE_SURFACE_INFO_OUTPUT);
 188         addr_out->pTileInfo = &addr_tile_info_out;
 189
 190         if (AddrComputeSurfaceInfo(addrlib, &addr_surf_info_in,
 191                                    addr_out) != ADDR_OK)
 192                 return -EINVAL;
 193
 194         ADDR_CONVERT_TILEINFOTOHW_INPUT s_in = {0};
 195         ADDR_CONVERT_TILEINFOTOHW_OUTPUT s_out = {0};
 196         ADDR_TILEINFO s_tile_hw_info_out = {0};
 197
 198         s_in.size = sizeof(ADDR_CONVERT_TILEINFOTOHW_INPUT);
 199         /* Convert from real value to HW value */
 200         s_in.reverse = 0;
 201         s_in.pTileInfo = &addr_tile_info_out;
 202         s_in.tileIndex = -1;
 203
 204         s_out.size = sizeof(ADDR_CONVERT_TILEINFOTOHW_OUTPUT);
 205         s_out.pTileInfo = &s_tile_hw_info_out;
 206
 207         if (AddrConvertTileInfoToHW(addrlib, &s_in, &s_out) != ADDR_OK)
 208                 return -EINVAL;
 209
 210         if (addr_out->tileMode >= ADDR_TM_2D_TILED_THIN1)
 211                 /* 2D_TILED_THIN1 */
 212                 *tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 4);
 213         else if (addr_out->tileMode >= ADDR_TM_1D_TILED_THIN1)
 214                 /* 1D_TILED_THIN1 */
 215                 *tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 2);
 216         else
 217                 /* LINEAR_ALIGNED */
 218                 *tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 1);
 219
 220         *tiling_flags |= AMDGPU_TILING_SET(BANK_WIDTH,
 221                         drv_log_base2(addr_tile_info_out.bankWidth));
 222         *tiling_flags |= AMDGPU_TILING_SET(BANK_HEIGHT,
 223                         drv_log_base2(addr_tile_info_out.bankHeight));
 224         *tiling_flags |= AMDGPU_TILING_SET(TILE_SPLIT,
 225                         s_tile_hw_info_out.tileSplitBytes);
 226         *tiling_flags |= AMDGPU_TILING_SET(MACRO_TILE_ASPECT,
 227                         drv_log_base2(addr_tile_info_out.macroAspectRatio));
 228         *tiling_flags |= AMDGPU_TILING_SET(PIPE_CONFIG,
 229                                 s_tile_hw_info_out.pipeConfig);
 230         *tiling_flags |= AMDGPU_TILING_SET(NUM_BANKS, s_tile_hw_info_out.banks);
 231
 232         return 0;
 233 }
 234
 235 static void *amdgpu_addrlib_init(int fd)
 236 {
 237         int ret;
 238         ADDR_CREATE_INPUT addr_create_input = {0};
 239         ADDR_CREATE_OUTPUT addr_create_output = {0};
 240         ADDR_REGISTER_VALUE reg_value = {0};
 241         ADDR_CREATE_FLAGS create_flags = { {0} };
 242         ADDR_E_RETURNCODE addr_ret;
 243
 244         addr_create_input.size = sizeof(ADDR_CREATE_INPUT);
 245         addr_create_output.size = sizeof(ADDR_CREATE_OUTPUT);
 246
 247         struct amdgpu_gpu_info gpu_info = {0};
 248
 249         ret = amdgpu_query_gpu(fd, &gpu_info);
 250
 251         if (ret) {
 252                 fprintf(stderr, "[%s]failed with error =%d\n", __func__, ret);
 253                 return NULL;
 254         }
 255
 256         reg_value.noOfBanks = gpu_info.mc_arb_ramcfg & 0x3;
 257         reg_value.gbAddrConfig = gpu_info.gb_addr_cfg;
 258         reg_value.noOfRanks = (gpu_info.mc_arb_ramcfg & 0x4) >> 2;
 259
 260         reg_value.backendDisables = gpu_info.backend_disable[0];
 261         reg_value.pTileConfig = gpu_info.gb_tile_mode;
 262         reg_value.noOfEntries = sizeof(gpu_info.gb_tile_mode)
 263                         / sizeof(gpu_info.gb_tile_mode[0]);
 264         reg_value.pMacroTileConfig = gpu_info.gb_macro_tile_mode;
 265         reg_value.noOfMacroEntries = sizeof(gpu_info.gb_macro_tile_mode)
 266                         / sizeof(gpu_info.gb_macro_tile_mode[0]);
 267         create_flags.value = 0;
 268         create_flags.useTileIndex = 1;
 269
 270         addr_create_input.chipEngine = CIASICIDGFXENGINE_SOUTHERNISLAND;
 271
 272         addr_create_input.chipFamily = FAMILY_CZ;
 273         addr_create_input.createFlags = create_flags;
 274         addr_create_input.callbacks.allocSysMem = alloc_sys_mem;
 275         addr_create_input.callbacks.freeSysMem = free_sys_mem;
 276         addr_create_input.callbacks.debugPrint = 0;
 277         addr_create_input.regValue = reg_value;
 278
 279         addr_ret = AddrCreate(&addr_create_input, &addr_create_output);
 280
 281         if (addr_ret != ADDR_OK) {
 282                 fprintf(stderr, "[%s]failed error =%d\n", __func__, addr_ret);
 283                 return NULL;
 284         }
 285
 286         return addr_create_output.hLib;
 287 }
 288
 289 static int amdgpu_init(struct driver *drv)
 290 {
 291         void *addrlib;
 292
 293         addrlib = amdgpu_addrlib_init(drv_get_fd(drv));
 294         if (!addrlib)
 295                 return -1;
 296
 297         drv->priv = addrlib;
 298
 299         drv_insert_combinations(drv, combos, ARRAY_SIZE(combos));
 300         return drv_add_kms_flags(drv);
 301 }
 302
 303 static void amdgpu_close(struct driver *drv)
 304 {
 305         AddrDestroy(drv->priv);
 306         drv->priv = NULL;
 307 }
 308
 309 static int amdgpu_bo_create(struct bo *bo, uint32_t width, uint32_t height,
 310                             uint32_t format, uint32_t usage)
 311 {
 312         void *addrlib = bo->drv->priv;
 313         union drm_amdgpu_gem_create gem_create;
 314         struct amdgpu_bo_metadata metadata = {0};
 315         ADDR_COMPUTE_SURFACE_INFO_OUTPUT addr_out = {0};
 316         uint32_t tiling_flags = 0;
 317         int ret;
 318
 319         if (amdgpu_addrlib_compute(addrlib, width,
 320                                    height, format, usage,
 321                                    &tiling_flags,
 322                                    &addr_out) < 0)
 323                 return -EINVAL;
 324
 325         bo->tiling = tiling_flags;
 326         bo->offsets[0] = 0;
 327         bo->sizes[0] = addr_out.surfSize;
 328         bo->strides[0] = addr_out.pixelPitch
 329                 * DIV_ROUND_UP(addr_out.pixelBits, 8);
 330
 331         memset(&gem_create, 0, sizeof(gem_create));
 332         gem_create.in.bo_size = bo->sizes[0];
 333         gem_create.in.alignment = addr_out.baseAlign;
 334         /* Set the placement. */
 335         gem_create.in.domains = AMDGPU_GEM_DOMAIN_VRAM;
 336         gem_create.in.domain_flags = usage;
 337
 338         /* Allocate the buffer with the preferred heap. */
 339         ret = drmCommandWriteRead(drv_get_fd(bo->drv), DRM_AMDGPU_GEM_CREATE,
 340                                   &gem_create, sizeof(gem_create));
 341
 342         if (ret < 0)
 343                 return ret;
 344
 345         bo->handles[0].u32 = gem_create.out.handle;
 346
 347         metadata.tiling_info = tiling_flags;
 348
 349         ret = amdgpu_set_metadata(drv_get_fd(bo->drv),
 350                                   bo->handles[0].u32, &metadata);
 351
 352         return ret;
 353 }
 354
 355 struct backend backend_amdgpu = {
 356         .name = "amdgpu",
 357         .init = amdgpu_init,
 358         .close = amdgpu_close,
 359         .bo_create = amdgpu_bo_create,
 360         .bo_destroy = drv_gem_bo_destroy,
 361 };
 362
 363 #endif
 364