amdgpu.c

   1 /*
   2  * Copyright (c) 2016 The Chromium OS Authors. All rights reserved.
   3  * Use of this source code is governed by a BSD-style license that can be
   4  * found in the LICENSE file.
   5  */
   6 #ifdef DRV_AMDGPU
   7 #include <errno.h>
   8 #include <stdio.h>
   9 #include <stdlib.h>
  10 #include <string.h>
  11 #include <xf86drm.h>
  12 #include <amdgpu_drm.h>
  13 #include <amdgpu.h>
  14
  15 #include "addrinterface.h"
  16 #include "drv_priv.h"
  17 #include "helpers.h"
  18 #include "util.h"
  19
  20 #ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
  21 #define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
  22 #endif
  23
  24 #define mmCC_RB_BACKEND_DISABLE         0x263d
  25 #define mmGB_TILE_MODE0                 0x2644
  26 #define mmGB_MACROTILE_MODE0            0x2664
  27 #define mmGB_ADDR_CONFIG                0x263e
  28 #define mmMC_ARB_RAMCFG                 0x9d8
  29
  30 enum {
  31         FAMILY_UNKNOWN,
  32         FAMILY_SI,
  33         FAMILY_CI,
  34         FAMILY_KV,
  35         FAMILY_VI,
  36         FAMILY_CZ,
  37         FAMILY_PI,
  38         FAMILY_LAST,
  39 };
  40
  41 static int amdgpu_set_metadata(int fd, uint32_t handle,
  42                                struct amdgpu_bo_metadata *info)
  43 {
  44         struct drm_amdgpu_gem_metadata args = {0};
  45
  46         if (!info)
  47                 return -EINVAL;
  48
  49         args.handle = handle;
  50         args.op = AMDGPU_GEM_METADATA_OP_SET_METADATA;
  51         args.data.flags = info->flags;
  52         args.data.tiling_info = info->tiling_info;
  53
  54         if (info->size_metadata > sizeof(args.data.data))
  55                 return -EINVAL;
  56
  57         if (info->size_metadata) {
  58                 args.data.data_size_bytes = info->size_metadata;
  59                 memcpy(args.data.data, info->umd_metadata, info->size_metadata);
  60         }
  61
  62         return drmCommandWriteRead(fd, DRM_AMDGPU_GEM_METADATA, &args,
  63                                    sizeof(args));
  64 }
  65
  66 static int amdgpu_read_mm_regs(int fd, unsigned dword_offset,
  67                                unsigned count, uint32_t instance,
  68                                uint32_t flags, uint32_t *values)
  69 {
  70         struct drm_amdgpu_info request;
  71
  72         memset(&request, 0, sizeof(request));
  73         request.return_pointer = (uintptr_t) values;
  74         request.return_size = count * sizeof(uint32_t);
  75         request.query = AMDGPU_INFO_READ_MMR_REG;
  76         request.read_mmr_reg.dword_offset = dword_offset;
  77         request.read_mmr_reg.count = count;
  78         request.read_mmr_reg.instance = instance;
  79         request.read_mmr_reg.flags = flags;
  80
  81         return drmCommandWrite(fd, DRM_AMDGPU_INFO, &request,
  82                                sizeof(struct drm_amdgpu_info));
  83 }
  84
  85 static int amdgpu_query_gpu(int fd, struct amdgpu_gpu_info *gpu_info)
  86 {
  87         int ret;
  88         uint32_t instance;
  89
  90         if (!gpu_info)
  91                 return -EINVAL;
  92
  93         instance = AMDGPU_INFO_MMR_SH_INDEX_MASK <<
  94                         AMDGPU_INFO_MMR_SH_INDEX_SHIFT;
  95
  96         ret = amdgpu_read_mm_regs(fd, mmCC_RB_BACKEND_DISABLE, 1, instance, 0,
  97                                   &gpu_info->backend_disable[0]);
  98         if (ret)
  99                 return ret;
 100         /* extract bitfield CC_RB_BACKEND_DISABLE.BACKEND_DISABLE */
 101         gpu_info->backend_disable[0] =
 102                 (gpu_info->backend_disable[0] >> 16) & 0xff;
 103
 104         ret = amdgpu_read_mm_regs(fd, mmGB_TILE_MODE0, 32, 0xffffffff, 0,
 105                                   gpu_info->gb_tile_mode);
 106         if (ret)
 107                 return ret;
 108
 109         ret = amdgpu_read_mm_regs(fd, mmGB_MACROTILE_MODE0, 16, 0xffffffff, 0,
 110                                   gpu_info->gb_macro_tile_mode);
 111         if (ret)
 112                 return ret;
 113
 114         ret = amdgpu_read_mm_regs(fd, mmGB_ADDR_CONFIG, 1, 0xffffffff, 0,
 115                                   &gpu_info->gb_addr_cfg);
 116         if (ret)
 117                 return ret;
 118
 119         ret = amdgpu_read_mm_regs(fd, mmMC_ARB_RAMCFG, 1, 0xffffffff, 0,
 120                                   &gpu_info->mc_arb_ramcfg);
 121         if (ret)
 122                 return ret;
 123
 124         return 0;
 125 }
 126
 127 static void *ADDR_API alloc_sys_mem(const ADDR_ALLOCSYSMEM_INPUT *in)
 128 {
 129         return malloc(in->sizeInBytes);
 130 }
 131
 132 static ADDR_E_RETURNCODE ADDR_API free_sys_mem(const ADDR_FREESYSMEM_INPUT *in)
 133 {
 134         free(in->pVirtAddr);
 135         return ADDR_OK;
 136 }
 137
 138 static int amdgpu_addrlib_compute(void *addrlib, uint32_t width,
 139                                   uint32_t height, uint32_t format,
 140                                   uint32_t usage, uint32_t *tiling_flags,
 141                                   ADDR_COMPUTE_SURFACE_INFO_OUTPUT *addr_out)
 142 {
 143         ADDR_COMPUTE_SURFACE_INFO_INPUT addr_surf_info_in = {0};
 144         ADDR_TILEINFO addr_tile_info = {0};
 145         ADDR_TILEINFO addr_tile_info_out = {0};
 146
 147         addr_surf_info_in.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_INPUT);
 148
 149         /* Set the requested tiling mode. */
 150         addr_surf_info_in.tileMode = ADDR_TM_2D_TILED_THIN1;
 151         if (usage & (DRV_BO_USE_CURSOR | DRV_BO_USE_LINEAR))
 152                 addr_surf_info_in.tileMode = ADDR_TM_LINEAR_ALIGNED;
 153         if (width <= 16 || height <= 16)
 154                 addr_surf_info_in.tileMode = ADDR_TM_1D_TILED_THIN1;
 155
 156         /* Bits per pixel should be calculated from format*/
 157         addr_surf_info_in.bpp = drv_bpp_from_format(format, 0);
 158         addr_surf_info_in.numSamples = 1;
 159         addr_surf_info_in.width = width;
 160         addr_surf_info_in.height = height;
 161         addr_surf_info_in.numSlices = 1;
 162         addr_surf_info_in.pTileInfo = &addr_tile_info;
 163         addr_surf_info_in.tileIndex = -1;
 164
 165         /* This disables incorrect calculations (hacks) in addrlib. */
 166         addr_surf_info_in.flags.noStencil = 1;
 167
 168         /* Set the micro tile type. */
 169         if (usage & DRV_BO_USE_SCANOUT)
 170                 addr_surf_info_in.tileType = ADDR_DISPLAYABLE;
 171         else
 172                 addr_surf_info_in.tileType = ADDR_NON_DISPLAYABLE;
 173
 174         addr_out->size = sizeof(ADDR_COMPUTE_SURFACE_INFO_OUTPUT);
 175         addr_out->pTileInfo = &addr_tile_info_out;
 176
 177         if (AddrComputeSurfaceInfo(addrlib, &addr_surf_info_in,
 178                                    addr_out) != ADDR_OK)
 179                 return -EINVAL;
 180
 181         ADDR_CONVERT_TILEINFOTOHW_INPUT s_in = {0};
 182         ADDR_CONVERT_TILEINFOTOHW_OUTPUT s_out = {0};
 183         ADDR_TILEINFO s_tile_hw_info_out = {0};
 184
 185         s_in.size = sizeof(ADDR_CONVERT_TILEINFOTOHW_INPUT);
 186         /* Convert from real value to HW value */
 187         s_in.reverse = 0;
 188         s_in.pTileInfo = &addr_tile_info_out;
 189         s_in.tileIndex = -1;
 190
 191         s_out.size = sizeof(ADDR_CONVERT_TILEINFOTOHW_OUTPUT);
 192         s_out.pTileInfo = &s_tile_hw_info_out;
 193
 194         if (AddrConvertTileInfoToHW(addrlib, &s_in, &s_out) != ADDR_OK)
 195                 return -EINVAL;
 196
 197         if (addr_out->tileMode >= ADDR_TM_2D_TILED_THIN1)
 198                 /* 2D_TILED_THIN1 */
 199                 *tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 4);
 200         else if (addr_out->tileMode >= ADDR_TM_1D_TILED_THIN1)
 201                 /* 1D_TILED_THIN1 */
 202                 *tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 2);
 203         else
 204                 /* LINEAR_ALIGNED */
 205                 *tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 1);
 206
 207         *tiling_flags |= AMDGPU_TILING_SET(BANK_WIDTH,
 208                         drv_log_base2(addr_tile_info_out.bankWidth));
 209         *tiling_flags |= AMDGPU_TILING_SET(BANK_HEIGHT,
 210                         drv_log_base2(addr_tile_info_out.bankHeight));
 211         *tiling_flags |= AMDGPU_TILING_SET(TILE_SPLIT,
 212                         s_tile_hw_info_out.tileSplitBytes);
 213         *tiling_flags |= AMDGPU_TILING_SET(MACRO_TILE_ASPECT,
 214                         drv_log_base2(addr_tile_info_out.macroAspectRatio));
 215         *tiling_flags |= AMDGPU_TILING_SET(PIPE_CONFIG,
 216                                 s_tile_hw_info_out.pipeConfig);
 217         *tiling_flags |= AMDGPU_TILING_SET(NUM_BANKS, s_tile_hw_info_out.banks);
 218
 219         return 0;
 220 }
 221
 222 static void *amdgpu_addrlib_init(int fd)
 223 {
 224         int ret;
 225         ADDR_CREATE_INPUT addr_create_input = {0};
 226         ADDR_CREATE_OUTPUT addr_create_output = {0};
 227         ADDR_REGISTER_VALUE reg_value = {0};
 228         ADDR_CREATE_FLAGS create_flags = { {0} };
 229         ADDR_E_RETURNCODE addr_ret;
 230
 231         addr_create_input.size = sizeof(ADDR_CREATE_INPUT);
 232         addr_create_output.size = sizeof(ADDR_CREATE_OUTPUT);
 233
 234         struct amdgpu_gpu_info gpu_info = {0};
 235
 236         ret = amdgpu_query_gpu(fd, &gpu_info);
 237
 238         if (ret) {
 239                 fprintf(stderr, "[%s]failed with error =%d\n", __func__, ret);
 240                 return NULL;
 241         }
 242
 243         reg_value.noOfBanks = gpu_info.mc_arb_ramcfg & 0x3;
 244         reg_value.gbAddrConfig = gpu_info.gb_addr_cfg;
 245         reg_value.noOfRanks = (gpu_info.mc_arb_ramcfg & 0x4) >> 2;
 246
 247         reg_value.backendDisables = gpu_info.backend_disable[0];
 248         reg_value.pTileConfig = gpu_info.gb_tile_mode;
 249         reg_value.noOfEntries = sizeof(gpu_info.gb_tile_mode)
 250                         / sizeof(gpu_info.gb_tile_mode[0]);
 251         reg_value.pMacroTileConfig = gpu_info.gb_macro_tile_mode;
 252         reg_value.noOfMacroEntries = sizeof(gpu_info.gb_macro_tile_mode)
 253                         / sizeof(gpu_info.gb_macro_tile_mode[0]);
 254         create_flags.value = 0;
 255         create_flags.useTileIndex = 1;
 256
 257         addr_create_input.chipEngine = CIASICIDGFXENGINE_SOUTHERNISLAND;
 258
 259         addr_create_input.chipFamily = FAMILY_CZ;
 260         addr_create_input.createFlags = create_flags;
 261         addr_create_input.callbacks.allocSysMem = alloc_sys_mem;
 262         addr_create_input.callbacks.freeSysMem = free_sys_mem;
 263         addr_create_input.callbacks.debugPrint = 0;
 264         addr_create_input.regValue = reg_value;
 265
 266         addr_ret = AddrCreate(&addr_create_input, &addr_create_output);
 267
 268         if (addr_ret != ADDR_OK) {
 269                 fprintf(stderr, "[%s]failed error =%d\n", __func__, addr_ret);
 270                 return NULL;
 271         }
 272
 273         return addr_create_output.hLib;
 274 }
 275
 276 static int amdgpu_init(struct driver *drv)
 277 {
 278         void *addrlib;
 279
 280         addrlib = amdgpu_addrlib_init(drv_get_fd(drv));
 281         if (!addrlib)
 282                 return -1;
 283
 284         drv->priv = addrlib;
 285
 286         return 0;
 287 }
 288
 289 static void amdgpu_close(struct driver *drv)
 290 {
 291         AddrDestroy(drv->priv);
 292         drv->priv = NULL;
 293 }
 294
 295 static int amdgpu_bo_create(struct bo *bo, uint32_t width, uint32_t height,
 296                             uint32_t format, uint32_t usage)
 297 {
 298         void *addrlib = bo->drv->priv;
 299         union drm_amdgpu_gem_create gem_create;
 300         struct amdgpu_bo_metadata metadata = {0};
 301         ADDR_COMPUTE_SURFACE_INFO_OUTPUT addr_out = {0};
 302         uint32_t tiling_flags = 0;
 303         int ret;
 304
 305         if (amdgpu_addrlib_compute(addrlib, width,
 306                                    height, format, usage,
 307                                    &tiling_flags,
 308                                    &addr_out) < 0)
 309                 return -EINVAL;
 310
 311         bo->tiling = tiling_flags;
 312         bo->offsets[0] = 0;
 313         bo->sizes[0] = addr_out.surfSize;
 314         bo->strides[0] = addr_out.pixelPitch
 315                 * DIV_ROUND_UP(addr_out.pixelBits, 8);
 316
 317         memset(&gem_create, 0, sizeof(gem_create));
 318         gem_create.in.bo_size = bo->sizes[0];
 319         gem_create.in.alignment = addr_out.baseAlign;
 320         /* Set the placement. */
 321         gem_create.in.domains = AMDGPU_GEM_DOMAIN_VRAM;
 322         gem_create.in.domain_flags = usage;
 323
 324         /* Allocate the buffer with the preferred heap. */
 325         ret = drmCommandWriteRead(drv_get_fd(bo->drv), DRM_AMDGPU_GEM_CREATE,
 326                                   &gem_create, sizeof(gem_create));
 327
 328         if (ret < 0)
 329                 return ret;
 330
 331         bo->handles[0].u32 = gem_create.out.handle;
 332
 333         metadata.tiling_info = tiling_flags;
 334
 335         ret = amdgpu_set_metadata(drv_get_fd(bo->drv),
 336                                   bo->handles[0].u32, &metadata);
 337
 338         return ret;
 339 }
 340
 341 const struct backend backend_amdgpu = {
 342         .name = "amdgpu",
 343         .init = amdgpu_init,
 344         .close = amdgpu_close,
 345         .bo_create = amdgpu_bo_create,
 346         .bo_destroy = drv_gem_bo_destroy,
 347         .format_list = {
 348                 /* Linear support */
 349                 {DRM_FORMAT_XRGB8888, DRV_BO_USE_SCANOUT | DRV_BO_USE_LINEAR},
 350                 {DRM_FORMAT_ARGB8888, DRV_BO_USE_SCANOUT | DRV_BO_USE_CURSOR | DRV_BO_USE_LINEAR},
 351                 /* Blocklinear support */
 352                 {DRM_FORMAT_XRGB8888, DRV_BO_USE_SCANOUT | DRV_BO_USE_RENDERING},
 353                 {DRM_FORMAT_ARGB8888, DRV_BO_USE_SCANOUT | DRV_BO_USE_RENDERING},
 354                 {DRM_FORMAT_XBGR8888, DRV_BO_USE_SCANOUT | DRV_BO_USE_RENDERING},
 355         }
 356 };
 357
 358 #endif
 359