i915.c

   1 /*
   2  * Copyright 2014 The Chromium OS Authors. All rights reserved.
   3  * Use of this source code is governed by a BSD-style license that can be
   4  * found in the LICENSE file.
   5  */
   6
   7 #ifdef DRV_I915
   8
   9 #include <errno.h>
  10 #include <i915_drm.h>
  11 #include <stdio.h>
  12 #include <string.h>
  13 #include <sys/mman.h>
  14 #include <xf86drm.h>
  15
  16 #include "drv_priv.h"
  17 #include "helpers.h"
  18 #include "util.h"
  19
  20 #define I915_CACHELINE_SIZE 64
  21 #define I915_CACHELINE_MASK (I915_CACHELINE_SIZE - 1)
  22
  23 static const uint32_t render_target_formats[] = { DRM_FORMAT_ARGB1555, DRM_FORMAT_ABGR8888,
  24                                                   DRM_FORMAT_ARGB8888, DRM_FORMAT_RGB565,
  25                                                   DRM_FORMAT_XBGR8888, DRM_FORMAT_XRGB1555,
  26                                                   DRM_FORMAT_XRGB8888 };
  27
  28 static const uint32_t tileable_texture_source_formats[] = { DRM_FORMAT_GR88, DRM_FORMAT_NV12,
  29                                                             DRM_FORMAT_R8, DRM_FORMAT_UYVY,
  30                                                             DRM_FORMAT_YUYV };
  31
  32 static const uint32_t texture_source_formats[] = { DRM_FORMAT_YVU420, DRM_FORMAT_YVU420_ANDROID };
  33
  34 struct i915_device {
  35         uint32_t gen;
  36         int32_t has_llc;
  37 };
  38
  39 static uint32_t i915_get_gen(int device_id)
  40 {
  41         const uint16_t gen3_ids[] = { 0x2582, 0x2592, 0x2772, 0x27A2, 0x27AE,
  42                                       0x29C2, 0x29B2, 0x29D2, 0xA001, 0xA011 };
  43         unsigned i;
  44         for (i = 0; i < ARRAY_SIZE(gen3_ids); i++)
  45                 if (gen3_ids[i] == device_id)
  46                         return 3;
  47
  48         return 4;
  49 }
  50
  51 static int i915_add_kms_item(struct driver *drv, const struct kms_item *item)
  52 {
  53         uint32_t i;
  54         struct combination *combo;
  55
  56         /*
  57          * Older hardware can't scanout Y-tiled formats. Newer devices can, and
  58          * report this functionality via format modifiers.
  59          */
  60         for (i = 0; i < drv->combos.size; i++) {
  61                 combo = &drv->combos.data[i];
  62                 if (combo->format != item->format)
  63                         continue;
  64
  65                 if (item->modifier == DRM_FORMAT_MOD_NONE &&
  66                     combo->metadata.tiling == I915_TILING_X) {
  67                         /*
  68                          * FIXME: drv_query_kms() does not report the available modifiers
  69                          * yet, but we know that all hardware can scanout from X-tiled
  70                          * buffers, so let's add this to our combinations, except for
  71                          * cursor, which must not be tiled.
  72                          */
  73                         combo->use_flags |= item->use_flags & ~BO_USE_CURSOR;
  74                 }
  75
  76                 if (combo->metadata.modifier == item->modifier)
  77                         combo->use_flags |= item->use_flags;
  78         }
  79
  80         return 0;
  81 }
  82
  83 static int i915_add_combinations(struct driver *drv)
  84 {
  85         int ret;
  86         uint32_t i, num_items;
  87         struct kms_item *items;
  88         struct format_metadata metadata;
  89         uint64_t render_use_flags, texture_use_flags;
  90
  91         render_use_flags = BO_USE_RENDER_MASK;
  92         texture_use_flags = BO_USE_TEXTURE_MASK;
  93
  94         metadata.tiling = I915_TILING_NONE;
  95         metadata.priority = 1;
  96         metadata.modifier = DRM_FORMAT_MOD_NONE;
  97
  98         ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
  99                                    &metadata, render_use_flags);
 100         if (ret)
 101                 return ret;
 102
 103         ret = drv_add_combinations(drv, texture_source_formats, ARRAY_SIZE(texture_source_formats),
 104                                    &metadata, texture_use_flags);
 105         if (ret)
 106                 return ret;
 107
 108         ret = drv_add_combinations(drv, tileable_texture_source_formats,
 109                                    ARRAY_SIZE(tileable_texture_source_formats), &metadata,
 110                                    texture_use_flags);
 111         if (ret)
 112                 return ret;
 113
 114         drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
 115         drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
 116
 117         /* IPU3 camera ISP supports only NV12 output. */
 118         drv_modify_combination(drv, DRM_FORMAT_NV12, &metadata,
 119                                BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE);
 120         /*
 121          * R8 format is used for Android's HAL_PIXEL_FORMAT_BLOB and is used for JPEG snapshots
 122          * from camera.
 123          */
 124         drv_modify_combination(drv, DRM_FORMAT_R8, &metadata,
 125                                BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE);
 126
 127         render_use_flags &= ~BO_USE_RENDERSCRIPT;
 128         render_use_flags &= ~BO_USE_SW_WRITE_OFTEN;
 129         render_use_flags &= ~BO_USE_SW_READ_OFTEN;
 130         render_use_flags &= ~BO_USE_LINEAR;
 131
 132         texture_use_flags &= ~BO_USE_RENDERSCRIPT;
 133         texture_use_flags &= ~BO_USE_SW_WRITE_OFTEN;
 134         texture_use_flags &= ~BO_USE_SW_READ_OFTEN;
 135         texture_use_flags &= ~BO_USE_LINEAR;
 136
 137         metadata.tiling = I915_TILING_X;
 138         metadata.priority = 2;
 139         metadata.modifier = I915_FORMAT_MOD_X_TILED;
 140
 141         ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
 142                                    &metadata, render_use_flags);
 143         if (ret)
 144                 return ret;
 145
 146         ret = drv_add_combinations(drv, tileable_texture_source_formats,
 147                                    ARRAY_SIZE(tileable_texture_source_formats), &metadata,
 148                                    texture_use_flags);
 149         if (ret)
 150                 return ret;
 151
 152         metadata.tiling = I915_TILING_Y;
 153         metadata.priority = 3;
 154         metadata.modifier = I915_FORMAT_MOD_Y_TILED;
 155
 156         ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
 157                                    &metadata, render_use_flags);
 158         if (ret)
 159                 return ret;
 160
 161         ret = drv_add_combinations(drv, tileable_texture_source_formats,
 162                                    ARRAY_SIZE(tileable_texture_source_formats), &metadata,
 163                                    texture_use_flags);
 164         if (ret)
 165                 return ret;
 166
 167         items = drv_query_kms(drv, &num_items);
 168         if (!items || !num_items)
 169                 return 0;
 170
 171         for (i = 0; i < num_items; i++) {
 172                 ret = i915_add_kms_item(drv, &items[i]);
 173                 if (ret) {
 174                         free(items);
 175                         return ret;
 176                 }
 177         }
 178
 179         free(items);
 180         return 0;
 181 }
 182
 183 static int i915_align_dimensions(struct bo *bo, uint32_t tiling, uint32_t *stride,
 184                                  uint32_t *aligned_height)
 185 {
 186         struct i915_device *i915 = bo->drv->priv;
 187         uint32_t horizontal_alignment = 4;
 188         uint32_t vertical_alignment = 4;
 189
 190         switch (tiling) {
 191         default:
 192         case I915_TILING_NONE:
 193                 horizontal_alignment = 64;
 194                 break;
 195
 196         case I915_TILING_X:
 197                 horizontal_alignment = 512;
 198                 vertical_alignment = 8;
 199                 break;
 200
 201         case I915_TILING_Y:
 202                 if (i915->gen == 3) {
 203                         horizontal_alignment = 512;
 204                         vertical_alignment = 8;
 205                 } else {
 206                         horizontal_alignment = 128;
 207                         vertical_alignment = 32;
 208                 }
 209                 break;
 210         }
 211
 212         /*
 213          * The alignment calculated above is based on the full size luma plane and to have chroma
 214          * planes properly aligned with subsampled formats, we need to multiply luma alignment by
 215          * subsampling factor.
 216          */
 217         switch (bo->format) {
 218         case DRM_FORMAT_YVU420_ANDROID:
 219         case DRM_FORMAT_YVU420:
 220                 horizontal_alignment *= 2;
 221         /* Fall through */
 222         case DRM_FORMAT_NV12:
 223                 vertical_alignment *= 2;
 224                 break;
 225         }
 226
 227         /*
 228          * For multi-planar formats we must be aligned to 16
 229          */
 230         if (bo->num_planes > 1)
 231                 vertical_alignment = MAX(vertical_alignment, 16);
 232
 233         *aligned_height = ALIGN(bo->height, vertical_alignment);
 234         if (i915->gen > 3) {
 235                 *stride = ALIGN(*stride, horizontal_alignment);
 236         } else {
 237                 while (*stride > horizontal_alignment)
 238                         horizontal_alignment <<= 1;
 239
 240                 *stride = horizontal_alignment;
 241         }
 242
 243         if (i915->gen <= 3 && *stride > 8192)
 244                 return -EINVAL;
 245
 246         return 0;
 247 }
 248
 249 static void i915_clflush(void *start, size_t size)
 250 {
 251         void *p = (void *)(((uintptr_t)start) & ~I915_CACHELINE_MASK);
 252         void *end = (void *)((uintptr_t)start + size);
 253
 254         __builtin_ia32_mfence();
 255         while (p < end) {
 256                 __builtin_ia32_clflush(p);
 257                 p = (void *)((uintptr_t)p + I915_CACHELINE_SIZE);
 258         }
 259 }
 260
 261 static int i915_init(struct driver *drv)
 262 {
 263         int ret;
 264         int device_id;
 265         struct i915_device *i915;
 266         drm_i915_getparam_t get_param;
 267
 268         i915 = calloc(1, sizeof(*i915));
 269         if (!i915)
 270                 return -ENOMEM;
 271
 272         memset(&get_param, 0, sizeof(get_param));
 273         get_param.param = I915_PARAM_CHIPSET_ID;
 274         get_param.value = &device_id;
 275         ret = drmIoctl(drv->fd, DRM_IOCTL_I915_GETPARAM, &get_param);
 276         if (ret) {
 277                 fprintf(stderr, "drv: Failed to get I915_PARAM_CHIPSET_ID\n");
 278                 free(i915);
 279                 return -EINVAL;
 280         }
 281
 282         i915->gen = i915_get_gen(device_id);
 283
 284         memset(&get_param, 0, sizeof(get_param));
 285         get_param.param = I915_PARAM_HAS_LLC;
 286         get_param.value = &i915->has_llc;
 287         ret = drmIoctl(drv->fd, DRM_IOCTL_I915_GETPARAM, &get_param);
 288         if (ret) {
 289                 fprintf(stderr, "drv: Failed to get I915_PARAM_HAS_LLC\n");
 290                 free(i915);
 291                 return -EINVAL;
 292         }
 293
 294         drv->priv = i915;
 295
 296         return i915_add_combinations(drv);
 297 }
 298
 299 static int i915_bo_create(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
 300                           uint64_t use_flags)
 301 {
 302         int ret;
 303         size_t plane;
 304         uint32_t stride;
 305         struct drm_i915_gem_create gem_create;
 306         struct drm_i915_gem_set_tiling gem_set_tiling;
 307         struct combination *combo;
 308
 309         combo = drv_get_combination(bo->drv, format, use_flags);
 310         if (!combo)
 311                 return -EINVAL;
 312
 313         bo->tiling = combo->metadata.tiling;
 314
 315         stride = drv_stride_from_format(format, width, 0);
 316
 317         ret = i915_align_dimensions(bo, bo->tiling, &stride, &height);
 318         if (ret)
 319                 return ret;
 320
 321         /*
 322          * HAL_PIXEL_FORMAT_YV12 requires the buffer height not be aligned, but we need to keep
 323          * total size as with aligned height to ensure enough padding space after each plane to
 324          * satisfy GPU alignment requirements.
 325          *
 326          * We do it by first calling drv_bo_from_format() with aligned height and
 327          * DRM_FORMAT_YVU420, which allows height alignment, saving the total size it calculates
 328          * and then calling it again with requested parameters.
 329          *
 330          * This relies on the fact that i965 driver uses separate surfaces for each plane and
 331          * contents of padding bytes is not affected, as it is only used to satisfy GPU cache
 332          * requests.
 333          *
 334          * This is enforced by Mesa in src/intel/isl/isl_gen8.c, inside
 335          * isl_gen8_choose_image_alignment_el(), which is used for GEN9 and GEN8.
 336          */
 337         if (format == DRM_FORMAT_YVU420_ANDROID) {
 338                 uint32_t unaligned_height = bo->height;
 339                 size_t total_size;
 340
 341                 drv_bo_from_format(bo, stride, height, DRM_FORMAT_YVU420);
 342                 total_size = bo->total_size;
 343                 drv_bo_from_format(bo, stride, unaligned_height, format);
 344                 bo->total_size = total_size;
 345         } else {
 346                 drv_bo_from_format(bo, stride, height, format);
 347         }
 348
 349         /*
 350          * Quoting Mesa ISL library:
 351          *
 352          *    - For linear surfaces, additional padding of 64 bytes is required at
 353          *      the bottom of the surface. This is in addition to the padding
 354          *      required above.
 355          */
 356         if (bo->tiling == I915_TILING_NONE)
 357                 bo->total_size += 64;
 358
 359         memset(&gem_create, 0, sizeof(gem_create));
 360         gem_create.size = bo->total_size;
 361
 362         ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_CREATE, &gem_create);
 363         if (ret) {
 364                 fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_CREATE failed (size=%llu)\n",
 365                         gem_create.size);
 366                 return ret;
 367         }
 368
 369         for (plane = 0; plane < bo->num_planes; plane++)
 370                 bo->handles[plane].u32 = gem_create.handle;
 371
 372         memset(&gem_set_tiling, 0, sizeof(gem_set_tiling));
 373         gem_set_tiling.handle = bo->handles[0].u32;
 374         gem_set_tiling.tiling_mode = bo->tiling;
 375         gem_set_tiling.stride = bo->strides[0];
 376
 377         ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_SET_TILING, &gem_set_tiling);
 378         if (ret) {
 379                 struct drm_gem_close gem_close;
 380                 memset(&gem_close, 0, sizeof(gem_close));
 381                 gem_close.handle = bo->handles[0].u32;
 382                 drmIoctl(bo->drv->fd, DRM_IOCTL_GEM_CLOSE, &gem_close);
 383
 384                 fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_SET_TILING failed with %d", errno);
 385                 return -errno;
 386         }
 387
 388         return 0;
 389 }
 390
 391 static void i915_close(struct driver *drv)
 392 {
 393         free(drv->priv);
 394         drv->priv = NULL;
 395 }
 396
 397 static int i915_bo_import(struct bo *bo, struct drv_import_fd_data *data)
 398 {
 399         int ret;
 400         struct drm_i915_gem_get_tiling gem_get_tiling;
 401
 402         ret = drv_prime_bo_import(bo, data);
 403         if (ret)
 404                 return ret;
 405
 406         /* TODO(gsingh): export modifiers and get rid of backdoor tiling. */
 407         memset(&gem_get_tiling, 0, sizeof(gem_get_tiling));
 408         gem_get_tiling.handle = bo->handles[0].u32;
 409
 410         ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_GET_TILING, &gem_get_tiling);
 411         if (ret) {
 412                 drv_gem_bo_destroy(bo);
 413                 fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_GET_TILING failed.");
 414                 return ret;
 415         }
 416
 417         bo->tiling = gem_get_tiling.tiling_mode;
 418         return 0;
 419 }
 420
 421 static void *i915_bo_map(struct bo *bo, struct map_info *data, size_t plane, uint32_t map_flags)
 422 {
 423         int ret;
 424         void *addr;
 425         struct drm_i915_gem_set_domain set_domain;
 426
 427         memset(&set_domain, 0, sizeof(set_domain));
 428         set_domain.handle = bo->handles[0].u32;
 429         if (bo->tiling == I915_TILING_NONE) {
 430                 struct drm_i915_gem_mmap gem_map;
 431                 memset(&gem_map, 0, sizeof(gem_map));
 432
 433                 if ((bo->use_flags & BO_USE_SCANOUT) && !(bo->use_flags & BO_USE_RENDERSCRIPT))
 434                         gem_map.flags = I915_MMAP_WC;
 435
 436                 gem_map.handle = bo->handles[0].u32;
 437                 gem_map.offset = 0;
 438                 gem_map.size = bo->total_size;
 439
 440                 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_MMAP, &gem_map);
 441                 if (ret) {
 442                         fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_MMAP failed\n");
 443                         return MAP_FAILED;
 444                 }
 445
 446                 addr = (void *)(uintptr_t)gem_map.addr_ptr;
 447                 set_domain.read_domains = I915_GEM_DOMAIN_CPU;
 448                 set_domain.write_domain = I915_GEM_DOMAIN_CPU;
 449
 450         } else {
 451                 struct drm_i915_gem_mmap_gtt gem_map;
 452                 memset(&gem_map, 0, sizeof(gem_map));
 453
 454                 gem_map.handle = bo->handles[0].u32;
 455
 456                 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_MMAP_GTT, &gem_map);
 457                 if (ret) {
 458                         fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_MMAP_GTT failed\n");
 459                         return MAP_FAILED;
 460                 }
 461
 462                 addr = mmap(0, bo->total_size, drv_get_prot(map_flags), MAP_SHARED, bo->drv->fd,
 463                             gem_map.offset);
 464                 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
 465                 set_domain.write_domain = I915_GEM_DOMAIN_GTT;
 466         }
 467
 468         if (addr == MAP_FAILED) {
 469                 fprintf(stderr, "drv: i915 GEM mmap failed\n");
 470                 return addr;
 471         }
 472
 473         ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_SET_DOMAIN, &set_domain);
 474         if (ret) {
 475                 fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_SET_DOMAIN failed\n");
 476                 return MAP_FAILED;
 477         }
 478
 479         data->length = bo->total_size;
 480         return addr;
 481 }
 482
 483 static int i915_bo_flush(struct bo *bo, struct map_info *data)
 484 {
 485         struct i915_device *i915 = bo->drv->priv;
 486         if (!i915->has_llc && bo->tiling == I915_TILING_NONE)
 487                 i915_clflush(data->addr, data->length);
 488
 489         return 0;
 490 }
 491
 492 static uint32_t i915_resolve_format(uint32_t format, uint64_t use_flags)
 493 {
 494         switch (format) {
 495         case DRM_FORMAT_FLEX_IMPLEMENTATION_DEFINED:
 496                 /* KBL camera subsystem requires NV12. */
 497                 if (use_flags & (BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE))
 498                         return DRM_FORMAT_NV12;
 499                 /*HACK: See b/28671744 */
 500                 return DRM_FORMAT_XBGR8888;
 501         case DRM_FORMAT_FLEX_YCbCr_420_888:
 502                 /* KBL camera subsystem requires NV12. */
 503                 if (use_flags & (BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE))
 504                         return DRM_FORMAT_NV12;
 505                 return DRM_FORMAT_YVU420;
 506         default:
 507                 return format;
 508         }
 509 }
 510
 511 struct backend backend_i915 = {
 512         .name = "i915",
 513         .init = i915_init,
 514         .close = i915_close,
 515         .bo_create = i915_bo_create,
 516         .bo_destroy = drv_gem_bo_destroy,
 517         .bo_import = i915_bo_import,
 518         .bo_map = i915_bo_map,
 519         .bo_unmap = drv_bo_munmap,
 520         .bo_flush = i915_bo_flush,
 521         .resolve_format = i915_resolve_format,
 522 };
 523
 524 #endif