i915.c

   1 /*
   2  * Copyright 2014 The Chromium OS Authors. All rights reserved.
   3  * Use of this source code is governed by a BSD-style license that can be
   4  * found in the LICENSE file.
   5  */
   6
   7 #ifdef DRV_I915
   8
   9 #include <errno.h>
  10 #include <i915_drm.h>
  11 #include <stdio.h>
  12 #include <string.h>
  13 #include <sys/mman.h>
  14 #include <xf86drm.h>
  15
  16 #include "drv_priv.h"
  17 #include "helpers.h"
  18 #include "util.h"
  19 #include "i915_private.h"
  20
  21 #define I915_CACHELINE_SIZE 64
  22 #define I915_CACHELINE_MASK (I915_CACHELINE_SIZE - 1)
  23
  24 static const uint32_t render_target_formats[] = { DRM_FORMAT_ABGR8888,    DRM_FORMAT_ARGB1555,
  25                                                   DRM_FORMAT_ARGB8888,    DRM_FORMAT_RGB565,
  26                                                   DRM_FORMAT_XBGR2101010, DRM_FORMAT_XBGR8888,
  27                                                   DRM_FORMAT_XRGB1555,    DRM_FORMAT_XRGB2101010,
  28                                                   DRM_FORMAT_XRGB8888 };
  29
  30 static const uint32_t tileable_texture_source_formats[] = { DRM_FORMAT_GR88, DRM_FORMAT_R8,
  31                                                             DRM_FORMAT_UYVY, DRM_FORMAT_YUYV,
  32                                                             DRM_FORMAT_YVYU, DRM_FORMAT_VYUY };
  33
  34 static const uint32_t texture_source_formats[] = { DRM_FORMAT_YVU420, DRM_FORMAT_YVU420_ANDROID,
  35                                                    DRM_FORMAT_NV12 };
  36
  37 struct i915_device
  38 {
  39         uint32_t gen;
  40         int32_t has_llc;
  41         uint64_t cursor_width;
  42         uint64_t cursor_height;
  43 };
  44
  45 static uint32_t i915_get_gen(int device_id)
  46 {
  47         const uint16_t gen3_ids[] = { 0x2582, 0x2592, 0x2772, 0x27A2, 0x27AE,
  48                                       0x29C2, 0x29B2, 0x29D2, 0xA001, 0xA011 };
  49         unsigned i;
  50         for (i = 0; i < ARRAY_SIZE(gen3_ids); i++)
  51                 if (gen3_ids[i] == device_id)
  52                         return 3;
  53
  54         return 4;
  55 }
  56
  57 static int i915_add_kms_item(struct driver *drv, const struct kms_item *item)
  58 {
  59         uint32_t i;
  60         struct combination *combo;
  61
  62         /*
  63          * Older hardware can't scanout Y-tiled formats. Newer devices can, and
  64          * report this functionality via format modifiers.
  65          */
  66         for (i = 0; i < drv->combos.size; i++) {
  67                 combo = &drv->combos.data[i];
  68                 if (combo->format != item->format)
  69                         continue;
  70
  71                 if (item->modifier == DRM_FORMAT_MOD_INVALID &&
  72                     combo->metadata.tiling == I915_TILING_X) {
  73                         /*
  74                          * FIXME: drv_query_kms() does not report the available modifiers
  75                          * yet, but we know that all hardware can scanout from X-tiled
  76                          * buffers, so let's add this to our combinations, except for
  77                          * cursor, which must not be tiled.
  78                          */
  79                         combo->use_flags |= item->use_flags & ~BO_USE_CURSOR;
  80                 }
  81
  82                 if (combo->metadata.modifier == item->modifier)
  83                         combo->use_flags |= item->use_flags;
  84         }
  85
  86         return 0;
  87 }
  88
  89 static int i915_add_combinations(struct driver *drv)
  90 {
  91         int ret;
  92         uint32_t i, num_items;
  93         struct kms_item *items;
  94         struct format_metadata metadata;
  95         uint64_t render_use_flags, texture_use_flags;
  96
  97         render_use_flags = BO_USE_RENDER_MASK;
  98         texture_use_flags = BO_USE_TEXTURE_MASK;
  99
 100         metadata.tiling = I915_TILING_NONE;
 101         metadata.priority = 1;
 102         metadata.modifier = DRM_FORMAT_MOD_LINEAR;
 103
 104         ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
 105                                    &metadata, render_use_flags);
 106         if (ret)
 107                 return ret;
 108
 109         ret = drv_add_combinations(drv, texture_source_formats, ARRAY_SIZE(texture_source_formats),
 110                                    &metadata, texture_use_flags);
 111         if (ret)
 112                 return ret;
 113
 114         ret = drv_add_combinations(drv, tileable_texture_source_formats,
 115                                    ARRAY_SIZE(tileable_texture_source_formats), &metadata,
 116                                    texture_use_flags);
 117         if (ret)
 118                 return ret;
 119
 120         drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
 121         drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
 122
 123         /* IPU3 camera ISP supports only NV12 output. */
 124         drv_modify_combination(drv, DRM_FORMAT_NV12, &metadata,
 125                                BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE);
 126         /*
 127          * R8 format is used for Android's HAL_PIXEL_FORMAT_BLOB and is used for JPEG snapshots
 128          * from camera.
 129          */
 130         drv_modify_combination(drv, DRM_FORMAT_R8, &metadata,
 131                                BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE);
 132
 133         render_use_flags &= ~BO_USE_RENDERSCRIPT;
 134         render_use_flags &= ~BO_USE_SW_WRITE_OFTEN;
 135         render_use_flags &= ~BO_USE_SW_READ_OFTEN;
 136         render_use_flags &= ~BO_USE_LINEAR;
 137
 138         texture_use_flags &= ~BO_USE_RENDERSCRIPT;
 139         texture_use_flags &= ~BO_USE_SW_WRITE_OFTEN;
 140         texture_use_flags &= ~BO_USE_SW_READ_OFTEN;
 141         texture_use_flags &= ~BO_USE_LINEAR;
 142
 143         metadata.tiling = I915_TILING_X;
 144         metadata.priority = 2;
 145         metadata.modifier = I915_FORMAT_MOD_X_TILED;
 146
 147         ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
 148                                    &metadata, render_use_flags);
 149         if (ret)
 150                 return ret;
 151
 152         ret = drv_add_combinations(drv, tileable_texture_source_formats,
 153                                    ARRAY_SIZE(tileable_texture_source_formats), &metadata,
 154                                    texture_use_flags);
 155         if (ret)
 156                 return ret;
 157
 158         metadata.tiling = I915_TILING_Y;
 159         metadata.priority = 3;
 160         metadata.modifier = I915_FORMAT_MOD_Y_TILED;
 161
 162         ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
 163                                    &metadata, render_use_flags);
 164         if (ret)
 165                 return ret;
 166
 167         ret = drv_add_combinations(drv, tileable_texture_source_formats,
 168                                    ARRAY_SIZE(tileable_texture_source_formats), &metadata,
 169                                    texture_use_flags);
 170         if (ret)
 171                 return ret;
 172
 173         i915_private_add_combinations(drv);
 174
 175         items = drv_query_kms(drv, &num_items);
 176         if (!items || !num_items)
 177                 return 0;
 178
 179         for (i = 0; i < num_items; i++) {
 180                 ret = i915_add_kms_item(drv, &items[i]);
 181                 if (ret) {
 182                         free(items);
 183                         return ret;
 184                 }
 185         }
 186
 187         free(items);
 188         return 0;
 189 }
 190
 191 static int i915_align_dimensions(struct bo *bo, uint32_t tiling, uint32_t *stride,
 192                                  uint32_t *aligned_height)
 193 {
 194         struct i915_device *i915 = bo->drv->priv;
 195         uint32_t horizontal_alignment = 4;
 196         uint32_t vertical_alignment = 4;
 197
 198         switch (tiling) {
 199         default:
 200         case I915_TILING_NONE:
 201                 horizontal_alignment = 64;
 202                 break;
 203
 204         case I915_TILING_X:
 205                 horizontal_alignment = 512;
 206                 vertical_alignment = 8;
 207                 break;
 208
 209         case I915_TILING_Y:
 210                 if (i915->gen == 3) {
 211                         horizontal_alignment = 512;
 212                         vertical_alignment = 8;
 213                 } else {
 214                        horizontal_alignment = 128;
 215                        vertical_alignment = 32;
 216                 }
 217                 break;
 218         }
 219
 220         /*
 221          * The alignment calculated above is based on the full size luma plane and to have chroma
 222          * planes properly aligned with subsampled formats, we need to multiply luma alignment by
 223          * subsampling factor.
 224          */
 225         switch (bo->format) {
 226         case DRM_FORMAT_YVU420_ANDROID:
 227         case DRM_FORMAT_YVU420:
 228                 horizontal_alignment *= 2;
 229         /* Fall through */
 230         case DRM_FORMAT_NV12:
 231                 vertical_alignment *= 2;
 232                 break;
 233         }
 234
 235         i915_private_align_dimensions(bo->format, &vertical_alignment);
 236
 237         *aligned_height = ALIGN(bo->height, vertical_alignment);
 238         if (i915->gen > 3) {
 239                 *stride = ALIGN(*stride, horizontal_alignment);
 240         } else {
 241                 while (*stride > horizontal_alignment)
 242                         horizontal_alignment <<= 1;
 243
 244                 *stride = horizontal_alignment;
 245         }
 246
 247         if (i915->gen <= 3 && *stride > 8192)
 248                 return -EINVAL;
 249
 250         return 0;
 251 }
 252
 253 static void i915_clflush(void *start, size_t size)
 254 {
 255         void *p = (void *)(((uintptr_t)start) & ~I915_CACHELINE_MASK);
 256         void *end = (void *)((uintptr_t)start + size);
 257
 258         __builtin_ia32_mfence();
 259         while (p < end) {
 260                 __builtin_ia32_clflush(p);
 261                 p = (void *)((uintptr_t)p + I915_CACHELINE_SIZE);
 262         }
 263 }
 264
 265 static int i915_init(struct driver *drv)
 266 {
 267         int ret;
 268         int device_id;
 269         struct i915_device *i915;
 270         drm_i915_getparam_t get_param;
 271
 272         i915 = calloc(1, sizeof(*i915));
 273         if (!i915)
 274                 return -ENOMEM;
 275
 276         memset(&get_param, 0, sizeof(get_param));
 277         get_param.param = I915_PARAM_CHIPSET_ID;
 278         get_param.value = &device_id;
 279         ret = drmIoctl(drv->fd, DRM_IOCTL_I915_GETPARAM, &get_param);
 280         if (ret) {
 281                 fprintf(stderr, "drv: Failed to get I915_PARAM_CHIPSET_ID\n");
 282                 free(i915);
 283                 return -EINVAL;
 284         }
 285
 286         i915->gen = i915_get_gen(device_id);
 287
 288         memset(&get_param, 0, sizeof(get_param));
 289         get_param.param = I915_PARAM_HAS_LLC;
 290         get_param.value = &i915->has_llc;
 291         ret = drmIoctl(drv->fd, DRM_IOCTL_I915_GETPARAM, &get_param);
 292         if (ret) {
 293                 fprintf(stderr, "drv: Failed to get I915_PARAM_HAS_LLC\n");
 294                 free(i915);
 295                 return -EINVAL;
 296         }
 297
 298         drv->priv = i915;
 299
 300         i915_private_init(drv, &i915->cursor_width, &i915->cursor_height);
 301
 302         return i915_add_combinations(drv);
 303 }
 304
 305 static int i915_bo_create_for_modifier(struct bo *bo, uint32_t width, uint32_t height,
 306                                        uint32_t format, uint64_t modifier)
 307 {
 308         int ret;
 309         size_t plane;
 310         uint32_t stride;
 311         struct drm_i915_gem_create gem_create;
 312         struct drm_i915_gem_set_tiling gem_set_tiling;
 313         struct i915_device *i915_dev = (struct i915_device *)bo->drv->priv;
 314
 315         switch (modifier) {
 316         case DRM_FORMAT_MOD_LINEAR:
 317                 bo->tiling = I915_TILING_NONE;
 318                 break;
 319         case I915_FORMAT_MOD_X_TILED:
 320                 bo->tiling = I915_TILING_X;
 321                 break;
 322         case I915_FORMAT_MOD_Y_TILED:
 323         case I915_FORMAT_MOD_Y_TILED_CCS:
 324                 bo->tiling = I915_TILING_Y;
 325                 break;
 326         }
 327
 328         stride = drv_stride_from_format(format, width, 0);
 329
 330         /*
 331          * Align cursor width and height to values expected by Intel
 332          * HW.
 333          */
 334         if (bo->use_flags & BO_USE_CURSOR) {
 335             width = ALIGN(width, i915_dev->cursor_width);
 336             height = ALIGN(height, i915_dev->cursor_height);
 337             stride = drv_stride_from_format(format, width, 0);
 338         } else {
 339             ret = i915_align_dimensions(bo, bo->tiling, &stride, &height);
 340             if (ret)
 341                 return ret;
 342         }
 343
 344         /*
 345          * HAL_PIXEL_FORMAT_YV12 requires the buffer height not be aligned, but we need to keep
 346          * total size as with aligned height to ensure enough padding space after each plane to
 347          * satisfy GPU alignment requirements.
 348          *
 349          * We do it by first calling drv_bo_from_format() with aligned height and
 350          * DRM_FORMAT_YVU420, which allows height alignment, saving the total size it calculates
 351          * and then calling it again with requested parameters.
 352          *
 353          * This relies on the fact that i965 driver uses separate surfaces for each plane and
 354          * contents of padding bytes is not affected, as it is only used to satisfy GPU cache
 355          * requests.
 356          *
 357          * This is enforced by Mesa in src/intel/isl/isl_gen8.c, inside
 358          * isl_gen8_choose_image_alignment_el(), which is used for GEN9 and GEN8.
 359          */
 360         if (format == DRM_FORMAT_YVU420_ANDROID) {
 361                 uint32_t unaligned_height = bo->height;
 362                 size_t total_size;
 363
 364                 drv_bo_from_format(bo, stride, height, DRM_FORMAT_YVU420);
 365                 total_size = bo->total_size;
 366                 drv_bo_from_format(bo, stride, unaligned_height, format);
 367                 bo->total_size = total_size;
 368         } else {
 369                 drv_bo_from_format(bo, stride, height, format);
 370         }
 371
 372         if (modifier == I915_FORMAT_MOD_Y_TILED_CCS) {
 373                 /*
 374                  * For compressed surfaces, we need a color control surface
 375                  * (CCS). Color compression is only supported for Y tiled
 376                  * surfaces, and for each 32x16 tiles in the main surface we
 377                  * need a tile in the control surface.  Y tiles are 128 bytes
 378                  * wide and 32 lines tall and we use that to first compute the
 379                  * width and height in tiles of the main surface. stride and
 380                  * height are already multiples of 128 and 32, respectively:
 381                  */
 382                 uint32_t width_in_tiles = stride / 128;
 383                 uint32_t height_in_tiles = height / 32;
 384
 385                 /*
 386                  * Now, compute the width and height in tiles of the control
 387                  * surface by dividing and rounding up.
 388                  */
 389                 uint32_t ccs_width_in_tiles = DIV_ROUND_UP(width_in_tiles, 32);
 390                 uint32_t ccs_height_in_tiles = DIV_ROUND_UP(height_in_tiles, 16);
 391                 uint32_t ccs_size = ccs_width_in_tiles * ccs_height_in_tiles * 4096;
 392
 393                 /*
 394                  * With stride and height aligned to y tiles, bo->total_size
 395                  * is already a multiple of 4096, which is the required
 396                  * alignment of the CCS.
 397                  */
 398                 bo->num_planes = 2;
 399                 bo->strides[1] = ccs_width_in_tiles * 128;
 400                 bo->sizes[1] = ccs_size;
 401                 bo->offsets[1] = bo->total_size;
 402                 bo->total_size += ccs_size;
 403         }
 404
 405         /*
 406          * Quoting Mesa ISL library:
 407          *
 408          *    - For linear surfaces, additional padding of 64 bytes is required at
 409          *      the bottom of the surface. This is in addition to the padding
 410          *      required above.
 411          */
 412         if (bo->tiling == I915_TILING_NONE)
 413                 bo->total_size += 64;
 414
 415         /*
 416          * Ensure we pass aligned width/height.
 417          */
 418         bo->width = width;
 419         bo->height = height;
 420
 421         memset(&gem_create, 0, sizeof(gem_create));
 422         gem_create.size = bo->total_size;
 423
 424         ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_CREATE, &gem_create);
 425         if (ret) {
 426                 fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_CREATE failed (size=%llu)\n",
 427                         gem_create.size);
 428                 return ret;
 429         }
 430
 431         for (plane = 0; plane < bo->num_planes; plane++)
 432                 bo->handles[plane].u32 = gem_create.handle;
 433
 434         memset(&gem_set_tiling, 0, sizeof(gem_set_tiling));
 435         gem_set_tiling.handle = bo->handles[0].u32;
 436         gem_set_tiling.tiling_mode = bo->tiling;
 437         gem_set_tiling.stride = bo->strides[0];
 438
 439         ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_SET_TILING, &gem_set_tiling);
 440         if (ret) {
 441                 struct drm_gem_close gem_close;
 442                 memset(&gem_close, 0, sizeof(gem_close));
 443                 gem_close.handle = bo->handles[0].u32;
 444                 drmIoctl(bo->drv->fd, DRM_IOCTL_GEM_CLOSE, &gem_close);
 445
 446                 fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_SET_TILING failed with %d", errno);
 447                 return -errno;
 448         }
 449
 450         return 0;
 451 }
 452
 453 static int i915_bo_create(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
 454                           uint64_t use_flags)
 455 {
 456         struct combination *combo;
 457
 458         combo = drv_get_combination(bo->drv, format, use_flags);
 459         if (!combo)
 460                 return -EINVAL;
 461
 462         return i915_bo_create_for_modifier(bo, width, height, format, combo->metadata.modifier);
 463 }
 464
 465 static int i915_bo_create_with_modifiers(struct bo *bo, uint32_t width, uint32_t height,
 466                                          uint32_t format, const uint64_t *modifiers, uint32_t count)
 467 {
 468         static const uint64_t modifier_order[] = {
 469                 I915_FORMAT_MOD_Y_TILED, I915_FORMAT_MOD_Y_TILED_CCS, I915_FORMAT_MOD_X_TILED, DRM_FORMAT_MOD_LINEAR,
 470         };
 471         uint64_t modifier;
 472
 473         modifier = drv_pick_modifier(modifiers, count, modifier_order, ARRAY_SIZE(modifier_order));
 474
 475         bo->format_modifiers[0] = modifier;
 476
 477         return i915_bo_create_for_modifier(bo, width, height, format, modifier);
 478 }
 479
 480 static void i915_close(struct driver *drv)
 481 {
 482         free(drv->priv);
 483         drv->priv = NULL;
 484 }
 485
 486 static int i915_bo_import(struct bo *bo, struct drv_import_fd_data *data)
 487 {
 488         int ret;
 489         struct drm_i915_gem_get_tiling gem_get_tiling;
 490
 491         ret = drv_prime_bo_import(bo, data);
 492         if (ret)
 493                 return ret;
 494
 495         /* TODO(gsingh): export modifiers and get rid of backdoor tiling. */
 496         memset(&gem_get_tiling, 0, sizeof(gem_get_tiling));
 497         gem_get_tiling.handle = bo->handles[0].u32;
 498
 499         ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_GET_TILING, &gem_get_tiling);
 500         if (ret) {
 501                 drv_gem_bo_destroy(bo);
 502                 fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_GET_TILING failed.");
 503                 return ret;
 504         }
 505
 506         bo->tiling = gem_get_tiling.tiling_mode;
 507         return 0;
 508 }
 509
 510 static void *i915_bo_map(struct bo *bo, struct map_info *data, size_t plane, uint32_t map_flags)
 511 {
 512         int ret;
 513         void *addr;
 514
 515         if (bo->tiling == I915_TILING_NONE) {
 516                 struct drm_i915_gem_mmap gem_map;
 517                 memset(&gem_map, 0, sizeof(gem_map));
 518
 519                 if ((bo->use_flags & BO_USE_SCANOUT) && !(bo->use_flags & BO_USE_RENDERSCRIPT))
 520                         gem_map.flags = I915_MMAP_WC;
 521
 522                 gem_map.handle = bo->handles[0].u32;
 523                 gem_map.offset = 0;
 524                 gem_map.size = bo->total_size;
 525
 526                 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_MMAP, &gem_map);
 527                 if (ret) {
 528                         fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_MMAP failed\n");
 529                         return MAP_FAILED;
 530                 }
 531
 532                 addr = (void *)(uintptr_t)gem_map.addr_ptr;
 533         } else {
 534                 struct drm_i915_gem_mmap_gtt gem_map;
 535                 memset(&gem_map, 0, sizeof(gem_map));
 536
 537                 gem_map.handle = bo->handles[0].u32;
 538
 539                 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_MMAP_GTT, &gem_map);
 540                 if (ret) {
 541                         fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_MMAP_GTT failed\n");
 542                         return MAP_FAILED;
 543                 }
 544
 545                 addr = mmap(0, bo->total_size, drv_get_prot(map_flags), MAP_SHARED, bo->drv->fd,
 546                             gem_map.offset);
 547         }
 548
 549         if (addr == MAP_FAILED) {
 550                 fprintf(stderr, "drv: i915 GEM mmap failed\n");
 551                 return addr;
 552         }
 553
 554         data->length = bo->total_size;
 555         return addr;
 556 }
 557
 558 static int i915_bo_invalidate(struct bo *bo, struct map_info *data)
 559 {
 560         int ret;
 561         struct drm_i915_gem_set_domain set_domain;
 562
 563         memset(&set_domain, 0, sizeof(set_domain));
 564         set_domain.handle = bo->handles[0].u32;
 565         if (bo->tiling == I915_TILING_NONE) {
 566                 set_domain.read_domains = I915_GEM_DOMAIN_CPU;
 567                 if (data->map_flags & BO_MAP_WRITE)
 568                         set_domain.write_domain = I915_GEM_DOMAIN_CPU;
 569         } else {
 570                 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
 571                 if (data->map_flags & BO_MAP_WRITE)
 572                         set_domain.write_domain = I915_GEM_DOMAIN_GTT;
 573         }
 574
 575         ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_SET_DOMAIN, &set_domain);
 576         if (ret) {
 577                 fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_SET_DOMAIN with %d\n", ret);
 578                 return ret;
 579         }
 580
 581         return 0;
 582 }
 583
 584 static int i915_bo_flush(struct bo *bo, struct map_info *data)
 585 {
 586         struct i915_device *i915 = bo->drv->priv;
 587         if (!i915->has_llc && bo->tiling == I915_TILING_NONE)
 588                 i915_clflush(data->addr, data->length);
 589
 590         return 0;
 591 }
 592
 593 static uint32_t i915_resolve_format(uint32_t format, uint64_t use_flags)
 594 {
 595         uint32_t resolved_format;
 596         if (i915_private_resolve_format(format, use_flags, &resolved_format)) {
 597             return resolved_format;
 598         }
 599
 600         switch (format) {
 601         case DRM_FORMAT_FLEX_IMPLEMENTATION_DEFINED:
 602                 /* KBL camera subsystem requires NV12. */
 603                 if (use_flags & (BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE))
 604                         return DRM_FORMAT_NV12;
 605                 /*HACK: See b/28671744 */
 606                 return DRM_FORMAT_XBGR8888;
 607         case DRM_FORMAT_FLEX_YCbCr_420_888:
 608                 /*
 609                  * KBL camera subsystem requires NV12. Our other use cases
 610                  * don't care:
 611                  * - Hardware video supports NV12,
 612                  * - USB Camera HALv3 supports NV12,
 613                  * - USB Camera HALv1 doesn't use this format.
 614                  * Moreover, NV12 is preferred for video, due to overlay
 615                  * support on SKL+.
 616                  */
 617                 return DRM_FORMAT_NV12;
 618         default:
 619                 return format;
 620         }
 621 }
 622
 623 struct backend backend_i915 = {
 624         .name = "i915",
 625         .init = i915_init,
 626         .close = i915_close,
 627         .bo_create = i915_bo_create,
 628         .bo_create_with_modifiers = i915_bo_create_with_modifiers,
 629         .bo_destroy = drv_gem_bo_destroy,
 630         .bo_import = i915_bo_import,
 631         .bo_map = i915_bo_map,
 632         .bo_unmap = drv_bo_munmap,
 633         .bo_invalidate = i915_bo_invalidate,
 634         .bo_flush = i915_bo_flush,
 635         .resolve_format = i915_resolve_format,
 636 };
 637
 638 #endif