i915.c

   1 /*
   2  * Copyright 2014 The Chromium OS Authors. All rights reserved.
   3  * Use of this source code is governed by a BSD-style license that can be
   4  * found in the LICENSE file.
   5  */
   6
   7 #ifdef DRV_I915
   8
   9 #include <assert.h>
  10 #include <errno.h>
  11 #include <i915_drm.h>
  12 #include <stdbool.h>
  13 #include <stdio.h>
  14 #include <string.h>
  15 #include <sys/mman.h>
  16 #include <unistd.h>
  17 #include <xf86drm.h>
  18
  19 #include "drv_priv.h"
  20 #include "helpers.h"
  21 #include "util.h"
  22
  23 #define I915_CACHELINE_SIZE 64
  24 #define I915_CACHELINE_MASK (I915_CACHELINE_SIZE - 1)
  25
  26 static const uint32_t scanout_render_formats[] = { DRM_FORMAT_ABGR2101010, DRM_FORMAT_ABGR8888,
  27                                                    DRM_FORMAT_ARGB2101010, DRM_FORMAT_ARGB8888,
  28                                                    DRM_FORMAT_RGB565,      DRM_FORMAT_XBGR2101010,
  29                                                    DRM_FORMAT_XBGR8888,    DRM_FORMAT_XRGB2101010,
  30                                                    DRM_FORMAT_XRGB8888 };
  31
  32 static const uint32_t render_formats[] = { DRM_FORMAT_ABGR16161616F };
  33
  34 static const uint32_t texture_only_formats[] = { DRM_FORMAT_R8, DRM_FORMAT_NV12, DRM_FORMAT_P010,
  35                                                  DRM_FORMAT_YVU420, DRM_FORMAT_YVU420_ANDROID };
  36
  37 static const uint64_t gen_modifier_order[] = { I915_FORMAT_MOD_Y_TILED, I915_FORMAT_MOD_X_TILED,
  38                                                DRM_FORMAT_MOD_LINEAR };
  39
  40 static const uint64_t gen11_modifier_order[] = { I915_FORMAT_MOD_Y_TILED_CCS,
  41                                                  I915_FORMAT_MOD_Y_TILED, I915_FORMAT_MOD_X_TILED,
  42                                                  DRM_FORMAT_MOD_LINEAR };
  43
  44 struct modifier_support_t {
  45         const uint64_t *order;
  46         uint32_t count;
  47 };
  48
  49 struct i915_device {
  50         uint32_t gen;
  51         int32_t has_llc;
  52         struct modifier_support_t modifier;
  53 };
  54
  55 static uint32_t i915_get_gen(int device_id)
  56 {
  57         const uint16_t gen3_ids[] = { 0x2582, 0x2592, 0x2772, 0x27A2, 0x27AE,
  58                                       0x29C2, 0x29B2, 0x29D2, 0xA001, 0xA011 };
  59         const uint16_t gen11_ids[] = { 0x4E71, 0x4E61, 0x4E51, 0x4E55, 0x4E57 };
  60         const uint16_t gen12_ids[] = { 0x9A40, 0x9A49, 0x9A59, 0x9A60, 0x9A68, 0x9A70,
  61                                        0x9A78, 0x9AC0, 0x9AC9, 0x9AD9, 0x9AF8 };
  62         unsigned i;
  63         for (i = 0; i < ARRAY_SIZE(gen3_ids); i++)
  64                 if (gen3_ids[i] == device_id)
  65                         return 3;
  66         /* Gen 11 */
  67         for (i = 0; i < ARRAY_SIZE(gen11_ids); i++)
  68                 if (gen11_ids[i] == device_id)
  69                         return 11;
  70
  71         /* Gen 12 */
  72         for (i = 0; i < ARRAY_SIZE(gen12_ids); i++)
  73                 if (gen12_ids[i] == device_id)
  74                         return 12;
  75
  76         return 4;
  77 }
  78
  79 static void i915_get_modifier_order(struct i915_device *i915)
  80 {
  81         if (i915->gen == 11) {
  82                 i915->modifier.order = gen11_modifier_order;
  83                 i915->modifier.count = ARRAY_SIZE(gen11_modifier_order);
  84         } else {
  85                 i915->modifier.order = gen_modifier_order;
  86                 i915->modifier.count = ARRAY_SIZE(gen_modifier_order);
  87         }
  88 }
  89
  90 static uint64_t unset_flags(uint64_t current_flags, uint64_t mask)
  91 {
  92         uint64_t value = current_flags & ~mask;
  93         return value;
  94 }
  95
  96 static int i915_add_combinations(struct driver *drv)
  97 {
  98         struct format_metadata metadata;
  99         uint64_t render, scanout_and_render, texture_only;
 100
 101         scanout_and_render = BO_USE_RENDER_MASK | BO_USE_SCANOUT;
 102         render = BO_USE_RENDER_MASK;
 103         texture_only = BO_USE_TEXTURE_MASK;
 104         uint64_t linear_mask =
 105             BO_USE_RENDERSCRIPT | BO_USE_LINEAR | BO_USE_SW_READ_OFTEN | BO_USE_SW_WRITE_OFTEN;
 106
 107         metadata.tiling = I915_TILING_NONE;
 108         metadata.priority = 1;
 109         metadata.modifier = DRM_FORMAT_MOD_LINEAR;
 110
 111         drv_add_combinations(drv, scanout_render_formats, ARRAY_SIZE(scanout_render_formats),
 112                              &metadata, scanout_and_render);
 113
 114         drv_add_combinations(drv, render_formats, ARRAY_SIZE(render_formats), &metadata, render);
 115
 116         drv_add_combinations(drv, texture_only_formats, ARRAY_SIZE(texture_only_formats), &metadata,
 117                              texture_only);
 118
 119         drv_modify_linear_combinations(drv);
 120
 121         /* NV12 format for camera, display, decoding and encoding. */
 122         /* IPU3 camera ISP supports only NV12 output. */
 123         drv_modify_combination(drv, DRM_FORMAT_NV12, &metadata,
 124                                BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE | BO_USE_SCANOUT |
 125                                    BO_USE_HW_VIDEO_DECODER | BO_USE_HW_VIDEO_ENCODER);
 126
 127         /* Android CTS tests require this. */
 128         drv_add_combination(drv, DRM_FORMAT_BGR888, &metadata, BO_USE_SW_MASK);
 129
 130         /*
 131          * R8 format is used for Android's HAL_PIXEL_FORMAT_BLOB and is used for JPEG snapshots
 132          * from camera and input/output from hardware decoder/encoder.
 133          */
 134         drv_modify_combination(drv, DRM_FORMAT_R8, &metadata,
 135                                BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE | BO_USE_HW_VIDEO_DECODER |
 136                                    BO_USE_HW_VIDEO_ENCODER);
 137
 138         render = unset_flags(render, linear_mask);
 139         scanout_and_render = unset_flags(scanout_and_render, linear_mask);
 140
 141         metadata.tiling = I915_TILING_X;
 142         metadata.priority = 2;
 143         metadata.modifier = I915_FORMAT_MOD_X_TILED;
 144
 145         drv_add_combinations(drv, render_formats, ARRAY_SIZE(render_formats), &metadata, render);
 146         drv_add_combinations(drv, scanout_render_formats, ARRAY_SIZE(scanout_render_formats),
 147                              &metadata, scanout_and_render);
 148
 149         metadata.tiling = I915_TILING_Y;
 150         metadata.priority = 3;
 151         metadata.modifier = I915_FORMAT_MOD_Y_TILED;
 152
 153         scanout_and_render =
 154             unset_flags(scanout_and_render, BO_USE_SW_READ_RARELY | BO_USE_SW_WRITE_RARELY);
 155 /* Support y-tiled NV12 and P010 for libva */
 156 #ifdef I915_SCANOUT_Y_TILED
 157         drv_add_combination(drv, DRM_FORMAT_NV12, &metadata,
 158                             BO_USE_TEXTURE | BO_USE_HW_VIDEO_DECODER | BO_USE_SCANOUT);
 159 #else
 160         drv_add_combination(drv, DRM_FORMAT_NV12, &metadata,
 161                             BO_USE_TEXTURE | BO_USE_HW_VIDEO_DECODER);
 162 #endif
 163         scanout_and_render = unset_flags(scanout_and_render, BO_USE_SCANOUT);
 164         drv_add_combination(drv, DRM_FORMAT_P010, &metadata,
 165                             BO_USE_TEXTURE | BO_USE_HW_VIDEO_DECODER);
 166
 167         drv_add_combinations(drv, render_formats, ARRAY_SIZE(render_formats), &metadata, render);
 168         drv_add_combinations(drv, scanout_render_formats, ARRAY_SIZE(scanout_render_formats),
 169                              &metadata, scanout_and_render);
 170         return 0;
 171 }
 172
 173 static int i915_align_dimensions(struct bo *bo, uint32_t tiling, uint32_t *stride,
 174                                  uint32_t *aligned_height)
 175 {
 176         struct i915_device *i915 = bo->drv->priv;
 177         uint32_t horizontal_alignment;
 178         uint32_t vertical_alignment;
 179
 180         switch (tiling) {
 181         default:
 182         case I915_TILING_NONE:
 183                 /*
 184                  * The Intel GPU doesn't need any alignment in linear mode,
 185                  * but libva requires the allocation stride to be aligned to
 186                  * 16 bytes and height to 4 rows. Further, we round up the
 187                  * horizontal alignment so that row start on a cache line (64
 188                  * bytes).
 189                  */
 190                 horizontal_alignment = 64;
 191                 vertical_alignment = 4;
 192                 break;
 193
 194         case I915_TILING_X:
 195                 horizontal_alignment = 512;
 196                 vertical_alignment = 8;
 197                 break;
 198
 199         case I915_TILING_Y:
 200                 if (i915->gen == 3) {
 201                         horizontal_alignment = 512;
 202                         vertical_alignment = 8;
 203                 } else {
 204                         horizontal_alignment = 128;
 205                         vertical_alignment = 32;
 206                 }
 207                 break;
 208         }
 209
 210         *aligned_height = ALIGN(*aligned_height, vertical_alignment);
 211         if (i915->gen > 3) {
 212                 *stride = ALIGN(*stride, horizontal_alignment);
 213         } else {
 214                 while (*stride > horizontal_alignment)
 215                         horizontal_alignment <<= 1;
 216
 217                 *stride = horizontal_alignment;
 218         }
 219
 220         if (i915->gen <= 3 && *stride > 8192)
 221                 return -EINVAL;
 222
 223         return 0;
 224 }
 225
 226 static void i915_clflush(void *start, size_t size)
 227 {
 228         void *p = (void *)(((uintptr_t)start) & ~I915_CACHELINE_MASK);
 229         void *end = (void *)((uintptr_t)start + size);
 230
 231         __builtin_ia32_mfence();
 232         while (p < end) {
 233                 __builtin_ia32_clflush(p);
 234                 p = (void *)((uintptr_t)p + I915_CACHELINE_SIZE);
 235         }
 236 }
 237
 238 static int i915_init(struct driver *drv)
 239 {
 240         int ret;
 241         int device_id;
 242         struct i915_device *i915;
 243         drm_i915_getparam_t get_param = { 0 };
 244
 245         i915 = calloc(1, sizeof(*i915));
 246         if (!i915)
 247                 return -ENOMEM;
 248
 249         get_param.param = I915_PARAM_CHIPSET_ID;
 250         get_param.value = &device_id;
 251         ret = drmIoctl(drv->fd, DRM_IOCTL_I915_GETPARAM, &get_param);
 252         if (ret) {
 253                 drv_log("Failed to get I915_PARAM_CHIPSET_ID\n");
 254                 free(i915);
 255                 return -EINVAL;
 256         }
 257
 258         i915->gen = i915_get_gen(device_id);
 259         i915_get_modifier_order(i915);
 260
 261         memset(&get_param, 0, sizeof(get_param));
 262         get_param.param = I915_PARAM_HAS_LLC;
 263         get_param.value = &i915->has_llc;
 264         ret = drmIoctl(drv->fd, DRM_IOCTL_I915_GETPARAM, &get_param);
 265         if (ret) {
 266                 drv_log("Failed to get I915_PARAM_HAS_LLC\n");
 267                 free(i915);
 268                 return -EINVAL;
 269         }
 270
 271         drv->priv = i915;
 272
 273         return i915_add_combinations(drv);
 274 }
 275
 276 static int i915_bo_from_format(struct bo *bo, uint32_t width, uint32_t height, uint32_t format)
 277 {
 278         uint32_t offset;
 279         size_t plane;
 280         int ret, pagesize;
 281
 282         offset = 0;
 283         pagesize = getpagesize();
 284         for (plane = 0; plane < drv_num_planes_from_format(format); plane++) {
 285                 uint32_t stride = drv_stride_from_format(format, width, plane);
 286                 uint32_t plane_height = drv_height_from_format(format, height, plane);
 287
 288                 if (bo->meta.tiling != I915_TILING_NONE)
 289                         assert(IS_ALIGNED(offset, pagesize));
 290
 291                 ret = i915_align_dimensions(bo, bo->meta.tiling, &stride, &plane_height);
 292                 if (ret)
 293                         return ret;
 294
 295                 bo->meta.strides[plane] = stride;
 296                 bo->meta.sizes[plane] = stride * plane_height;
 297                 bo->meta.offsets[plane] = offset;
 298                 offset += bo->meta.sizes[plane];
 299         }
 300
 301         bo->meta.total_size = ALIGN(offset, pagesize);
 302
 303         return 0;
 304 }
 305
 306 static int i915_bo_compute_metadata(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
 307                                     uint64_t use_flags, const uint64_t *modifiers, uint32_t count)
 308 {
 309         uint64_t modifier;
 310         struct i915_device *i915 = bo->drv->priv;
 311         bool huge_bo = (i915->gen < 11) && (width > 4096);
 312
 313         if (modifiers) {
 314                 modifier =
 315                     drv_pick_modifier(modifiers, count, i915->modifier.order, i915->modifier.count);
 316         } else {
 317                 struct combination *combo = drv_get_combination(bo->drv, format, use_flags);
 318                 if (!combo)
 319                         return -EINVAL;
 320                 modifier = combo->metadata.modifier;
 321         }
 322
 323         /*
 324          * i915 only supports linear/x-tiled above 4096 wide on Gen9/Gen10 GPU.
 325          * VAAPI decode in NV12 Y tiled format so skip modifier change for NV12/P010 huge bo.
 326          */
 327         if (huge_bo && format != DRM_FORMAT_NV12 && format != DRM_FORMAT_P010 &&
 328             modifier != I915_FORMAT_MOD_X_TILED && modifier != DRM_FORMAT_MOD_LINEAR) {
 329                 uint32_t i;
 330                 for (i = 0; modifiers && i < count; i++) {
 331                         if (modifiers[i] == I915_FORMAT_MOD_X_TILED)
 332                                 break;
 333                 }
 334                 if (i == count)
 335                         modifier = DRM_FORMAT_MOD_LINEAR;
 336                 else
 337                         modifier = I915_FORMAT_MOD_X_TILED;
 338         }
 339
 340         switch (modifier) {
 341         case DRM_FORMAT_MOD_LINEAR:
 342                 bo->meta.tiling = I915_TILING_NONE;
 343                 break;
 344         case I915_FORMAT_MOD_X_TILED:
 345                 bo->meta.tiling = I915_TILING_X;
 346                 break;
 347         case I915_FORMAT_MOD_Y_TILED:
 348         case I915_FORMAT_MOD_Y_TILED_CCS:
 349                 bo->meta.tiling = I915_TILING_Y;
 350                 break;
 351         }
 352
 353         bo->meta.format_modifiers[0] = modifier;
 354
 355         if (format == DRM_FORMAT_YVU420_ANDROID) {
 356                 /*
 357                  * We only need to be able to use this as a linear texture,
 358                  * which doesn't put any HW restrictions on how we lay it
 359                  * out. The Android format does require the stride to be a
 360                  * multiple of 16 and expects the Cr and Cb stride to be
 361                  * ALIGN(Y_stride / 2, 16), which we can make happen by
 362                  * aligning to 32 bytes here.
 363                  */
 364                 uint32_t stride = ALIGN(width, 32);
 365                 drv_bo_from_format(bo, stride, height, format);
 366         } else if (modifier == I915_FORMAT_MOD_Y_TILED_CCS) {
 367                 /*
 368                  * For compressed surfaces, we need a color control surface
 369                  * (CCS). Color compression is only supported for Y tiled
 370                  * surfaces, and for each 32x16 tiles in the main surface we
 371                  * need a tile in the control surface.  Y tiles are 128 bytes
 372                  * wide and 32 lines tall and we use that to first compute the
 373                  * width and height in tiles of the main surface. stride and
 374                  * height are already multiples of 128 and 32, respectively:
 375                  */
 376                 uint32_t stride = drv_stride_from_format(format, width, 0);
 377                 uint32_t width_in_tiles = DIV_ROUND_UP(stride, 128);
 378                 uint32_t height_in_tiles = DIV_ROUND_UP(height, 32);
 379                 uint32_t size = width_in_tiles * height_in_tiles * 4096;
 380                 uint32_t offset = 0;
 381
 382                 bo->meta.strides[0] = width_in_tiles * 128;
 383                 bo->meta.sizes[0] = size;
 384                 bo->meta.offsets[0] = offset;
 385                 offset += size;
 386
 387                 /*
 388                  * Now, compute the width and height in tiles of the control
 389                  * surface by dividing and rounding up.
 390                  */
 391                 uint32_t ccs_width_in_tiles = DIV_ROUND_UP(width_in_tiles, 32);
 392                 uint32_t ccs_height_in_tiles = DIV_ROUND_UP(height_in_tiles, 16);
 393                 uint32_t ccs_size = ccs_width_in_tiles * ccs_height_in_tiles * 4096;
 394
 395                 /*
 396                  * With stride and height aligned to y tiles, offset is
 397                  * already a multiple of 4096, which is the required alignment
 398                  * of the CCS.
 399                  */
 400                 bo->meta.strides[1] = ccs_width_in_tiles * 128;
 401                 bo->meta.sizes[1] = ccs_size;
 402                 bo->meta.offsets[1] = offset;
 403                 offset += ccs_size;
 404
 405                 bo->meta.num_planes = 2;
 406                 bo->meta.total_size = offset;
 407         } else {
 408                 i915_bo_from_format(bo, width, height, format);
 409         }
 410         return 0;
 411 }
 412
 413 static int i915_bo_create_from_metadata(struct bo *bo)
 414 {
 415         int ret;
 416         size_t plane;
 417         struct drm_i915_gem_create gem_create = { 0 };
 418         struct drm_i915_gem_set_tiling gem_set_tiling = { 0 };
 419
 420         gem_create.size = bo->meta.total_size;
 421         ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_CREATE, &gem_create);
 422         if (ret) {
 423                 drv_log("DRM_IOCTL_I915_GEM_CREATE failed (size=%llu)\n", gem_create.size);
 424                 return -errno;
 425         }
 426
 427         for (plane = 0; plane < bo->meta.num_planes; plane++)
 428                 bo->handles[plane].u32 = gem_create.handle;
 429
 430         gem_set_tiling.handle = bo->handles[0].u32;
 431         gem_set_tiling.tiling_mode = bo->meta.tiling;
 432         gem_set_tiling.stride = bo->meta.strides[0];
 433
 434         ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_SET_TILING, &gem_set_tiling);
 435         if (ret) {
 436                 struct drm_gem_close gem_close = { 0 };
 437                 gem_close.handle = bo->handles[0].u32;
 438                 drmIoctl(bo->drv->fd, DRM_IOCTL_GEM_CLOSE, &gem_close);
 439
 440                 drv_log("DRM_IOCTL_I915_GEM_SET_TILING failed with %d\n", errno);
 441                 return -errno;
 442         }
 443
 444         return 0;
 445 }
 446
 447 static void i915_close(struct driver *drv)
 448 {
 449         free(drv->priv);
 450         drv->priv = NULL;
 451 }
 452
 453 static int i915_bo_import(struct bo *bo, struct drv_import_fd_data *data)
 454 {
 455         int ret;
 456         struct drm_i915_gem_get_tiling gem_get_tiling = { 0 };
 457
 458         ret = drv_prime_bo_import(bo, data);
 459         if (ret)
 460                 return ret;
 461
 462         /* TODO(gsingh): export modifiers and get rid of backdoor tiling. */
 463         gem_get_tiling.handle = bo->handles[0].u32;
 464
 465         ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_GET_TILING, &gem_get_tiling);
 466         if (ret) {
 467                 drv_gem_bo_destroy(bo);
 468                 drv_log("DRM_IOCTL_I915_GEM_GET_TILING failed.\n");
 469                 return ret;
 470         }
 471
 472         bo->meta.tiling = gem_get_tiling.tiling_mode;
 473         return 0;
 474 }
 475
 476 static void *i915_bo_map(struct bo *bo, struct vma *vma, size_t plane, uint32_t map_flags)
 477 {
 478         int ret;
 479         void *addr;
 480
 481         if (bo->meta.format_modifiers[0] == I915_FORMAT_MOD_Y_TILED_CCS)
 482                 return MAP_FAILED;
 483
 484         if (bo->meta.tiling == I915_TILING_NONE) {
 485                 struct drm_i915_gem_mmap gem_map = { 0 };
 486                 /* TODO(b/118799155): We don't seem to have a good way to
 487                  * detect the use cases for which WC mapping is really needed.
 488                  * The current heuristic seems overly coarse and may be slowing
 489                  * down some other use cases unnecessarily.
 490                  *
 491                  * For now, care must be taken not to use WC mappings for
 492                  * Renderscript and camera use cases, as they're
 493                  * performance-sensitive. */
 494                 if ((bo->meta.use_flags & BO_USE_SCANOUT) &&
 495                     !(bo->meta.use_flags &
 496                       (BO_USE_RENDERSCRIPT | BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE)))
 497                         gem_map.flags = I915_MMAP_WC;
 498
 499                 gem_map.handle = bo->handles[0].u32;
 500                 gem_map.offset = 0;
 501                 gem_map.size = bo->meta.total_size;
 502
 503                 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_MMAP, &gem_map);
 504                 if (ret) {
 505                         drv_log("DRM_IOCTL_I915_GEM_MMAP failed\n");
 506                         return MAP_FAILED;
 507                 }
 508
 509                 addr = (void *)(uintptr_t)gem_map.addr_ptr;
 510         } else {
 511                 struct drm_i915_gem_mmap_gtt gem_map = { 0 };
 512
 513                 gem_map.handle = bo->handles[0].u32;
 514                 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_MMAP_GTT, &gem_map);
 515                 if (ret) {
 516                         drv_log("DRM_IOCTL_I915_GEM_MMAP_GTT failed\n");
 517                         return MAP_FAILED;
 518                 }
 519
 520                 addr = mmap(0, bo->meta.total_size, drv_get_prot(map_flags), MAP_SHARED,
 521                             bo->drv->fd, gem_map.offset);
 522         }
 523
 524         if (addr == MAP_FAILED) {
 525                 drv_log("i915 GEM mmap failed\n");
 526                 return addr;
 527         }
 528
 529         vma->length = bo->meta.total_size;
 530         return addr;
 531 }
 532
 533 static int i915_bo_invalidate(struct bo *bo, struct mapping *mapping)
 534 {
 535         int ret;
 536         struct drm_i915_gem_set_domain set_domain = { 0 };
 537
 538         set_domain.handle = bo->handles[0].u32;
 539         if (bo->meta.tiling == I915_TILING_NONE) {
 540                 set_domain.read_domains = I915_GEM_DOMAIN_CPU;
 541                 if (mapping->vma->map_flags & BO_MAP_WRITE)
 542                         set_domain.write_domain = I915_GEM_DOMAIN_CPU;
 543         } else {
 544                 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
 545                 if (mapping->vma->map_flags & BO_MAP_WRITE)
 546                         set_domain.write_domain = I915_GEM_DOMAIN_GTT;
 547         }
 548
 549         ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_SET_DOMAIN, &set_domain);
 550         if (ret) {
 551                 drv_log("DRM_IOCTL_I915_GEM_SET_DOMAIN with %d\n", ret);
 552                 return ret;
 553         }
 554
 555         return 0;
 556 }
 557
 558 static int i915_bo_flush(struct bo *bo, struct mapping *mapping)
 559 {
 560         struct i915_device *i915 = bo->drv->priv;
 561         if (!i915->has_llc && bo->meta.tiling == I915_TILING_NONE)
 562                 i915_clflush(mapping->vma->addr, mapping->vma->length);
 563
 564         return 0;
 565 }
 566
 567 static uint32_t i915_resolve_format(struct driver *drv, uint32_t format, uint64_t use_flags)
 568 {
 569         switch (format) {
 570         case DRM_FORMAT_FLEX_IMPLEMENTATION_DEFINED:
 571                 /* KBL camera subsystem requires NV12. */
 572                 if (use_flags & (BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE))
 573                         return DRM_FORMAT_NV12;
 574                 /*HACK: See b/28671744 */
 575                 return DRM_FORMAT_XBGR8888;
 576         case DRM_FORMAT_FLEX_YCbCr_420_888:
 577                 /*
 578                  * KBL camera subsystem requires NV12. Our other use cases
 579                  * don't care:
 580                  * - Hardware video supports NV12,
 581                  * - USB Camera HALv3 supports NV12,
 582                  * - USB Camera HALv1 doesn't use this format.
 583                  * Moreover, NV12 is preferred for video, due to overlay
 584                  * support on SKL+.
 585                  */
 586                 return DRM_FORMAT_NV12;
 587         default:
 588                 return format;
 589         }
 590 }
 591
 592 const struct backend backend_i915 = {
 593         .name = "i915",
 594         .init = i915_init,
 595         .close = i915_close,
 596         .bo_compute_metadata = i915_bo_compute_metadata,
 597         .bo_create_from_metadata = i915_bo_create_from_metadata,
 598         .bo_destroy = drv_gem_bo_destroy,
 599         .bo_import = i915_bo_import,
 600         .bo_map = i915_bo_map,
 601         .bo_unmap = drv_bo_munmap,
 602         .bo_invalidate = i915_bo_invalidate,
 603         .bo_flush = i915_bo_flush,
 604         .resolve_format = i915_resolve_format,
 605 };
 606
 607 #endif