2 * Copyright 2014 The Chromium OS Authors. All rights reserved.
3 * Use of this source code is governed by a BSD-style license that can be
4 * found in the LICENSE file.
23 #define I915_CACHELINE_SIZE 64
24 #define I915_CACHELINE_MASK (I915_CACHELINE_SIZE - 1)
26 static const uint32_t scanout_render_formats[] = { DRM_FORMAT_ABGR2101010, DRM_FORMAT_ABGR8888,
27 DRM_FORMAT_ARGB2101010, DRM_FORMAT_ARGB8888,
28 DRM_FORMAT_RGB565, DRM_FORMAT_XBGR2101010,
29 DRM_FORMAT_XBGR8888, DRM_FORMAT_XRGB2101010,
30 DRM_FORMAT_XRGB8888 };
32 static const uint32_t render_formats[] = { DRM_FORMAT_ABGR16161616F };
34 static const uint32_t texture_only_formats[] = { DRM_FORMAT_R8, DRM_FORMAT_NV12, DRM_FORMAT_P010,
35 DRM_FORMAT_YVU420, DRM_FORMAT_YVU420_ANDROID };
37 static const uint64_t gen_modifier_order[] = { I915_FORMAT_MOD_Y_TILED, I915_FORMAT_MOD_X_TILED,
38 DRM_FORMAT_MOD_LINEAR };
40 static const uint64_t gen11_modifier_order[] = { I915_FORMAT_MOD_Y_TILED_CCS,
41 I915_FORMAT_MOD_Y_TILED, I915_FORMAT_MOD_X_TILED,
42 DRM_FORMAT_MOD_LINEAR };
44 struct modifier_support_t {
45 const uint64_t *order;
52 struct modifier_support_t modifier;
55 static uint32_t i915_get_gen(int device_id)
57 const uint16_t gen3_ids[] = { 0x2582, 0x2592, 0x2772, 0x27A2, 0x27AE,
58 0x29C2, 0x29B2, 0x29D2, 0xA001, 0xA011 };
59 const uint16_t gen11_ids[] = { 0x4E71, 0x4E61, 0x4E51, 0x4E55, 0x4E57 };
60 const uint16_t gen12_ids[] = { 0x9A40, 0x9A49, 0x9A59, 0x9A60, 0x9A68, 0x9A70,
61 0x9A78, 0x9AC0, 0x9AC9, 0x9AD9, 0x9AF8 };
63 for (i = 0; i < ARRAY_SIZE(gen3_ids); i++)
64 if (gen3_ids[i] == device_id)
67 for (i = 0; i < ARRAY_SIZE(gen11_ids); i++)
68 if (gen11_ids[i] == device_id)
72 for (i = 0; i < ARRAY_SIZE(gen12_ids); i++)
73 if (gen12_ids[i] == device_id)
79 static void i915_get_modifier_order(struct i915_device *i915)
81 if (i915->gen == 11) {
82 i915->modifier.order = gen11_modifier_order;
83 i915->modifier.count = ARRAY_SIZE(gen11_modifier_order);
85 i915->modifier.order = gen_modifier_order;
86 i915->modifier.count = ARRAY_SIZE(gen_modifier_order);
90 static uint64_t unset_flags(uint64_t current_flags, uint64_t mask)
92 uint64_t value = current_flags & ~mask;
96 static int i915_add_combinations(struct driver *drv)
98 struct format_metadata metadata;
99 uint64_t render, scanout_and_render, texture_only;
101 scanout_and_render = BO_USE_RENDER_MASK | BO_USE_SCANOUT;
102 render = BO_USE_RENDER_MASK;
103 texture_only = BO_USE_TEXTURE_MASK;
104 uint64_t linear_mask =
105 BO_USE_RENDERSCRIPT | BO_USE_LINEAR | BO_USE_SW_READ_OFTEN | BO_USE_SW_WRITE_OFTEN;
107 metadata.tiling = I915_TILING_NONE;
108 metadata.priority = 1;
109 metadata.modifier = DRM_FORMAT_MOD_LINEAR;
111 drv_add_combinations(drv, scanout_render_formats, ARRAY_SIZE(scanout_render_formats),
112 &metadata, scanout_and_render);
114 drv_add_combinations(drv, render_formats, ARRAY_SIZE(render_formats), &metadata, render);
116 drv_add_combinations(drv, texture_only_formats, ARRAY_SIZE(texture_only_formats), &metadata,
119 drv_modify_linear_combinations(drv);
121 /* NV12 format for camera, display, decoding and encoding. */
122 /* IPU3 camera ISP supports only NV12 output. */
123 drv_modify_combination(drv, DRM_FORMAT_NV12, &metadata,
124 BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE | BO_USE_SCANOUT |
125 BO_USE_HW_VIDEO_DECODER | BO_USE_HW_VIDEO_ENCODER);
127 /* Android CTS tests require this. */
128 drv_add_combination(drv, DRM_FORMAT_BGR888, &metadata, BO_USE_SW_MASK);
131 * R8 format is used for Android's HAL_PIXEL_FORMAT_BLOB and is used for JPEG snapshots
132 * from camera and input/output from hardware decoder/encoder.
134 drv_modify_combination(drv, DRM_FORMAT_R8, &metadata,
135 BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE | BO_USE_HW_VIDEO_DECODER |
136 BO_USE_HW_VIDEO_ENCODER);
138 render = unset_flags(render, linear_mask);
139 scanout_and_render = unset_flags(scanout_and_render, linear_mask);
141 metadata.tiling = I915_TILING_X;
142 metadata.priority = 2;
143 metadata.modifier = I915_FORMAT_MOD_X_TILED;
145 drv_add_combinations(drv, render_formats, ARRAY_SIZE(render_formats), &metadata, render);
146 drv_add_combinations(drv, scanout_render_formats, ARRAY_SIZE(scanout_render_formats),
147 &metadata, scanout_and_render);
149 metadata.tiling = I915_TILING_Y;
150 metadata.priority = 3;
151 metadata.modifier = I915_FORMAT_MOD_Y_TILED;
154 unset_flags(scanout_and_render, BO_USE_SW_READ_RARELY | BO_USE_SW_WRITE_RARELY);
155 /* Support y-tiled NV12 and P010 for libva */
156 #ifdef I915_SCANOUT_Y_TILED
157 drv_add_combination(drv, DRM_FORMAT_NV12, &metadata,
158 BO_USE_TEXTURE | BO_USE_HW_VIDEO_DECODER | BO_USE_SCANOUT);
160 drv_add_combination(drv, DRM_FORMAT_NV12, &metadata,
161 BO_USE_TEXTURE | BO_USE_HW_VIDEO_DECODER);
163 scanout_and_render = unset_flags(scanout_and_render, BO_USE_SCANOUT);
164 drv_add_combination(drv, DRM_FORMAT_P010, &metadata,
165 BO_USE_TEXTURE | BO_USE_HW_VIDEO_DECODER);
167 drv_add_combinations(drv, render_formats, ARRAY_SIZE(render_formats), &metadata, render);
168 drv_add_combinations(drv, scanout_render_formats, ARRAY_SIZE(scanout_render_formats),
169 &metadata, scanout_and_render);
173 static int i915_align_dimensions(struct bo *bo, uint32_t tiling, uint32_t *stride,
174 uint32_t *aligned_height)
176 struct i915_device *i915 = bo->drv->priv;
177 uint32_t horizontal_alignment;
178 uint32_t vertical_alignment;
182 case I915_TILING_NONE:
184 * The Intel GPU doesn't need any alignment in linear mode,
185 * but libva requires the allocation stride to be aligned to
186 * 16 bytes and height to 4 rows. Further, we round up the
187 * horizontal alignment so that row start on a cache line (64
190 horizontal_alignment = 64;
191 vertical_alignment = 4;
195 horizontal_alignment = 512;
196 vertical_alignment = 8;
200 if (i915->gen == 3) {
201 horizontal_alignment = 512;
202 vertical_alignment = 8;
204 horizontal_alignment = 128;
205 vertical_alignment = 32;
210 *aligned_height = ALIGN(*aligned_height, vertical_alignment);
212 *stride = ALIGN(*stride, horizontal_alignment);
214 while (*stride > horizontal_alignment)
215 horizontal_alignment <<= 1;
217 *stride = horizontal_alignment;
220 if (i915->gen <= 3 && *stride > 8192)
226 static void i915_clflush(void *start, size_t size)
228 void *p = (void *)(((uintptr_t)start) & ~I915_CACHELINE_MASK);
229 void *end = (void *)((uintptr_t)start + size);
231 __builtin_ia32_mfence();
233 __builtin_ia32_clflush(p);
234 p = (void *)((uintptr_t)p + I915_CACHELINE_SIZE);
238 static int i915_init(struct driver *drv)
242 struct i915_device *i915;
243 drm_i915_getparam_t get_param = { 0 };
245 i915 = calloc(1, sizeof(*i915));
249 get_param.param = I915_PARAM_CHIPSET_ID;
250 get_param.value = &device_id;
251 ret = drmIoctl(drv->fd, DRM_IOCTL_I915_GETPARAM, &get_param);
253 drv_log("Failed to get I915_PARAM_CHIPSET_ID\n");
258 i915->gen = i915_get_gen(device_id);
259 i915_get_modifier_order(i915);
261 memset(&get_param, 0, sizeof(get_param));
262 get_param.param = I915_PARAM_HAS_LLC;
263 get_param.value = &i915->has_llc;
264 ret = drmIoctl(drv->fd, DRM_IOCTL_I915_GETPARAM, &get_param);
266 drv_log("Failed to get I915_PARAM_HAS_LLC\n");
273 return i915_add_combinations(drv);
276 static int i915_bo_from_format(struct bo *bo, uint32_t width, uint32_t height, uint32_t format)
283 pagesize = getpagesize();
284 for (plane = 0; plane < drv_num_planes_from_format(format); plane++) {
285 uint32_t stride = drv_stride_from_format(format, width, plane);
286 uint32_t plane_height = drv_height_from_format(format, height, plane);
288 if (bo->meta.tiling != I915_TILING_NONE)
289 assert(IS_ALIGNED(offset, pagesize));
291 ret = i915_align_dimensions(bo, bo->meta.tiling, &stride, &plane_height);
295 bo->meta.strides[plane] = stride;
296 bo->meta.sizes[plane] = stride * plane_height;
297 bo->meta.offsets[plane] = offset;
298 offset += bo->meta.sizes[plane];
301 bo->meta.total_size = ALIGN(offset, pagesize);
306 static int i915_bo_compute_metadata(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
307 uint64_t use_flags, const uint64_t *modifiers, uint32_t count)
310 struct i915_device *i915 = bo->drv->priv;
311 bool huge_bo = (i915->gen < 11) && (width > 4096);
315 drv_pick_modifier(modifiers, count, i915->modifier.order, i915->modifier.count);
317 struct combination *combo = drv_get_combination(bo->drv, format, use_flags);
320 modifier = combo->metadata.modifier;
324 * i915 only supports linear/x-tiled above 4096 wide on Gen9/Gen10 GPU.
325 * VAAPI decode in NV12 Y tiled format so skip modifier change for NV12/P010 huge bo.
327 if (huge_bo && format != DRM_FORMAT_NV12 && format != DRM_FORMAT_P010 &&
328 modifier != I915_FORMAT_MOD_X_TILED && modifier != DRM_FORMAT_MOD_LINEAR) {
330 for (i = 0; modifiers && i < count; i++) {
331 if (modifiers[i] == I915_FORMAT_MOD_X_TILED)
335 modifier = DRM_FORMAT_MOD_LINEAR;
337 modifier = I915_FORMAT_MOD_X_TILED;
341 case DRM_FORMAT_MOD_LINEAR:
342 bo->meta.tiling = I915_TILING_NONE;
344 case I915_FORMAT_MOD_X_TILED:
345 bo->meta.tiling = I915_TILING_X;
347 case I915_FORMAT_MOD_Y_TILED:
348 case I915_FORMAT_MOD_Y_TILED_CCS:
349 bo->meta.tiling = I915_TILING_Y;
353 bo->meta.format_modifiers[0] = modifier;
355 if (format == DRM_FORMAT_YVU420_ANDROID) {
357 * We only need to be able to use this as a linear texture,
358 * which doesn't put any HW restrictions on how we lay it
359 * out. The Android format does require the stride to be a
360 * multiple of 16 and expects the Cr and Cb stride to be
361 * ALIGN(Y_stride / 2, 16), which we can make happen by
362 * aligning to 32 bytes here.
364 uint32_t stride = ALIGN(width, 32);
365 drv_bo_from_format(bo, stride, height, format);
366 } else if (modifier == I915_FORMAT_MOD_Y_TILED_CCS) {
368 * For compressed surfaces, we need a color control surface
369 * (CCS). Color compression is only supported for Y tiled
370 * surfaces, and for each 32x16 tiles in the main surface we
371 * need a tile in the control surface. Y tiles are 128 bytes
372 * wide and 32 lines tall and we use that to first compute the
373 * width and height in tiles of the main surface. stride and
374 * height are already multiples of 128 and 32, respectively:
376 uint32_t stride = drv_stride_from_format(format, width, 0);
377 uint32_t width_in_tiles = DIV_ROUND_UP(stride, 128);
378 uint32_t height_in_tiles = DIV_ROUND_UP(height, 32);
379 uint32_t size = width_in_tiles * height_in_tiles * 4096;
382 bo->meta.strides[0] = width_in_tiles * 128;
383 bo->meta.sizes[0] = size;
384 bo->meta.offsets[0] = offset;
388 * Now, compute the width and height in tiles of the control
389 * surface by dividing and rounding up.
391 uint32_t ccs_width_in_tiles = DIV_ROUND_UP(width_in_tiles, 32);
392 uint32_t ccs_height_in_tiles = DIV_ROUND_UP(height_in_tiles, 16);
393 uint32_t ccs_size = ccs_width_in_tiles * ccs_height_in_tiles * 4096;
396 * With stride and height aligned to y tiles, offset is
397 * already a multiple of 4096, which is the required alignment
400 bo->meta.strides[1] = ccs_width_in_tiles * 128;
401 bo->meta.sizes[1] = ccs_size;
402 bo->meta.offsets[1] = offset;
405 bo->meta.num_planes = 2;
406 bo->meta.total_size = offset;
408 i915_bo_from_format(bo, width, height, format);
413 static int i915_bo_create_from_metadata(struct bo *bo)
417 struct drm_i915_gem_create gem_create = { 0 };
418 struct drm_i915_gem_set_tiling gem_set_tiling = { 0 };
420 gem_create.size = bo->meta.total_size;
421 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_CREATE, &gem_create);
423 drv_log("DRM_IOCTL_I915_GEM_CREATE failed (size=%llu)\n", gem_create.size);
427 for (plane = 0; plane < bo->meta.num_planes; plane++)
428 bo->handles[plane].u32 = gem_create.handle;
430 gem_set_tiling.handle = bo->handles[0].u32;
431 gem_set_tiling.tiling_mode = bo->meta.tiling;
432 gem_set_tiling.stride = bo->meta.strides[0];
434 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_SET_TILING, &gem_set_tiling);
436 struct drm_gem_close gem_close = { 0 };
437 gem_close.handle = bo->handles[0].u32;
438 drmIoctl(bo->drv->fd, DRM_IOCTL_GEM_CLOSE, &gem_close);
440 drv_log("DRM_IOCTL_I915_GEM_SET_TILING failed with %d\n", errno);
447 static void i915_close(struct driver *drv)
453 static int i915_bo_import(struct bo *bo, struct drv_import_fd_data *data)
456 struct drm_i915_gem_get_tiling gem_get_tiling = { 0 };
458 ret = drv_prime_bo_import(bo, data);
462 /* TODO(gsingh): export modifiers and get rid of backdoor tiling. */
463 gem_get_tiling.handle = bo->handles[0].u32;
465 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_GET_TILING, &gem_get_tiling);
467 drv_gem_bo_destroy(bo);
468 drv_log("DRM_IOCTL_I915_GEM_GET_TILING failed.\n");
472 bo->meta.tiling = gem_get_tiling.tiling_mode;
476 static void *i915_bo_map(struct bo *bo, struct vma *vma, size_t plane, uint32_t map_flags)
481 if (bo->meta.format_modifiers[0] == I915_FORMAT_MOD_Y_TILED_CCS)
484 if (bo->meta.tiling == I915_TILING_NONE) {
485 struct drm_i915_gem_mmap gem_map = { 0 };
486 /* TODO(b/118799155): We don't seem to have a good way to
487 * detect the use cases for which WC mapping is really needed.
488 * The current heuristic seems overly coarse and may be slowing
489 * down some other use cases unnecessarily.
491 * For now, care must be taken not to use WC mappings for
492 * Renderscript and camera use cases, as they're
493 * performance-sensitive. */
494 if ((bo->meta.use_flags & BO_USE_SCANOUT) &&
495 !(bo->meta.use_flags &
496 (BO_USE_RENDERSCRIPT | BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE)))
497 gem_map.flags = I915_MMAP_WC;
499 gem_map.handle = bo->handles[0].u32;
501 gem_map.size = bo->meta.total_size;
503 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_MMAP, &gem_map);
505 drv_log("DRM_IOCTL_I915_GEM_MMAP failed\n");
509 addr = (void *)(uintptr_t)gem_map.addr_ptr;
511 struct drm_i915_gem_mmap_gtt gem_map = { 0 };
513 gem_map.handle = bo->handles[0].u32;
514 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_MMAP_GTT, &gem_map);
516 drv_log("DRM_IOCTL_I915_GEM_MMAP_GTT failed\n");
520 addr = mmap(0, bo->meta.total_size, drv_get_prot(map_flags), MAP_SHARED,
521 bo->drv->fd, gem_map.offset);
524 if (addr == MAP_FAILED) {
525 drv_log("i915 GEM mmap failed\n");
529 vma->length = bo->meta.total_size;
533 static int i915_bo_invalidate(struct bo *bo, struct mapping *mapping)
536 struct drm_i915_gem_set_domain set_domain = { 0 };
538 set_domain.handle = bo->handles[0].u32;
539 if (bo->meta.tiling == I915_TILING_NONE) {
540 set_domain.read_domains = I915_GEM_DOMAIN_CPU;
541 if (mapping->vma->map_flags & BO_MAP_WRITE)
542 set_domain.write_domain = I915_GEM_DOMAIN_CPU;
544 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
545 if (mapping->vma->map_flags & BO_MAP_WRITE)
546 set_domain.write_domain = I915_GEM_DOMAIN_GTT;
549 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_SET_DOMAIN, &set_domain);
551 drv_log("DRM_IOCTL_I915_GEM_SET_DOMAIN with %d\n", ret);
558 static int i915_bo_flush(struct bo *bo, struct mapping *mapping)
560 struct i915_device *i915 = bo->drv->priv;
561 if (!i915->has_llc && bo->meta.tiling == I915_TILING_NONE)
562 i915_clflush(mapping->vma->addr, mapping->vma->length);
567 static uint32_t i915_resolve_format(struct driver *drv, uint32_t format, uint64_t use_flags)
570 case DRM_FORMAT_FLEX_IMPLEMENTATION_DEFINED:
571 /* KBL camera subsystem requires NV12. */
572 if (use_flags & (BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE))
573 return DRM_FORMAT_NV12;
574 /*HACK: See b/28671744 */
575 return DRM_FORMAT_XBGR8888;
576 case DRM_FORMAT_FLEX_YCbCr_420_888:
578 * KBL camera subsystem requires NV12. Our other use cases
580 * - Hardware video supports NV12,
581 * - USB Camera HALv3 supports NV12,
582 * - USB Camera HALv1 doesn't use this format.
583 * Moreover, NV12 is preferred for video, due to overlay
586 return DRM_FORMAT_NV12;
592 const struct backend backend_i915 = {
596 .bo_compute_metadata = i915_bo_compute_metadata,
597 .bo_create_from_metadata = i915_bo_create_from_metadata,
598 .bo_destroy = drv_gem_bo_destroy,
599 .bo_import = i915_bo_import,
600 .bo_map = i915_bo_map,
601 .bo_unmap = drv_bo_munmap,
602 .bo_invalidate = i915_bo_invalidate,
603 .bo_flush = i915_bo_flush,
604 .resolve_format = i915_resolve_format,