2 * Copyright 2014 The Chromium OS Authors. All rights reserved.
3 * Use of this source code is governed by a BSD-style license that can be
4 * found in the LICENSE file.
20 #define I915_CACHELINE_SIZE 64
21 #define I915_CACHELINE_MASK (I915_CACHELINE_SIZE - 1)
23 static const uint32_t render_target_formats[] = { DRM_FORMAT_ARGB1555, DRM_FORMAT_ABGR8888,
24 DRM_FORMAT_ARGB8888, DRM_FORMAT_RGB565,
25 DRM_FORMAT_XBGR8888, DRM_FORMAT_XRGB1555,
26 DRM_FORMAT_XRGB8888 };
28 static const uint32_t tileable_texture_source_formats[] = { DRM_FORMAT_GR88, DRM_FORMAT_NV12,
29 DRM_FORMAT_R8, DRM_FORMAT_UYVY,
32 static const uint32_t texture_source_formats[] = { DRM_FORMAT_YVU420, DRM_FORMAT_YVU420_ANDROID };
39 static uint32_t i915_get_gen(int device_id)
41 const uint16_t gen3_ids[] = { 0x2582, 0x2592, 0x2772, 0x27A2, 0x27AE,
42 0x29C2, 0x29B2, 0x29D2, 0xA001, 0xA011 };
44 for (i = 0; i < ARRAY_SIZE(gen3_ids); i++)
45 if (gen3_ids[i] == device_id)
51 static int i915_add_kms_item(struct driver *drv, const struct kms_item *item)
54 struct combination *combo;
57 * Older hardware can't scanout Y-tiled formats. Newer devices can, and
58 * report this functionality via format modifiers.
60 for (i = 0; i < drv->backend->combos.size; i++) {
61 combo = &drv->backend->combos.data[i];
62 if (combo->format == item->format) {
63 if ((combo->metadata.tiling == I915_TILING_Y &&
64 item->modifier == I915_FORMAT_MOD_Y_TILED) ||
65 (combo->metadata.tiling == I915_TILING_X &&
66 item->modifier == I915_FORMAT_MOD_X_TILED)) {
67 combo->metadata.modifier = item->modifier;
68 combo->usage |= item->usage;
69 } else if (combo->metadata.tiling != I915_TILING_Y) {
70 combo->usage |= item->usage;
78 static int i915_add_combinations(struct driver *drv)
81 uint32_t i, num_items;
82 struct kms_item *items;
83 struct format_metadata metadata;
84 uint64_t render_flags, texture_flags;
86 render_flags = BO_USE_RENDER_MASK;
87 texture_flags = BO_USE_TEXTURE_MASK;
89 metadata.tiling = I915_TILING_NONE;
90 metadata.priority = 1;
91 metadata.modifier = DRM_FORMAT_MOD_NONE;
93 ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
94 &metadata, render_flags);
98 ret = drv_add_combinations(drv, texture_source_formats, ARRAY_SIZE(texture_source_formats),
99 &metadata, texture_flags);
103 ret = drv_add_combinations(drv, tileable_texture_source_formats,
104 ARRAY_SIZE(tileable_texture_source_formats), &metadata,
109 drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
110 drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
112 render_flags &= ~BO_USE_SW_WRITE_OFTEN;
113 render_flags &= ~BO_USE_SW_READ_OFTEN;
114 render_flags &= ~BO_USE_LINEAR;
116 texture_flags &= ~BO_USE_SW_WRITE_OFTEN;
117 texture_flags &= ~BO_USE_SW_READ_OFTEN;
118 texture_flags &= ~BO_USE_LINEAR;
120 metadata.tiling = I915_TILING_X;
121 metadata.priority = 2;
123 ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
124 &metadata, render_flags);
128 ret = drv_add_combinations(drv, tileable_texture_source_formats,
129 ARRAY_SIZE(tileable_texture_source_formats), &metadata,
134 metadata.tiling = I915_TILING_Y;
135 metadata.priority = 3;
137 ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
138 &metadata, render_flags);
142 ret = drv_add_combinations(drv, tileable_texture_source_formats,
143 ARRAY_SIZE(tileable_texture_source_formats), &metadata,
148 items = drv_query_kms(drv, &num_items);
149 if (!items || !num_items)
152 for (i = 0; i < num_items; i++) {
153 ret = i915_add_kms_item(drv, &items[i]);
164 static int i915_align_dimensions(struct bo *bo, uint32_t tiling, uint32_t *stride,
165 uint32_t *aligned_height)
167 struct i915_device *i915 = bo->drv->priv;
168 uint32_t horizontal_alignment = 4;
169 uint32_t vertical_alignment = 4;
173 case I915_TILING_NONE:
174 horizontal_alignment = 64;
178 horizontal_alignment = 512;
179 vertical_alignment = 8;
183 if (i915->gen == 3) {
184 horizontal_alignment = 512;
185 vertical_alignment = 8;
187 horizontal_alignment = 128;
188 vertical_alignment = 32;
193 *aligned_height = ALIGN(bo->height, vertical_alignment);
195 *stride = ALIGN(*stride, horizontal_alignment);
197 while (*stride > horizontal_alignment)
198 horizontal_alignment <<= 1;
200 *stride = horizontal_alignment;
203 if (i915->gen <= 3 && *stride > 8192)
209 static void i915_clflush(void *start, size_t size)
211 void *p = (void *)(((uintptr_t)start) & ~I915_CACHELINE_MASK);
212 void *end = (void *)((uintptr_t)start + size);
214 __builtin_ia32_mfence();
216 __builtin_ia32_clflush(p);
217 p = (void *)((uintptr_t)p + I915_CACHELINE_SIZE);
221 static int i915_init(struct driver *drv)
225 struct i915_device *i915;
226 drm_i915_getparam_t get_param;
228 i915 = calloc(1, sizeof(*i915));
232 memset(&get_param, 0, sizeof(get_param));
233 get_param.param = I915_PARAM_CHIPSET_ID;
234 get_param.value = &device_id;
235 ret = drmIoctl(drv->fd, DRM_IOCTL_I915_GETPARAM, &get_param);
237 fprintf(stderr, "drv: Failed to get I915_PARAM_CHIPSET_ID\n");
242 i915->gen = i915_get_gen(device_id);
244 memset(&get_param, 0, sizeof(get_param));
245 get_param.param = I915_PARAM_HAS_LLC;
246 get_param.value = &i915->has_llc;
247 ret = drmIoctl(drv->fd, DRM_IOCTL_I915_GETPARAM, &get_param);
249 fprintf(stderr, "drv: Failed to get I915_PARAM_HAS_LLC\n");
256 return i915_add_combinations(drv);
259 static int i915_bo_create(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
265 struct drm_i915_gem_create gem_create;
266 struct drm_i915_gem_set_tiling gem_set_tiling;
268 if (flags & (BO_USE_CURSOR | BO_USE_LINEAR | BO_USE_SW_READ_OFTEN | BO_USE_SW_WRITE_OFTEN))
269 bo->tiling = I915_TILING_NONE;
270 else if (flags & BO_USE_SCANOUT)
271 bo->tiling = I915_TILING_X;
273 bo->tiling = I915_TILING_Y;
275 if (format == DRM_FORMAT_YVU420 || format == DRM_FORMAT_YVU420_ANDROID)
276 bo->tiling = I915_TILING_NONE;
278 stride = drv_stride_from_format(format, width, 0);
280 ret = i915_align_dimensions(bo, bo->tiling, &stride, &height);
285 * Align the Y plane to 128 bytes so the chroma planes would be aligned
286 * to 64 byte boundaries. This is an Intel HW requirement.
288 if (format == DRM_FORMAT_YVU420)
289 stride = ALIGN(stride, 128);
292 * HAL_PIXEL_FORMAT_YV12 requires that the buffer's height not be aligned.
294 if (format == DRM_FORMAT_YVU420_ANDROID)
297 drv_bo_from_format(bo, stride, height, format);
299 memset(&gem_create, 0, sizeof(gem_create));
300 gem_create.size = bo->total_size;
302 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_CREATE, &gem_create);
304 fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_CREATE failed (size=%llu)\n",
309 for (plane = 0; plane < bo->num_planes; plane++)
310 bo->handles[plane].u32 = gem_create.handle;
312 memset(&gem_set_tiling, 0, sizeof(gem_set_tiling));
313 gem_set_tiling.handle = bo->handles[0].u32;
314 gem_set_tiling.tiling_mode = bo->tiling;
315 gem_set_tiling.stride = bo->strides[0];
317 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_SET_TILING, &gem_set_tiling);
319 struct drm_gem_close gem_close;
320 memset(&gem_close, 0, sizeof(gem_close));
321 gem_close.handle = bo->handles[0].u32;
322 drmIoctl(bo->drv->fd, DRM_IOCTL_GEM_CLOSE, &gem_close);
324 fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_SET_TILING failed with %d", errno);
331 static void i915_close(struct driver *drv)
337 static int i915_bo_import(struct bo *bo, struct drv_import_fd_data *data)
340 struct drm_i915_gem_get_tiling gem_get_tiling;
342 ret = drv_prime_bo_import(bo, data);
346 /* TODO(gsingh): export modifiers and get rid of backdoor tiling. */
347 memset(&gem_get_tiling, 0, sizeof(gem_get_tiling));
348 gem_get_tiling.handle = bo->handles[0].u32;
350 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_GET_TILING, &gem_get_tiling);
352 fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_GET_TILING failed.");
356 bo->tiling = gem_get_tiling.tiling_mode;
360 static void *i915_bo_map(struct bo *bo, struct map_info *data, size_t plane)
364 struct drm_i915_gem_set_domain set_domain;
366 memset(&set_domain, 0, sizeof(set_domain));
367 set_domain.handle = bo->handles[0].u32;
368 if (bo->tiling == I915_TILING_NONE) {
369 struct drm_i915_gem_mmap gem_map;
370 memset(&gem_map, 0, sizeof(gem_map));
372 gem_map.handle = bo->handles[0].u32;
374 gem_map.size = bo->total_size;
376 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_MMAP, &gem_map);
378 fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_MMAP failed\n");
382 addr = (void *)(uintptr_t)gem_map.addr_ptr;
383 set_domain.read_domains = I915_GEM_DOMAIN_CPU;
384 set_domain.write_domain = I915_GEM_DOMAIN_CPU;
387 struct drm_i915_gem_mmap_gtt gem_map;
388 memset(&gem_map, 0, sizeof(gem_map));
390 gem_map.handle = bo->handles[0].u32;
392 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_MMAP_GTT, &gem_map);
394 fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_MMAP_GTT failed\n");
398 addr = mmap(0, bo->total_size, PROT_READ | PROT_WRITE, MAP_SHARED, bo->drv->fd,
401 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
402 set_domain.write_domain = I915_GEM_DOMAIN_GTT;
405 if (addr == MAP_FAILED) {
406 fprintf(stderr, "drv: i915 GEM mmap failed\n");
410 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_SET_DOMAIN, &set_domain);
412 fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_SET_DOMAIN failed\n");
416 data->length = bo->total_size;
420 static int i915_bo_unmap(struct bo *bo, struct map_info *data)
422 struct i915_device *i915 = bo->drv->priv;
423 if (!i915->has_llc && bo->tiling == I915_TILING_NONE)
424 i915_clflush(data->addr, data->length);
426 return munmap(data->addr, data->length);
429 static uint32_t i915_resolve_format(uint32_t format)
432 case DRM_FORMAT_FLEX_IMPLEMENTATION_DEFINED:
433 /*HACK: See b/28671744 */
434 return DRM_FORMAT_XBGR8888;
435 case DRM_FORMAT_FLEX_YCbCr_420_888:
436 return DRM_FORMAT_YVU420;
442 struct backend backend_i915 = {
446 .bo_create = i915_bo_create,
447 .bo_destroy = drv_gem_bo_destroy,
448 .bo_import = i915_bo_import,
449 .bo_map = i915_bo_map,
450 .bo_unmap = i915_bo_unmap,
451 .resolve_format = i915_resolve_format,