2 * Copyright 2014 The Chromium OS Authors. All rights reserved.
3 * Use of this source code is governed by a BSD-style license that can be
4 * found in the LICENSE file.
23 #define I915_CACHELINE_SIZE 64
24 #define I915_CACHELINE_MASK (I915_CACHELINE_SIZE - 1)
26 static const uint32_t scanout_render_formats[] = { DRM_FORMAT_ABGR2101010, DRM_FORMAT_ABGR8888,
27 DRM_FORMAT_ARGB2101010, DRM_FORMAT_ARGB8888,
28 DRM_FORMAT_RGB565, DRM_FORMAT_XBGR2101010,
29 DRM_FORMAT_XBGR8888, DRM_FORMAT_XRGB2101010,
30 DRM_FORMAT_XRGB8888 };
32 static const uint32_t render_formats[] = { DRM_FORMAT_ABGR16161616F };
34 static const uint32_t texture_only_formats[] = { DRM_FORMAT_R8, DRM_FORMAT_NV12, DRM_FORMAT_P010,
35 DRM_FORMAT_YVU420, DRM_FORMAT_YVU420_ANDROID };
37 static const uint64_t gen_modifier_order[] = { I915_FORMAT_MOD_Y_TILED, I915_FORMAT_MOD_X_TILED,
38 DRM_FORMAT_MOD_LINEAR };
40 static const uint64_t gen11_modifier_order[] = { I915_FORMAT_MOD_Y_TILED_CCS,
41 I915_FORMAT_MOD_Y_TILED, I915_FORMAT_MOD_X_TILED,
42 DRM_FORMAT_MOD_LINEAR };
44 struct modifier_support_t {
45 const uint64_t *order;
52 struct modifier_support_t modifier;
55 static uint32_t i915_get_gen(int device_id)
57 const uint16_t gen3_ids[] = { 0x2582, 0x2592, 0x2772, 0x27A2, 0x27AE,
58 0x29C2, 0x29B2, 0x29D2, 0xA001, 0xA011 };
59 const uint16_t gen11_ids[] = { 0x4E71, 0x4E61, 0x4E51, 0x4E55, 0x4E57 };
60 const uint16_t gen12_ids[] = { 0x9A40, 0x9A49, 0x9A59, 0x9A60, 0x9A68,
61 0x9A70, 0x9A78, 0x9AC0, 0x9AC9, 0x9AD9,
64 for (i = 0; i < ARRAY_SIZE(gen3_ids); i++)
65 if (gen3_ids[i] == device_id)
68 for (i = 0; i < ARRAY_SIZE(gen11_ids); i++)
69 if (gen11_ids[i] == device_id)
73 for (i = 0; i < ARRAY_SIZE(gen12_ids); i++)
74 if (gen12_ids[i] == device_id)
80 static void i915_get_modifier_order(struct i915_device *i915)
82 if (i915->gen == 11) {
83 i915->modifier.order = gen11_modifier_order;
84 i915->modifier.count = ARRAY_SIZE(gen11_modifier_order);
86 i915->modifier.order = gen_modifier_order;
87 i915->modifier.count = ARRAY_SIZE(gen_modifier_order);
91 static uint64_t unset_flags(uint64_t current_flags, uint64_t mask)
93 uint64_t value = current_flags & ~mask;
97 static int i915_add_combinations(struct driver *drv)
99 struct format_metadata metadata;
100 uint64_t render, scanout_and_render, texture_only;
102 scanout_and_render = BO_USE_RENDER_MASK | BO_USE_SCANOUT;
103 render = BO_USE_RENDER_MASK;
104 texture_only = BO_USE_TEXTURE_MASK;
105 uint64_t linear_mask =
106 BO_USE_RENDERSCRIPT | BO_USE_LINEAR | BO_USE_SW_READ_OFTEN | BO_USE_SW_WRITE_OFTEN;
108 metadata.tiling = I915_TILING_NONE;
109 metadata.priority = 1;
110 metadata.modifier = DRM_FORMAT_MOD_LINEAR;
112 drv_add_combinations(drv, scanout_render_formats, ARRAY_SIZE(scanout_render_formats),
113 &metadata, scanout_and_render);
115 drv_add_combinations(drv, render_formats, ARRAY_SIZE(render_formats), &metadata, render);
117 drv_add_combinations(drv, texture_only_formats, ARRAY_SIZE(texture_only_formats), &metadata,
120 drv_modify_linear_combinations(drv);
122 /* NV12 format for camera, display, decoding and encoding. */
123 /* IPU3 camera ISP supports only NV12 output. */
124 drv_modify_combination(drv, DRM_FORMAT_NV12, &metadata,
125 BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE | BO_USE_SCANOUT |
126 BO_USE_HW_VIDEO_DECODER | BO_USE_HW_VIDEO_ENCODER);
128 /* Android CTS tests require this. */
129 drv_add_combination(drv, DRM_FORMAT_BGR888, &metadata, BO_USE_SW_MASK);
132 * R8 format is used for Android's HAL_PIXEL_FORMAT_BLOB and is used for JPEG snapshots
133 * from camera and input/output from hardware decoder/encoder.
135 drv_modify_combination(drv, DRM_FORMAT_R8, &metadata,
136 BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE | BO_USE_HW_VIDEO_DECODER |
137 BO_USE_HW_VIDEO_ENCODER);
139 render = unset_flags(render, linear_mask);
140 scanout_and_render = unset_flags(scanout_and_render, linear_mask);
142 metadata.tiling = I915_TILING_X;
143 metadata.priority = 2;
144 metadata.modifier = I915_FORMAT_MOD_X_TILED;
146 drv_add_combinations(drv, render_formats, ARRAY_SIZE(render_formats), &metadata, render);
147 drv_add_combinations(drv, scanout_render_formats, ARRAY_SIZE(scanout_render_formats),
148 &metadata, scanout_and_render);
150 metadata.tiling = I915_TILING_Y;
151 metadata.priority = 3;
152 metadata.modifier = I915_FORMAT_MOD_Y_TILED;
155 unset_flags(scanout_and_render, BO_USE_SW_READ_RARELY | BO_USE_SW_WRITE_RARELY);
156 /* Support y-tiled NV12 and P010 for libva */
157 #ifdef I915_SCANOUT_Y_TILED
158 drv_add_combination(drv, DRM_FORMAT_NV12, &metadata,
159 BO_USE_TEXTURE | BO_USE_HW_VIDEO_DECODER | BO_USE_SCANOUT);
161 drv_add_combination(drv, DRM_FORMAT_NV12, &metadata,
162 BO_USE_TEXTURE | BO_USE_HW_VIDEO_DECODER);
164 scanout_and_render = unset_flags(scanout_and_render, BO_USE_SCANOUT);
165 drv_add_combination(drv, DRM_FORMAT_P010, &metadata,
166 BO_USE_TEXTURE | BO_USE_HW_VIDEO_DECODER);
168 drv_add_combinations(drv, render_formats, ARRAY_SIZE(render_formats), &metadata, render);
169 drv_add_combinations(drv, scanout_render_formats, ARRAY_SIZE(scanout_render_formats),
170 &metadata, scanout_and_render);
174 static int i915_align_dimensions(struct bo *bo, uint32_t tiling, uint32_t *stride,
175 uint32_t *aligned_height)
177 struct i915_device *i915 = bo->drv->priv;
178 uint32_t horizontal_alignment;
179 uint32_t vertical_alignment;
183 case I915_TILING_NONE:
185 * The Intel GPU doesn't need any alignment in linear mode,
186 * but libva requires the allocation stride to be aligned to
187 * 16 bytes and height to 4 rows. Further, we round up the
188 * horizontal alignment so that row start on a cache line (64
191 horizontal_alignment = 64;
192 vertical_alignment = 4;
196 horizontal_alignment = 512;
197 vertical_alignment = 8;
201 if (i915->gen == 3) {
202 horizontal_alignment = 512;
203 vertical_alignment = 8;
205 horizontal_alignment = 128;
206 vertical_alignment = 32;
211 *aligned_height = ALIGN(*aligned_height, vertical_alignment);
213 *stride = ALIGN(*stride, horizontal_alignment);
215 while (*stride > horizontal_alignment)
216 horizontal_alignment <<= 1;
218 *stride = horizontal_alignment;
221 if (i915->gen <= 3 && *stride > 8192)
227 static void i915_clflush(void *start, size_t size)
229 void *p = (void *)(((uintptr_t)start) & ~I915_CACHELINE_MASK);
230 void *end = (void *)((uintptr_t)start + size);
232 __builtin_ia32_mfence();
234 __builtin_ia32_clflush(p);
235 p = (void *)((uintptr_t)p + I915_CACHELINE_SIZE);
239 static int i915_init(struct driver *drv)
243 struct i915_device *i915;
244 drm_i915_getparam_t get_param = { 0 };
246 i915 = calloc(1, sizeof(*i915));
250 get_param.param = I915_PARAM_CHIPSET_ID;
251 get_param.value = &device_id;
252 ret = drmIoctl(drv->fd, DRM_IOCTL_I915_GETPARAM, &get_param);
254 drv_log("Failed to get I915_PARAM_CHIPSET_ID\n");
259 i915->gen = i915_get_gen(device_id);
260 i915_get_modifier_order(i915);
262 memset(&get_param, 0, sizeof(get_param));
263 get_param.param = I915_PARAM_HAS_LLC;
264 get_param.value = &i915->has_llc;
265 ret = drmIoctl(drv->fd, DRM_IOCTL_I915_GETPARAM, &get_param);
267 drv_log("Failed to get I915_PARAM_HAS_LLC\n");
274 return i915_add_combinations(drv);
277 static int i915_bo_from_format(struct bo *bo, uint32_t width, uint32_t height, uint32_t format)
284 pagesize = getpagesize();
285 for (plane = 0; plane < drv_num_planes_from_format(format); plane++) {
286 uint32_t stride = drv_stride_from_format(format, width, plane);
287 uint32_t plane_height = drv_height_from_format(format, height, plane);
289 if (bo->meta.tiling != I915_TILING_NONE)
290 assert(IS_ALIGNED(offset, pagesize));
292 ret = i915_align_dimensions(bo, bo->meta.tiling, &stride, &plane_height);
296 bo->meta.strides[plane] = stride;
297 bo->meta.sizes[plane] = stride * plane_height;
298 bo->meta.offsets[plane] = offset;
299 offset += bo->meta.sizes[plane];
302 bo->meta.total_size = ALIGN(offset, pagesize);
307 static int i915_bo_compute_metadata(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
308 uint64_t use_flags, const uint64_t *modifiers, uint32_t count)
311 struct i915_device *i915 = bo->drv->priv;
312 bool huge_bo = (i915->gen < 11) && (width > 4096);
316 drv_pick_modifier(modifiers, count, i915->modifier.order, i915->modifier.count);
318 struct combination *combo = drv_get_combination(bo->drv, format, use_flags);
321 modifier = combo->metadata.modifier;
325 * i915 only supports linear/x-tiled above 4096 wide
327 if (huge_bo && modifier != I915_FORMAT_MOD_X_TILED && modifier != DRM_FORMAT_MOD_LINEAR) {
329 for (i = 0; modifiers && i < count; i++) {
330 if (modifiers[i] == I915_FORMAT_MOD_X_TILED)
334 modifier = DRM_FORMAT_MOD_LINEAR;
336 modifier = I915_FORMAT_MOD_X_TILED;
340 case DRM_FORMAT_MOD_LINEAR:
341 bo->meta.tiling = I915_TILING_NONE;
343 case I915_FORMAT_MOD_X_TILED:
344 bo->meta.tiling = I915_TILING_X;
346 case I915_FORMAT_MOD_Y_TILED:
347 case I915_FORMAT_MOD_Y_TILED_CCS:
348 bo->meta.tiling = I915_TILING_Y;
352 bo->meta.format_modifiers[0] = modifier;
354 if (format == DRM_FORMAT_YVU420_ANDROID) {
356 * We only need to be able to use this as a linear texture,
357 * which doesn't put any HW restrictions on how we lay it
358 * out. The Android format does require the stride to be a
359 * multiple of 16 and expects the Cr and Cb stride to be
360 * ALIGN(Y_stride / 2, 16), which we can make happen by
361 * aligning to 32 bytes here.
363 uint32_t stride = ALIGN(width, 32);
364 drv_bo_from_format(bo, stride, height, format);
365 } else if (modifier == I915_FORMAT_MOD_Y_TILED_CCS) {
367 * For compressed surfaces, we need a color control surface
368 * (CCS). Color compression is only supported for Y tiled
369 * surfaces, and for each 32x16 tiles in the main surface we
370 * need a tile in the control surface. Y tiles are 128 bytes
371 * wide and 32 lines tall and we use that to first compute the
372 * width and height in tiles of the main surface. stride and
373 * height are already multiples of 128 and 32, respectively:
375 uint32_t stride = drv_stride_from_format(format, width, 0);
376 uint32_t width_in_tiles = DIV_ROUND_UP(stride, 128);
377 uint32_t height_in_tiles = DIV_ROUND_UP(height, 32);
378 uint32_t size = width_in_tiles * height_in_tiles * 4096;
381 bo->meta.strides[0] = width_in_tiles * 128;
382 bo->meta.sizes[0] = size;
383 bo->meta.offsets[0] = offset;
387 * Now, compute the width and height in tiles of the control
388 * surface by dividing and rounding up.
390 uint32_t ccs_width_in_tiles = DIV_ROUND_UP(width_in_tiles, 32);
391 uint32_t ccs_height_in_tiles = DIV_ROUND_UP(height_in_tiles, 16);
392 uint32_t ccs_size = ccs_width_in_tiles * ccs_height_in_tiles * 4096;
395 * With stride and height aligned to y tiles, offset is
396 * already a multiple of 4096, which is the required alignment
399 bo->meta.strides[1] = ccs_width_in_tiles * 128;
400 bo->meta.sizes[1] = ccs_size;
401 bo->meta.offsets[1] = offset;
404 bo->meta.num_planes = 2;
405 bo->meta.total_size = offset;
407 i915_bo_from_format(bo, width, height, format);
412 static int i915_bo_create_from_metadata(struct bo *bo)
416 struct drm_i915_gem_create gem_create = { 0 };
417 struct drm_i915_gem_set_tiling gem_set_tiling = { 0 };
419 gem_create.size = bo->meta.total_size;
420 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_CREATE, &gem_create);
422 drv_log("DRM_IOCTL_I915_GEM_CREATE failed (size=%llu)\n", gem_create.size);
426 for (plane = 0; plane < bo->meta.num_planes; plane++)
427 bo->handles[plane].u32 = gem_create.handle;
429 gem_set_tiling.handle = bo->handles[0].u32;
430 gem_set_tiling.tiling_mode = bo->meta.tiling;
431 gem_set_tiling.stride = bo->meta.strides[0];
433 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_SET_TILING, &gem_set_tiling);
435 struct drm_gem_close gem_close = { 0 };
436 gem_close.handle = bo->handles[0].u32;
437 drmIoctl(bo->drv->fd, DRM_IOCTL_GEM_CLOSE, &gem_close);
439 drv_log("DRM_IOCTL_I915_GEM_SET_TILING failed with %d\n", errno);
446 static void i915_close(struct driver *drv)
452 static int i915_bo_import(struct bo *bo, struct drv_import_fd_data *data)
455 struct drm_i915_gem_get_tiling gem_get_tiling = { 0 };
457 ret = drv_prime_bo_import(bo, data);
461 /* TODO(gsingh): export modifiers and get rid of backdoor tiling. */
462 gem_get_tiling.handle = bo->handles[0].u32;
464 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_GET_TILING, &gem_get_tiling);
466 drv_gem_bo_destroy(bo);
467 drv_log("DRM_IOCTL_I915_GEM_GET_TILING failed.\n");
471 bo->meta.tiling = gem_get_tiling.tiling_mode;
475 static void *i915_bo_map(struct bo *bo, struct vma *vma, size_t plane, uint32_t map_flags)
480 if (bo->meta.format_modifiers[0] == I915_FORMAT_MOD_Y_TILED_CCS)
483 if (bo->meta.tiling == I915_TILING_NONE) {
484 struct drm_i915_gem_mmap gem_map = { 0 };
485 /* TODO(b/118799155): We don't seem to have a good way to
486 * detect the use cases for which WC mapping is really needed.
487 * The current heuristic seems overly coarse and may be slowing
488 * down some other use cases unnecessarily.
490 * For now, care must be taken not to use WC mappings for
491 * Renderscript and camera use cases, as they're
492 * performance-sensitive. */
493 if ((bo->meta.use_flags & BO_USE_SCANOUT) &&
494 !(bo->meta.use_flags &
495 (BO_USE_RENDERSCRIPT | BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE)))
496 gem_map.flags = I915_MMAP_WC;
498 gem_map.handle = bo->handles[0].u32;
500 gem_map.size = bo->meta.total_size;
502 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_MMAP, &gem_map);
504 drv_log("DRM_IOCTL_I915_GEM_MMAP failed\n");
508 addr = (void *)(uintptr_t)gem_map.addr_ptr;
510 struct drm_i915_gem_mmap_gtt gem_map = { 0 };
512 gem_map.handle = bo->handles[0].u32;
513 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_MMAP_GTT, &gem_map);
515 drv_log("DRM_IOCTL_I915_GEM_MMAP_GTT failed\n");
519 addr = mmap(0, bo->meta.total_size, drv_get_prot(map_flags), MAP_SHARED,
520 bo->drv->fd, gem_map.offset);
523 if (addr == MAP_FAILED) {
524 drv_log("i915 GEM mmap failed\n");
528 vma->length = bo->meta.total_size;
532 static int i915_bo_invalidate(struct bo *bo, struct mapping *mapping)
535 struct drm_i915_gem_set_domain set_domain = { 0 };
537 set_domain.handle = bo->handles[0].u32;
538 if (bo->meta.tiling == I915_TILING_NONE) {
539 set_domain.read_domains = I915_GEM_DOMAIN_CPU;
540 if (mapping->vma->map_flags & BO_MAP_WRITE)
541 set_domain.write_domain = I915_GEM_DOMAIN_CPU;
543 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
544 if (mapping->vma->map_flags & BO_MAP_WRITE)
545 set_domain.write_domain = I915_GEM_DOMAIN_GTT;
548 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_SET_DOMAIN, &set_domain);
550 drv_log("DRM_IOCTL_I915_GEM_SET_DOMAIN with %d\n", ret);
557 static int i915_bo_flush(struct bo *bo, struct mapping *mapping)
559 struct i915_device *i915 = bo->drv->priv;
560 if (!i915->has_llc && bo->meta.tiling == I915_TILING_NONE)
561 i915_clflush(mapping->vma->addr, mapping->vma->length);
566 static uint32_t i915_resolve_format(struct driver *drv, uint32_t format, uint64_t use_flags)
569 case DRM_FORMAT_FLEX_IMPLEMENTATION_DEFINED:
570 /* KBL camera subsystem requires NV12. */
571 if (use_flags & (BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE))
572 return DRM_FORMAT_NV12;
573 /*HACK: See b/28671744 */
574 return DRM_FORMAT_XBGR8888;
575 case DRM_FORMAT_FLEX_YCbCr_420_888:
577 * KBL camera subsystem requires NV12. Our other use cases
579 * - Hardware video supports NV12,
580 * - USB Camera HALv3 supports NV12,
581 * - USB Camera HALv1 doesn't use this format.
582 * Moreover, NV12 is preferred for video, due to overlay
585 return DRM_FORMAT_NV12;
591 const struct backend backend_i915 = {
595 .bo_compute_metadata = i915_bo_compute_metadata,
596 .bo_create_from_metadata = i915_bo_create_from_metadata,
597 .bo_destroy = drv_gem_bo_destroy,
598 .bo_import = i915_bo_import,
599 .bo_map = i915_bo_map,
600 .bo_unmap = drv_bo_munmap,
601 .bo_invalidate = i915_bo_invalidate,
602 .bo_flush = i915_bo_flush,
603 .resolve_format = i915_resolve_format,