i915.c

   1 /*
   2  * Copyright 2014 The Chromium OS Authors. All rights reserved.
   3  * Use of this source code is governed by a BSD-style license that can be
   4  * found in the LICENSE file.
   5  */
   6
   7 #ifdef DRV_I915
   8
   9 #include <errno.h>
  10 #include <i915_drm.h>
  11 #include <stdio.h>
  12 #include <string.h>
  13 #include <sys/mman.h>
  14 #include <xf86drm.h>
  15
  16 #include "drv_priv.h"
  17 #include "helpers.h"
  18 #include "util.h"
  19 #include "i915_private.h"
  20
  21 #define I915_CACHELINE_SIZE 64
  22 #define I915_CACHELINE_MASK (I915_CACHELINE_SIZE - 1)
  23
  24 static const uint32_t render_target_formats[] = { DRM_FORMAT_ABGR8888, DRM_FORMAT_ARGB1555,
  25                                                   DRM_FORMAT_ARGB8888, DRM_FORMAT_RGB565,
  26                                                   DRM_FORMAT_XBGR2101010, DRM_FORMAT_XBGR8888,
  27                                                   DRM_FORMAT_XRGB1555, DRM_FORMAT_XRGB2101010,
  28                                                   DRM_FORMAT_XRGB8888 };
  29
  30 static const uint32_t tileable_texture_source_formats[] = { DRM_FORMAT_GR88, DRM_FORMAT_NV12,
  31                                                             DRM_FORMAT_R8, DRM_FORMAT_UYVY,
  32                                                             DRM_FORMAT_YUYV, DRM_FORMAT_YVYU, DRM_FORMAT_VYUY };
  33
  34 static const uint32_t texture_source_formats[] = { DRM_FORMAT_YVU420, DRM_FORMAT_YVU420_ANDROID };
  35
  36 struct i915_device {
  37         uint32_t gen;
  38         int32_t has_llc;
  39         uint64_t cursor_width;
  40         uint64_t cursor_height;
  41 };
  42
  43 static uint32_t i915_get_gen(int device_id)
  44 {
  45         const uint16_t gen3_ids[] = { 0x2582, 0x2592, 0x2772, 0x27A2, 0x27AE,
  46                                       0x29C2, 0x29B2, 0x29D2, 0xA001, 0xA011 };
  47         unsigned i;
  48         for (i = 0; i < ARRAY_SIZE(gen3_ids); i++)
  49                 if (gen3_ids[i] == device_id)
  50                         return 3;
  51
  52         return 4;
  53 }
  54
  55 static int i915_add_kms_item(struct driver *drv, const struct kms_item *item)
  56 {
  57         uint32_t i;
  58         struct combination *combo;
  59
  60         /*
  61          * Older hardware can't scanout Y-tiled formats. Newer devices can, and
  62          * report this functionality via format modifiers.
  63          */
  64         for (i = 0; i < drv->combos.size; i++) {
  65                 combo = &drv->combos.data[i];
  66                 if (combo->format != item->format)
  67                         continue;
  68
  69                 if (item->modifier == DRM_FORMAT_MOD_INVALID &&
  70                     combo->metadata.tiling == I915_TILING_X) {
  71                         /*
  72                          * FIXME: drv_query_kms() does not report the available modifiers
  73                          * yet, but we know that all hardware can scanout from X-tiled
  74                          * buffers, so let's add this to our combinations, except for
  75                          * cursor, which must not be tiled.
  76                          */
  77                         combo->use_flags |= item->use_flags & ~BO_USE_CURSOR;
  78                 }
  79
  80                 if (combo->metadata.modifier == item->modifier)
  81                         combo->use_flags |= item->use_flags;
  82         }
  83
  84         return 0;
  85 }
  86
  87 static int i915_add_combinations(struct driver *drv)
  88 {
  89         int ret;
  90         uint32_t i, num_items;
  91         struct kms_item *items;
  92         struct format_metadata metadata;
  93         uint64_t render_use_flags, texture_use_flags;
  94
  95         render_use_flags = BO_USE_RENDER_MASK;
  96         texture_use_flags = BO_USE_TEXTURE_MASK;
  97
  98         metadata.tiling = I915_TILING_NONE;
  99         metadata.priority = 1;
 100         metadata.modifier = DRM_FORMAT_MOD_LINEAR;
 101
 102         ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
 103                                    &metadata, render_use_flags);
 104         if (ret)
 105                 return ret;
 106
 107         ret = drv_add_combinations(drv, texture_source_formats, ARRAY_SIZE(texture_source_formats),
 108                                    &metadata, texture_use_flags);
 109         if (ret)
 110                 return ret;
 111
 112         ret = drv_add_combinations(drv, tileable_texture_source_formats,
 113                                    ARRAY_SIZE(tileable_texture_source_formats), &metadata,
 114                                    texture_use_flags);
 115         if (ret)
 116                 return ret;
 117
 118         drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
 119         drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
 120
 121         /* IPU3 camera ISP supports only NV12 output. */
 122         drv_modify_combination(drv, DRM_FORMAT_NV12, &metadata,
 123                                BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE);
 124         /*
 125          * R8 format is used for Android's HAL_PIXEL_FORMAT_BLOB and is used for JPEG snapshots
 126          * from camera.
 127          */
 128         drv_modify_combination(drv, DRM_FORMAT_R8, &metadata,
 129                                BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE);
 130
 131         render_use_flags &= ~BO_USE_RENDERSCRIPT;
 132         render_use_flags &= ~BO_USE_SW_WRITE_OFTEN;
 133         render_use_flags &= ~BO_USE_SW_READ_OFTEN;
 134         render_use_flags &= ~BO_USE_LINEAR;
 135
 136         texture_use_flags &= ~BO_USE_RENDERSCRIPT;
 137         texture_use_flags &= ~BO_USE_SW_WRITE_OFTEN;
 138         texture_use_flags &= ~BO_USE_SW_READ_OFTEN;
 139         texture_use_flags &= ~BO_USE_LINEAR;
 140
 141         metadata.tiling = I915_TILING_X;
 142         metadata.priority = 2;
 143         metadata.modifier = I915_FORMAT_MOD_X_TILED;
 144
 145         ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
 146                                    &metadata, render_use_flags);
 147         if (ret)
 148                 return ret;
 149
 150         ret = drv_add_combinations(drv, tileable_texture_source_formats,
 151                                    ARRAY_SIZE(tileable_texture_source_formats), &metadata,
 152                                    texture_use_flags);
 153         if (ret)
 154                 return ret;
 155
 156         metadata.tiling = I915_TILING_Y;
 157         metadata.priority = 3;
 158         metadata.modifier = I915_FORMAT_MOD_Y_TILED;
 159
 160         ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
 161                                    &metadata, render_use_flags);
 162         if (ret)
 163                 return ret;
 164
 165         ret = drv_add_combinations(drv, tileable_texture_source_formats,
 166                                    ARRAY_SIZE(tileable_texture_source_formats), &metadata,
 167                                    texture_use_flags);
 168         if (ret)
 169                 return ret;
 170
 171         i915_private_add_combinations(drv);
 172
 173         items = drv_query_kms(drv, &num_items);
 174         if (!items || !num_items)
 175                 return 0;
 176
 177         for (i = 0; i < num_items; i++) {
 178                 ret = i915_add_kms_item(drv, &items[i]);
 179                 if (ret) {
 180                         free(items);
 181                         return ret;
 182                 }
 183         }
 184
 185         free(items);
 186         return 0;
 187 }
 188
 189 static int i915_align_dimensions(struct bo *bo, uint32_t tiling, uint32_t *stride,
 190                                  uint32_t *aligned_height)
 191 {
 192         struct i915_device *i915 = bo->drv->priv;
 193         uint32_t horizontal_alignment = 4;
 194         uint32_t vertical_alignment = 4;
 195
 196         switch (tiling) {
 197         default:
 198         case I915_TILING_NONE:
 199                 horizontal_alignment = 64;
 200                 break;
 201
 202         case I915_TILING_X:
 203                 horizontal_alignment = 512;
 204                 vertical_alignment = 8;
 205                 break;
 206
 207         case I915_TILING_Y:
 208                 if (i915->gen == 3) {
 209                         horizontal_alignment = 512;
 210                         vertical_alignment = 8;
 211                 } else {
 212                        horizontal_alignment = 128;
 213                        vertical_alignment = 32;
 214                 }
 215                 break;
 216         }
 217
 218         /*
 219          * The alignment calculated above is based on the full size luma plane and to have chroma
 220          * planes properly aligned with subsampled formats, we need to multiply luma alignment by
 221          * subsampling factor.
 222          */
 223         switch (bo->format) {
 224         case DRM_FORMAT_YVU420_ANDROID:
 225         case DRM_FORMAT_YVU420:
 226                 horizontal_alignment *= 2;
 227         /* Fall through */
 228         case DRM_FORMAT_NV12:
 229                 vertical_alignment *= 2;
 230                 break;
 231         }
 232
 233         i915_private_align_dimensions(bo->format, &vertical_alignment);
 234
 235         *aligned_height = ALIGN(bo->height, vertical_alignment);
 236         if (i915->gen > 3) {
 237                 *stride = ALIGN(*stride, horizontal_alignment);
 238         } else {
 239                 while (*stride > horizontal_alignment)
 240                         horizontal_alignment <<= 1;
 241
 242                 *stride = horizontal_alignment;
 243         }
 244
 245         if (i915->gen <= 3 && *stride > 8192)
 246                 return -EINVAL;
 247
 248         return 0;
 249 }
 250
 251 static void i915_clflush(void *start, size_t size)
 252 {
 253         void *p = (void *)(((uintptr_t)start) & ~I915_CACHELINE_MASK);
 254         void *end = (void *)((uintptr_t)start + size);
 255
 256         __builtin_ia32_mfence();
 257         while (p < end) {
 258                 __builtin_ia32_clflush(p);
 259                 p = (void *)((uintptr_t)p + I915_CACHELINE_SIZE);
 260         }
 261 }
 262
 263 static int i915_init(struct driver *drv)
 264 {
 265         int ret;
 266         int device_id;
 267         struct i915_device *i915;
 268         drm_i915_getparam_t get_param;
 269
 270         i915 = calloc(1, sizeof(*i915));
 271         if (!i915)
 272                 return -ENOMEM;
 273
 274         memset(&get_param, 0, sizeof(get_param));
 275         get_param.param = I915_PARAM_CHIPSET_ID;
 276         get_param.value = &device_id;
 277         ret = drmIoctl(drv->fd, DRM_IOCTL_I915_GETPARAM, &get_param);
 278         if (ret) {
 279                 fprintf(stderr, "drv: Failed to get I915_PARAM_CHIPSET_ID\n");
 280                 free(i915);
 281                 return -EINVAL;
 282         }
 283
 284         i915->gen = i915_get_gen(device_id);
 285
 286         memset(&get_param, 0, sizeof(get_param));
 287         get_param.param = I915_PARAM_HAS_LLC;
 288         get_param.value = &i915->has_llc;
 289         ret = drmIoctl(drv->fd, DRM_IOCTL_I915_GETPARAM, &get_param);
 290         if (ret) {
 291                 fprintf(stderr, "drv: Failed to get I915_PARAM_HAS_LLC\n");
 292                 free(i915);
 293                 return -EINVAL;
 294         }
 295
 296         drv->priv = i915;
 297
 298         i915_private_init(drv, &i915->cursor_width, &i915->cursor_height);
 299
 300         return i915_add_combinations(drv);
 301 }
 302
 303 static int i915_bo_create_for_modifier(struct bo *bo, uint32_t width, uint32_t height,
 304                                        uint32_t format, uint64_t modifier)
 305 {
 306         int ret;
 307         size_t plane;
 308         uint32_t stride;
 309         struct drm_i915_gem_create gem_create;
 310         struct drm_i915_gem_set_tiling gem_set_tiling;
 311         struct i915_device *i915_dev = (struct i915_device *)bo->drv->priv;
 312
 313         switch (modifier) {
 314         case DRM_FORMAT_MOD_LINEAR:
 315                 bo->tiling = I915_TILING_NONE;
 316                 break;
 317         case I915_FORMAT_MOD_X_TILED:
 318                 bo->tiling = I915_TILING_X;
 319                 break;
 320         case I915_FORMAT_MOD_Y_TILED:
 321                 bo->tiling = I915_TILING_Y;
 322                 break;
 323         }
 324
 325         stride = drv_stride_from_format(format, width, 0);
 326
 327         /*
 328          * Align cursor width and height to values expected by Intel
 329          * HW.
 330          */
 331         if (bo->use_flags & BO_USE_CURSOR) {
 332             width = ALIGN(width, i915_dev->cursor_width);
 333             height = ALIGN(height, i915_dev->cursor_height);
 334             stride = drv_stride_from_format(format, width, 0);
 335         } else {
 336             ret = i915_align_dimensions(bo, bo->tiling, &stride, &height);
 337             if (ret)
 338                 return ret;
 339         }
 340
 341         /*
 342          * HAL_PIXEL_FORMAT_YV12 requires the buffer height not be aligned, but we need to keep
 343          * total size as with aligned height to ensure enough padding space after each plane to
 344          * satisfy GPU alignment requirements.
 345          *
 346          * We do it by first calling drv_bo_from_format() with aligned height and
 347          * DRM_FORMAT_YVU420, which allows height alignment, saving the total size it calculates
 348          * and then calling it again with requested parameters.
 349          *
 350          * This relies on the fact that i965 driver uses separate surfaces for each plane and
 351          * contents of padding bytes is not affected, as it is only used to satisfy GPU cache
 352          * requests.
 353          *
 354          * This is enforced by Mesa in src/intel/isl/isl_gen8.c, inside
 355          * isl_gen8_choose_image_alignment_el(), which is used for GEN9 and GEN8.
 356          */
 357         if (format == DRM_FORMAT_YVU420_ANDROID) {
 358                 uint32_t unaligned_height = bo->height;
 359                 size_t total_size;
 360
 361                 drv_bo_from_format(bo, stride, height, DRM_FORMAT_YVU420);
 362                 total_size = bo->total_size;
 363                 drv_bo_from_format(bo, stride, unaligned_height, format);
 364                 bo->total_size = total_size;
 365         } else {
 366                 drv_bo_from_format(bo, stride, height, format);
 367         }
 368
 369         /*
 370          * Quoting Mesa ISL library:
 371          *
 372          *    - For linear surfaces, additional padding of 64 bytes is required at
 373          *      the bottom of the surface. This is in addition to the padding
 374          *      required above.
 375          */
 376         if (bo->tiling == I915_TILING_NONE)
 377                 bo->total_size += 64;
 378
 379         /*
 380          * Ensure we pass aligned width/height.
 381          */
 382         bo->width = width;
 383         bo->height = height;
 384
 385         memset(&gem_create, 0, sizeof(gem_create));
 386         gem_create.size = bo->total_size;
 387
 388         ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_CREATE, &gem_create);
 389         if (ret) {
 390                 fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_CREATE failed (size=%llu)\n",
 391                         gem_create.size);
 392                 return ret;
 393         }
 394
 395         for (plane = 0; plane < bo->num_planes; plane++)
 396                 bo->handles[plane].u32 = gem_create.handle;
 397
 398         memset(&gem_set_tiling, 0, sizeof(gem_set_tiling));
 399         gem_set_tiling.handle = bo->handles[0].u32;
 400         gem_set_tiling.tiling_mode = bo->tiling;
 401         gem_set_tiling.stride = bo->strides[0];
 402
 403         ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_SET_TILING, &gem_set_tiling);
 404         if (ret) {
 405                 struct drm_gem_close gem_close;
 406                 memset(&gem_close, 0, sizeof(gem_close));
 407                 gem_close.handle = bo->handles[0].u32;
 408                 drmIoctl(bo->drv->fd, DRM_IOCTL_GEM_CLOSE, &gem_close);
 409
 410                 fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_SET_TILING failed with %d", errno);
 411                 return -errno;
 412         }
 413
 414         return 0;
 415 }
 416
 417 static int i915_bo_create(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
 418                           uint64_t use_flags)
 419 {
 420         struct combination *combo;
 421
 422         combo = drv_get_combination(bo->drv, format, use_flags);
 423         if (!combo)
 424                 return -EINVAL;
 425
 426         return i915_bo_create_for_modifier(bo, width, height, format, combo->metadata.modifier);
 427 }
 428
 429 static int i915_bo_create_with_modifiers(struct bo *bo, uint32_t width, uint32_t height,
 430                                          uint32_t format, const uint64_t *modifiers, uint32_t count)
 431 {
 432         static const uint64_t modifier_order[] = {
 433                 I915_FORMAT_MOD_Y_TILED, I915_FORMAT_MOD_X_TILED, DRM_FORMAT_MOD_LINEAR,
 434         };
 435         uint64_t modifier;
 436
 437         modifier = drv_pick_modifier(modifiers, count, modifier_order, ARRAY_SIZE(modifier_order));
 438
 439         bo->format_modifiers[0] = modifier;
 440
 441         return i915_bo_create_for_modifier(bo, width, height, format, modifier);
 442 }
 443
 444 static void i915_close(struct driver *drv)
 445 {
 446         free(drv->priv);
 447         drv->priv = NULL;
 448 }
 449
 450 static int i915_bo_import(struct bo *bo, struct drv_import_fd_data *data)
 451 {
 452         int ret;
 453         struct drm_i915_gem_get_tiling gem_get_tiling;
 454
 455         ret = drv_prime_bo_import(bo, data);
 456         if (ret)
 457                 return ret;
 458
 459         /* TODO(gsingh): export modifiers and get rid of backdoor tiling. */
 460         memset(&gem_get_tiling, 0, sizeof(gem_get_tiling));
 461         gem_get_tiling.handle = bo->handles[0].u32;
 462
 463         ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_GET_TILING, &gem_get_tiling);
 464         if (ret) {
 465                 drv_gem_bo_destroy(bo);
 466                 fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_GET_TILING failed.");
 467                 return ret;
 468         }
 469
 470         bo->tiling = gem_get_tiling.tiling_mode;
 471         return 0;
 472 }
 473
 474 static void *i915_bo_map(struct bo *bo, struct map_info *data, size_t plane, uint32_t map_flags)
 475 {
 476         int ret;
 477         void *addr;
 478
 479         if (bo->tiling == I915_TILING_NONE) {
 480                 struct drm_i915_gem_mmap gem_map;
 481                 memset(&gem_map, 0, sizeof(gem_map));
 482
 483                 if ((bo->use_flags & BO_USE_SCANOUT) && !(bo->use_flags & BO_USE_RENDERSCRIPT))
 484                         gem_map.flags = I915_MMAP_WC;
 485
 486                 gem_map.handle = bo->handles[0].u32;
 487                 gem_map.offset = 0;
 488                 gem_map.size = bo->total_size;
 489
 490                 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_MMAP, &gem_map);
 491                 if (ret) {
 492                         fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_MMAP failed\n");
 493                         return MAP_FAILED;
 494                 }
 495
 496                 addr = (void *)(uintptr_t)gem_map.addr_ptr;
 497         } else {
 498                 struct drm_i915_gem_mmap_gtt gem_map;
 499                 memset(&gem_map, 0, sizeof(gem_map));
 500
 501                 gem_map.handle = bo->handles[0].u32;
 502
 503                 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_MMAP_GTT, &gem_map);
 504                 if (ret) {
 505                         fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_MMAP_GTT failed\n");
 506                         return MAP_FAILED;
 507                 }
 508
 509                 addr = mmap(0, bo->total_size, drv_get_prot(map_flags), MAP_SHARED, bo->drv->fd,
 510                             gem_map.offset);
 511         }
 512
 513         if (addr == MAP_FAILED) {
 514                 fprintf(stderr, "drv: i915 GEM mmap failed\n");
 515                 return addr;
 516         }
 517
 518         data->length = bo->total_size;
 519         return addr;
 520 }
 521
 522 static int i915_bo_invalidate(struct bo *bo, struct map_info *data)
 523 {
 524         int ret;
 525         struct drm_i915_gem_set_domain set_domain;
 526
 527         memset(&set_domain, 0, sizeof(set_domain));
 528         set_domain.handle = bo->handles[0].u32;
 529         if (bo->tiling == I915_TILING_NONE) {
 530                 set_domain.read_domains = I915_GEM_DOMAIN_CPU;
 531                 if (data->map_flags & BO_MAP_WRITE)
 532                         set_domain.write_domain = I915_GEM_DOMAIN_CPU;
 533         } else {
 534                 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
 535                 if (data->map_flags & BO_MAP_WRITE)
 536                         set_domain.write_domain = I915_GEM_DOMAIN_GTT;
 537         }
 538
 539         ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_SET_DOMAIN, &set_domain);
 540         if (ret) {
 541                 fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_SET_DOMAIN with %d\n", ret);
 542                 return ret;
 543         }
 544
 545         return 0;
 546 }
 547
 548 static int i915_bo_flush(struct bo *bo, struct map_info *data)
 549 {
 550         struct i915_device *i915 = bo->drv->priv;
 551         if (!i915->has_llc && bo->tiling == I915_TILING_NONE)
 552                 i915_clflush(data->addr, data->length);
 553
 554         return 0;
 555 }
 556
 557 static uint32_t i915_resolve_format(uint32_t format, uint64_t use_flags)
 558 {
 559         uint32_t resolved_format;
 560         if (i915_private_resolve_format(format, use_flags, &resolved_format)) {
 561             return resolved_format;
 562         }
 563
 564         switch (format) {
 565         case DRM_FORMAT_FLEX_IMPLEMENTATION_DEFINED:
 566                 /* KBL camera subsystem requires NV12. */
 567                 if (use_flags & (BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE))
 568                         return DRM_FORMAT_NV12;
 569                 /*HACK: See b/28671744 */
 570                 return DRM_FORMAT_XBGR8888;
 571         case DRM_FORMAT_FLEX_YCbCr_420_888:
 572                 /* KBL camera subsystem requires NV12. */
 573                 if (use_flags & (BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE))
 574                         return DRM_FORMAT_NV12;
 575                 return DRM_FORMAT_YVU420;
 576         default:
 577                 return format;
 578         }
 579 }
 580
 581 struct backend backend_i915 = {
 582         .name = "i915",
 583         .init = i915_init,
 584         .close = i915_close,
 585         .bo_create = i915_bo_create,
 586         .bo_create_with_modifiers = i915_bo_create_with_modifiers,
 587         .bo_destroy = drv_gem_bo_destroy,
 588         .bo_import = i915_bo_import,
 589         .bo_map = i915_bo_map,
 590         .bo_unmap = drv_bo_munmap,
 591         .bo_invalidate = i915_bo_invalidate,
 592         .bo_flush = i915_bo_flush,
 593         .resolve_format = i915_resolve_format,
 594 };
 595
 596 #endif