2 * Copyright 2014 The Chromium OS Authors. All rights reserved.
3 * Use of this source code is governed by a BSD-style license that can be
4 * found in the LICENSE file.
19 #include "external/i915_drm.h"
23 #define I915_CACHELINE_SIZE 64
24 #define I915_CACHELINE_MASK (I915_CACHELINE_SIZE - 1)
26 static const uint32_t scanout_render_formats[] = { DRM_FORMAT_ABGR2101010, DRM_FORMAT_ABGR8888,
27 DRM_FORMAT_ARGB2101010, DRM_FORMAT_ARGB8888,
28 DRM_FORMAT_RGB565, DRM_FORMAT_XBGR2101010,
29 DRM_FORMAT_XBGR8888, DRM_FORMAT_XRGB2101010,
30 DRM_FORMAT_XRGB8888 };
32 static const uint32_t render_formats[] = { DRM_FORMAT_ABGR16161616F };
34 static const uint32_t texture_only_formats[] = { DRM_FORMAT_R8, DRM_FORMAT_NV12, DRM_FORMAT_P010,
35 DRM_FORMAT_YVU420, DRM_FORMAT_YVU420_ANDROID };
37 static const uint64_t gen_modifier_order[] = { I915_FORMAT_MOD_Y_TILED, I915_FORMAT_MOD_X_TILED,
38 DRM_FORMAT_MOD_LINEAR };
40 static const uint64_t gen11_modifier_order[] = { I915_FORMAT_MOD_Y_TILED_CCS,
41 I915_FORMAT_MOD_Y_TILED, I915_FORMAT_MOD_X_TILED,
42 DRM_FORMAT_MOD_LINEAR };
44 struct modifier_support_t {
45 const uint64_t *order;
52 int32_t has_hw_protection;
53 struct modifier_support_t modifier;
56 static uint32_t i915_get_gen(int device_id)
58 const uint16_t gen3_ids[] = { 0x2582, 0x2592, 0x2772, 0x27A2, 0x27AE,
59 0x29C2, 0x29B2, 0x29D2, 0xA001, 0xA011 };
60 const uint16_t gen11_ids[] = { 0x4E71, 0x4E61, 0x4E51, 0x4E55, 0x4E57 };
61 const uint16_t gen12_ids[] = { 0x9A40, 0x9A49, 0x9A59, 0x9A60, 0x9A68, 0x9A70,
62 0x9A78, 0x9AC0, 0x9AC9, 0x9AD9, 0x9AF8 };
64 for (i = 0; i < ARRAY_SIZE(gen3_ids); i++)
65 if (gen3_ids[i] == device_id)
68 for (i = 0; i < ARRAY_SIZE(gen11_ids); i++)
69 if (gen11_ids[i] == device_id)
73 for (i = 0; i < ARRAY_SIZE(gen12_ids); i++)
74 if (gen12_ids[i] == device_id)
80 static void i915_get_modifier_order(struct i915_device *i915)
82 if (i915->gen == 11) {
83 i915->modifier.order = gen11_modifier_order;
84 i915->modifier.count = ARRAY_SIZE(gen11_modifier_order);
86 i915->modifier.order = gen_modifier_order;
87 i915->modifier.count = ARRAY_SIZE(gen_modifier_order);
91 static uint64_t unset_flags(uint64_t current_flags, uint64_t mask)
93 uint64_t value = current_flags & ~mask;
97 static int i915_add_combinations(struct driver *drv)
99 struct format_metadata metadata;
100 uint64_t render, scanout_and_render, texture_only, hw_protected;
101 struct i915_device *i915 = drv->priv;
103 scanout_and_render = BO_USE_RENDER_MASK | BO_USE_SCANOUT;
104 render = BO_USE_RENDER_MASK;
105 texture_only = BO_USE_TEXTURE_MASK;
106 // HW protected buffers also need to be scanned out.
107 hw_protected = i915->has_hw_protection ? (BO_USE_PROTECTED | BO_USE_SCANOUT) : 0;
109 uint64_t linear_mask =
110 BO_USE_RENDERSCRIPT | BO_USE_LINEAR | BO_USE_SW_READ_OFTEN | BO_USE_SW_WRITE_OFTEN;
112 metadata.tiling = I915_TILING_NONE;
113 metadata.priority = 1;
114 metadata.modifier = DRM_FORMAT_MOD_LINEAR;
116 drv_add_combinations(drv, scanout_render_formats, ARRAY_SIZE(scanout_render_formats),
117 &metadata, scanout_and_render);
119 drv_add_combinations(drv, render_formats, ARRAY_SIZE(render_formats), &metadata, render);
121 drv_add_combinations(drv, texture_only_formats, ARRAY_SIZE(texture_only_formats), &metadata,
124 drv_modify_linear_combinations(drv);
126 /* NV12 format for camera, display, decoding and encoding. */
127 /* IPU3 camera ISP supports only NV12 output. */
128 drv_modify_combination(drv, DRM_FORMAT_NV12, &metadata,
129 BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE | BO_USE_SCANOUT |
130 BO_USE_HW_VIDEO_DECODER | BO_USE_HW_VIDEO_ENCODER |
133 /* Android CTS tests require this. */
134 drv_add_combination(drv, DRM_FORMAT_BGR888, &metadata, BO_USE_SW_MASK);
137 * R8 format is used for Android's HAL_PIXEL_FORMAT_BLOB and is used for JPEG snapshots
138 * from camera and input/output from hardware decoder/encoder.
140 drv_modify_combination(drv, DRM_FORMAT_R8, &metadata,
141 BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE | BO_USE_HW_VIDEO_DECODER |
142 BO_USE_HW_VIDEO_ENCODER);
144 render = unset_flags(render, linear_mask);
145 scanout_and_render = unset_flags(scanout_and_render, linear_mask);
147 metadata.tiling = I915_TILING_X;
148 metadata.priority = 2;
149 metadata.modifier = I915_FORMAT_MOD_X_TILED;
151 drv_add_combinations(drv, render_formats, ARRAY_SIZE(render_formats), &metadata, render);
152 drv_add_combinations(drv, scanout_render_formats, ARRAY_SIZE(scanout_render_formats),
153 &metadata, scanout_and_render);
155 /* TODO: Y tiling does not seem to work for framebuffers */
156 render_use_flags &= ~BO_USE_FRAMEBUFFER;
158 metadata.tiling = I915_TILING_Y;
159 metadata.priority = 3;
160 metadata.modifier = I915_FORMAT_MOD_Y_TILED;
163 unset_flags(scanout_and_render, BO_USE_SW_READ_RARELY | BO_USE_SW_WRITE_RARELY);
164 /* Support y-tiled NV12 and P010 for libva */
165 #ifdef I915_SCANOUT_Y_TILED
166 uint64_t nv12_usage =
167 BO_USE_TEXTURE | BO_USE_HW_VIDEO_DECODER | BO_USE_SCANOUT | hw_protected;
168 uint64_t p010_usage = BO_USE_TEXTURE | BO_USE_HW_VIDEO_DECODER | hw_protected;
170 uint64_t nv12_usage = BO_USE_TEXTURE | BO_USE_HW_VIDEO_DECODER;
171 uint64_t p010_usage = nv12_usage;
173 drv_add_combination(drv, DRM_FORMAT_NV12, &metadata, nv12_usage);
174 drv_add_combination(drv, DRM_FORMAT_P010, &metadata, p010_usage);
176 scanout_and_render = unset_flags(scanout_and_render, BO_USE_SCANOUT);
178 drv_add_combinations(drv, render_formats, ARRAY_SIZE(render_formats), &metadata, render);
179 drv_add_combinations(drv, scanout_render_formats, ARRAY_SIZE(scanout_render_formats),
180 &metadata, scanout_and_render);
184 static int i915_align_dimensions(struct bo *bo, uint32_t tiling, uint32_t *stride,
185 uint32_t *aligned_height)
187 struct i915_device *i915 = bo->drv->priv;
188 uint32_t horizontal_alignment;
189 uint32_t vertical_alignment;
193 case I915_TILING_NONE:
195 * The Intel GPU doesn't need any alignment in linear mode,
196 * but libva requires the allocation stride to be aligned to
197 * 16 bytes and height to 4 rows. Further, we round up the
198 * horizontal alignment so that row start on a cache line (64
201 #ifdef LINEAR_ALIGN_256
203 * If we want to import these buffers to amdgpu they need to
204 * their match LINEAR_ALIGNED requirement of 256 byte alignement.
206 horizontal_alignment = 256;
208 horizontal_alignment = 64;
210 vertical_alignment = 4;
214 horizontal_alignment = 512;
215 vertical_alignment = 8;
219 if (i915->gen == 3) {
220 horizontal_alignment = 512;
221 vertical_alignment = 8;
223 horizontal_alignment = 128;
224 vertical_alignment = 32;
229 *aligned_height = ALIGN(*aligned_height, vertical_alignment);
231 *stride = ALIGN(*stride, horizontal_alignment);
233 while (*stride > horizontal_alignment)
234 horizontal_alignment <<= 1;
236 *stride = horizontal_alignment;
239 if (i915->gen <= 3 && *stride > 8192)
245 static void i915_clflush(void *start, size_t size)
247 void *p = (void *)(((uintptr_t)start) & ~I915_CACHELINE_MASK);
248 void *end = (void *)((uintptr_t)start + size);
250 __builtin_ia32_mfence();
252 __builtin_ia32_clflush(p);
253 p = (void *)((uintptr_t)p + I915_CACHELINE_SIZE);
257 static int i915_init(struct driver *drv)
261 struct i915_device *i915;
262 drm_i915_getparam_t get_param = { 0 };
264 i915 = calloc(1, sizeof(*i915));
268 get_param.param = I915_PARAM_CHIPSET_ID;
269 get_param.value = &device_id;
270 ret = drmIoctl(drv->fd, DRM_IOCTL_I915_GETPARAM, &get_param);
272 drv_log("Failed to get I915_PARAM_CHIPSET_ID\n");
277 i915->gen = i915_get_gen(device_id);
278 i915_get_modifier_order(i915);
280 memset(&get_param, 0, sizeof(get_param));
281 get_param.param = I915_PARAM_HAS_LLC;
282 get_param.value = &i915->has_llc;
283 ret = drmIoctl(drv->fd, DRM_IOCTL_I915_GETPARAM, &get_param);
285 drv_log("Failed to get I915_PARAM_HAS_LLC\n");
291 i915->has_hw_protection = 1;
294 return i915_add_combinations(drv);
297 static int i915_bo_from_format(struct bo *bo, uint32_t width, uint32_t height, uint32_t format)
304 pagesize = getpagesize();
305 for (plane = 0; plane < drv_num_planes_from_format(format); plane++) {
306 uint32_t stride = drv_stride_from_format(format, width, plane);
307 uint32_t plane_height = drv_height_from_format(format, height, plane);
309 if (bo->meta.tiling != I915_TILING_NONE)
310 assert(IS_ALIGNED(offset, pagesize));
312 ret = i915_align_dimensions(bo, bo->meta.tiling, &stride, &plane_height);
316 bo->meta.strides[plane] = stride;
317 bo->meta.sizes[plane] = stride * plane_height;
318 bo->meta.offsets[plane] = offset;
319 offset += bo->meta.sizes[plane];
322 bo->meta.total_size = ALIGN(offset, pagesize);
327 static int i915_bo_compute_metadata(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
328 uint64_t use_flags, const uint64_t *modifiers, uint32_t count)
331 struct i915_device *i915 = bo->drv->priv;
332 bool huge_bo = (i915->gen < 11) && (width > 4096);
336 drv_pick_modifier(modifiers, count, i915->modifier.order, i915->modifier.count);
338 struct combination *combo = drv_get_combination(bo->drv, format, use_flags);
341 modifier = combo->metadata.modifier;
345 * i915 only supports linear/x-tiled above 4096 wide on Gen9/Gen10 GPU.
346 * VAAPI decode in NV12 Y tiled format so skip modifier change for NV12/P010 huge bo.
348 if (huge_bo && format != DRM_FORMAT_NV12 && format != DRM_FORMAT_P010 &&
349 modifier != I915_FORMAT_MOD_X_TILED && modifier != DRM_FORMAT_MOD_LINEAR) {
351 for (i = 0; modifiers && i < count; i++) {
352 if (modifiers[i] == I915_FORMAT_MOD_X_TILED)
356 modifier = DRM_FORMAT_MOD_LINEAR;
358 modifier = I915_FORMAT_MOD_X_TILED;
362 * Skip I915_FORMAT_MOD_Y_TILED_CCS modifier if compression is disabled
363 * Pick y tiled modifier if it has been passed in, otherwise use linear
365 if (!bo->drv->compression && modifier == I915_FORMAT_MOD_Y_TILED_CCS) {
367 for (i = 0; modifiers && i < count; i++) {
368 if (modifiers[i] == I915_FORMAT_MOD_Y_TILED)
372 modifier = DRM_FORMAT_MOD_LINEAR;
374 modifier = I915_FORMAT_MOD_Y_TILED;
378 case DRM_FORMAT_MOD_LINEAR:
379 bo->meta.tiling = I915_TILING_NONE;
381 case I915_FORMAT_MOD_X_TILED:
382 bo->meta.tiling = I915_TILING_X;
384 case I915_FORMAT_MOD_Y_TILED:
385 case I915_FORMAT_MOD_Y_TILED_CCS:
386 bo->meta.tiling = I915_TILING_Y;
390 bo->meta.format_modifiers[0] = modifier;
392 if (format == DRM_FORMAT_YVU420_ANDROID) {
394 * We only need to be able to use this as a linear texture,
395 * which doesn't put any HW restrictions on how we lay it
396 * out. The Android format does require the stride to be a
397 * multiple of 16 and expects the Cr and Cb stride to be
398 * ALIGN(Y_stride / 2, 16), which we can make happen by
399 * aligning to 32 bytes here.
401 uint32_t stride = ALIGN(width, 32);
402 drv_bo_from_format(bo, stride, height, format);
403 } else if (modifier == I915_FORMAT_MOD_Y_TILED_CCS) {
405 * For compressed surfaces, we need a color control surface
406 * (CCS). Color compression is only supported for Y tiled
407 * surfaces, and for each 32x16 tiles in the main surface we
408 * need a tile in the control surface. Y tiles are 128 bytes
409 * wide and 32 lines tall and we use that to first compute the
410 * width and height in tiles of the main surface. stride and
411 * height are already multiples of 128 and 32, respectively:
413 uint32_t stride = drv_stride_from_format(format, width, 0);
414 uint32_t width_in_tiles = DIV_ROUND_UP(stride, 128);
415 uint32_t height_in_tiles = DIV_ROUND_UP(height, 32);
416 uint32_t size = width_in_tiles * height_in_tiles * 4096;
419 bo->meta.strides[0] = width_in_tiles * 128;
420 bo->meta.sizes[0] = size;
421 bo->meta.offsets[0] = offset;
425 * Now, compute the width and height in tiles of the control
426 * surface by dividing and rounding up.
428 uint32_t ccs_width_in_tiles = DIV_ROUND_UP(width_in_tiles, 32);
429 uint32_t ccs_height_in_tiles = DIV_ROUND_UP(height_in_tiles, 16);
430 uint32_t ccs_size = ccs_width_in_tiles * ccs_height_in_tiles * 4096;
433 * With stride and height aligned to y tiles, offset is
434 * already a multiple of 4096, which is the required alignment
437 bo->meta.strides[1] = ccs_width_in_tiles * 128;
438 bo->meta.sizes[1] = ccs_size;
439 bo->meta.offsets[1] = offset;
442 bo->meta.num_planes = 2;
443 bo->meta.total_size = offset;
445 i915_bo_from_format(bo, width, height, format);
450 static int i915_bo_create_from_metadata(struct bo *bo)
455 struct drm_i915_gem_set_tiling gem_set_tiling = { 0 };
456 struct i915_device *i915 = bo->drv->priv;
458 if (i915->has_hw_protection && (bo->meta.use_flags & BO_USE_PROTECTED)) {
459 struct drm_i915_gem_object_param protected_param = {
460 .param = I915_OBJECT_PARAM | I915_PARAM_PROTECTED_CONTENT,
464 struct drm_i915_gem_create_ext_setparam setparam_protected = {
465 .base = { .name = I915_GEM_CREATE_EXT_SETPARAM },
466 .param = protected_param,
469 struct drm_i915_gem_create_ext create_ext = {
470 .size = bo->meta.total_size,
471 .extensions = (uintptr_t)&setparam_protected,
474 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_CREATE_EXT, &create_ext);
476 drv_log("DRM_IOCTL_I915_GEM_CREATE_EXT failed (size=%llu)\n",
481 gem_handle = create_ext.handle;
483 struct drm_i915_gem_create gem_create = { 0 };
484 gem_create.size = bo->meta.total_size;
485 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_CREATE, &gem_create);
487 drv_log("DRM_IOCTL_I915_GEM_CREATE failed (size=%llu)\n", gem_create.size);
491 gem_handle = gem_create.handle;
494 for (plane = 0; plane < bo->meta.num_planes; plane++)
495 bo->handles[plane].u32 = gem_handle;
497 gem_set_tiling.handle = bo->handles[0].u32;
498 gem_set_tiling.tiling_mode = bo->meta.tiling;
499 gem_set_tiling.stride = bo->meta.strides[0];
501 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_SET_TILING, &gem_set_tiling);
503 struct drm_gem_close gem_close = { 0 };
504 gem_close.handle = bo->handles[0].u32;
505 drmIoctl(bo->drv->fd, DRM_IOCTL_GEM_CLOSE, &gem_close);
507 drv_log("DRM_IOCTL_I915_GEM_SET_TILING failed with %d\n", errno);
514 static void i915_close(struct driver *drv)
520 static int i915_bo_import(struct bo *bo, struct drv_import_fd_data *data)
523 struct drm_i915_gem_get_tiling gem_get_tiling = { 0 };
525 ret = drv_prime_bo_import(bo, data);
529 /* TODO(gsingh): export modifiers and get rid of backdoor tiling. */
530 gem_get_tiling.handle = bo->handles[0].u32;
532 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_GET_TILING, &gem_get_tiling);
534 drv_gem_bo_destroy(bo);
535 drv_log("DRM_IOCTL_I915_GEM_GET_TILING failed.\n");
539 bo->meta.tiling = gem_get_tiling.tiling_mode;
543 static void *i915_bo_map(struct bo *bo, struct vma *vma, size_t plane, uint32_t map_flags)
546 void *addr = MAP_FAILED;
548 if (bo->meta.format_modifiers[0] == I915_FORMAT_MOD_Y_TILED_CCS)
551 if (bo->meta.tiling == I915_TILING_NONE) {
552 struct drm_i915_gem_mmap gem_map = { 0 };
553 /* TODO(b/118799155): We don't seem to have a good way to
554 * detect the use cases for which WC mapping is really needed.
555 * The current heuristic seems overly coarse and may be slowing
556 * down some other use cases unnecessarily.
558 * For now, care must be taken not to use WC mappings for
559 * Renderscript and camera use cases, as they're
560 * performance-sensitive. */
561 if ((bo->meta.use_flags & BO_USE_SCANOUT) &&
562 !(bo->meta.use_flags &
563 (BO_USE_RENDERSCRIPT | BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE)))
564 gem_map.flags = I915_MMAP_WC;
566 gem_map.handle = bo->handles[0].u32;
568 gem_map.size = bo->meta.total_size;
570 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_MMAP, &gem_map);
571 /* DRM_IOCTL_I915_GEM_MMAP mmaps the underlying shm
572 * file and returns a user space address directly, ie,
573 * doesn't go through mmap. If we try that on a
574 * dma-buf that doesn't have a shm file, i915.ko
575 * returns ENXIO. Fall through to
576 * DRM_IOCTL_I915_GEM_MMAP_GTT in that case, which
577 * will mmap on the drm fd instead. */
579 addr = (void *)(uintptr_t)gem_map.addr_ptr;
582 if (addr == MAP_FAILED) {
583 struct drm_i915_gem_mmap_gtt gem_map = { 0 };
585 gem_map.handle = bo->handles[0].u32;
586 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_MMAP_GTT, &gem_map);
588 drv_log("DRM_IOCTL_I915_GEM_MMAP_GTT failed\n");
592 addr = mmap(0, bo->meta.total_size, drv_get_prot(map_flags), MAP_SHARED,
593 bo->drv->fd, gem_map.offset);
596 if (addr == MAP_FAILED) {
597 drv_log("i915 GEM mmap failed\n");
601 vma->length = bo->meta.total_size;
605 static int i915_bo_invalidate(struct bo *bo, struct mapping *mapping)
608 struct drm_i915_gem_set_domain set_domain = { 0 };
610 set_domain.handle = bo->handles[0].u32;
611 if (bo->meta.tiling == I915_TILING_NONE) {
612 set_domain.read_domains = I915_GEM_DOMAIN_CPU;
613 if (mapping->vma->map_flags & BO_MAP_WRITE)
614 set_domain.write_domain = I915_GEM_DOMAIN_CPU;
616 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
617 if (mapping->vma->map_flags & BO_MAP_WRITE)
618 set_domain.write_domain = I915_GEM_DOMAIN_GTT;
621 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_SET_DOMAIN, &set_domain);
623 drv_log("DRM_IOCTL_I915_GEM_SET_DOMAIN with %d\n", ret);
630 static int i915_bo_flush(struct bo *bo, struct mapping *mapping)
632 struct i915_device *i915 = bo->drv->priv;
633 if (!i915->has_llc && bo->meta.tiling == I915_TILING_NONE)
634 i915_clflush(mapping->vma->addr, mapping->vma->length);
639 static uint32_t i915_resolve_format(struct driver *drv, uint32_t format, uint64_t use_flags)
642 case DRM_FORMAT_FLEX_IMPLEMENTATION_DEFINED:
643 /* KBL camera subsystem requires NV12. */
644 if (use_flags & (BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE))
645 return DRM_FORMAT_NV12;
646 /*HACK: See b/28671744 */
647 return DRM_FORMAT_XBGR8888;
648 case DRM_FORMAT_FLEX_YCbCr_420_888:
650 * KBL camera subsystem requires NV12. Our other use cases
652 * - Hardware video supports NV12,
653 * - USB Camera HALv3 supports NV12,
654 * - USB Camera HALv1 doesn't use this format.
655 * Moreover, NV12 is preferred for video, due to overlay
658 return DRM_FORMAT_NV12;
664 const struct backend backend_i915 = {
668 .bo_compute_metadata = i915_bo_compute_metadata,
669 .bo_create_from_metadata = i915_bo_create_from_metadata,
670 .bo_destroy = drv_gem_bo_destroy,
671 .bo_import = i915_bo_import,
672 .bo_map = i915_bo_map,
673 .bo_unmap = drv_bo_munmap,
674 .bo_invalidate = i915_bo_invalidate,
675 .bo_flush = i915_bo_flush,
676 .resolve_format = i915_resolve_format,