2 * Copyright 2014 The Chromium OS Authors. All rights reserved.
3 * Use of this source code is governed by a BSD-style license that can be
4 * found in the LICENSE file.
20 #define I915_CACHELINE_SIZE 64
21 #define I915_CACHELINE_MASK (I915_CACHELINE_SIZE - 1)
23 static const uint32_t render_target_formats[] = { DRM_FORMAT_ABGR8888, DRM_FORMAT_ARGB1555,
24 DRM_FORMAT_ARGB8888, DRM_FORMAT_RGB565,
25 DRM_FORMAT_XBGR2101010, DRM_FORMAT_XBGR8888,
26 DRM_FORMAT_XRGB1555, DRM_FORMAT_XRGB2101010,
27 DRM_FORMAT_XRGB8888 };
29 static const uint32_t tileable_texture_source_formats[] = { DRM_FORMAT_GR88, DRM_FORMAT_NV12,
30 DRM_FORMAT_R8, DRM_FORMAT_UYVY,
33 static const uint32_t texture_source_formats[] = { DRM_FORMAT_YVU420, DRM_FORMAT_YVU420_ANDROID };
40 static uint32_t i915_get_gen(int device_id)
42 const uint16_t gen3_ids[] = { 0x2582, 0x2592, 0x2772, 0x27A2, 0x27AE,
43 0x29C2, 0x29B2, 0x29D2, 0xA001, 0xA011 };
45 for (i = 0; i < ARRAY_SIZE(gen3_ids); i++)
46 if (gen3_ids[i] == device_id)
52 static int i915_add_kms_item(struct driver *drv, const struct kms_item *item)
55 struct combination *combo;
58 * Older hardware can't scanout Y-tiled formats. Newer devices can, and
59 * report this functionality via format modifiers.
61 for (i = 0; i < drv->combos.size; i++) {
62 combo = &drv->combos.data[i];
63 if (combo->format != item->format)
66 if (item->modifier == DRM_FORMAT_MOD_INVALID &&
67 combo->metadata.tiling == I915_TILING_X) {
69 * FIXME: drv_query_kms() does not report the available modifiers
70 * yet, but we know that all hardware can scanout from X-tiled
71 * buffers, so let's add this to our combinations, except for
72 * cursor, which must not be tiled.
74 combo->use_flags |= item->use_flags & ~BO_USE_CURSOR;
77 if (combo->metadata.modifier == item->modifier)
78 combo->use_flags |= item->use_flags;
84 static int i915_add_combinations(struct driver *drv)
87 uint32_t i, num_items;
88 struct kms_item *items;
89 struct format_metadata metadata;
90 uint64_t render_use_flags, texture_use_flags;
92 render_use_flags = BO_USE_RENDER_MASK;
93 texture_use_flags = BO_USE_TEXTURE_MASK;
95 metadata.tiling = I915_TILING_NONE;
96 metadata.priority = 1;
97 metadata.modifier = DRM_FORMAT_MOD_LINEAR;
99 ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
100 &metadata, render_use_flags);
104 ret = drv_add_combinations(drv, texture_source_formats, ARRAY_SIZE(texture_source_formats),
105 &metadata, texture_use_flags);
109 ret = drv_add_combinations(drv, tileable_texture_source_formats,
110 ARRAY_SIZE(tileable_texture_source_formats), &metadata,
115 drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
116 drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
118 /* IPU3 camera ISP supports only NV12 output. */
119 drv_modify_combination(drv, DRM_FORMAT_NV12, &metadata,
120 BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE);
122 * R8 format is used for Android's HAL_PIXEL_FORMAT_BLOB and is used for JPEG snapshots
125 drv_modify_combination(drv, DRM_FORMAT_R8, &metadata,
126 BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE);
128 render_use_flags &= ~BO_USE_RENDERSCRIPT;
129 render_use_flags &= ~BO_USE_SW_WRITE_OFTEN;
130 render_use_flags &= ~BO_USE_SW_READ_OFTEN;
131 render_use_flags &= ~BO_USE_LINEAR;
133 texture_use_flags &= ~BO_USE_RENDERSCRIPT;
134 texture_use_flags &= ~BO_USE_SW_WRITE_OFTEN;
135 texture_use_flags &= ~BO_USE_SW_READ_OFTEN;
136 texture_use_flags &= ~BO_USE_LINEAR;
138 metadata.tiling = I915_TILING_X;
139 metadata.priority = 2;
140 metadata.modifier = I915_FORMAT_MOD_X_TILED;
142 ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
143 &metadata, render_use_flags);
147 ret = drv_add_combinations(drv, tileable_texture_source_formats,
148 ARRAY_SIZE(tileable_texture_source_formats), &metadata,
153 metadata.tiling = I915_TILING_Y;
154 metadata.priority = 3;
155 metadata.modifier = I915_FORMAT_MOD_Y_TILED;
157 ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
158 &metadata, render_use_flags);
162 ret = drv_add_combinations(drv, tileable_texture_source_formats,
163 ARRAY_SIZE(tileable_texture_source_formats), &metadata,
168 items = drv_query_kms(drv, &num_items);
169 if (!items || !num_items)
172 for (i = 0; i < num_items; i++) {
173 ret = i915_add_kms_item(drv, &items[i]);
184 static int i915_align_dimensions(struct bo *bo, uint32_t tiling, uint32_t *stride,
185 uint32_t *aligned_height)
187 struct i915_device *i915 = bo->drv->priv;
188 uint32_t horizontal_alignment = 4;
189 uint32_t vertical_alignment = 4;
193 case I915_TILING_NONE:
194 horizontal_alignment = 64;
198 horizontal_alignment = 512;
199 vertical_alignment = 8;
203 if (i915->gen == 3) {
204 horizontal_alignment = 512;
205 vertical_alignment = 8;
207 horizontal_alignment = 128;
208 vertical_alignment = 32;
214 * The alignment calculated above is based on the full size luma plane and to have chroma
215 * planes properly aligned with subsampled formats, we need to multiply luma alignment by
216 * subsampling factor.
218 switch (bo->format) {
219 case DRM_FORMAT_YVU420_ANDROID:
220 case DRM_FORMAT_YVU420:
221 horizontal_alignment *= 2;
223 case DRM_FORMAT_NV12:
224 vertical_alignment *= 2;
228 *aligned_height = ALIGN(bo->height, vertical_alignment);
230 *stride = ALIGN(*stride, horizontal_alignment);
232 while (*stride > horizontal_alignment)
233 horizontal_alignment <<= 1;
235 *stride = horizontal_alignment;
238 if (i915->gen <= 3 && *stride > 8192)
244 static void i915_clflush(void *start, size_t size)
246 void *p = (void *)(((uintptr_t)start) & ~I915_CACHELINE_MASK);
247 void *end = (void *)((uintptr_t)start + size);
249 __builtin_ia32_mfence();
251 __builtin_ia32_clflush(p);
252 p = (void *)((uintptr_t)p + I915_CACHELINE_SIZE);
256 static int i915_init(struct driver *drv)
260 struct i915_device *i915;
261 drm_i915_getparam_t get_param;
263 i915 = calloc(1, sizeof(*i915));
267 memset(&get_param, 0, sizeof(get_param));
268 get_param.param = I915_PARAM_CHIPSET_ID;
269 get_param.value = &device_id;
270 ret = drmIoctl(drv->fd, DRM_IOCTL_I915_GETPARAM, &get_param);
272 fprintf(stderr, "drv: Failed to get I915_PARAM_CHIPSET_ID\n");
277 i915->gen = i915_get_gen(device_id);
279 memset(&get_param, 0, sizeof(get_param));
280 get_param.param = I915_PARAM_HAS_LLC;
281 get_param.value = &i915->has_llc;
282 ret = drmIoctl(drv->fd, DRM_IOCTL_I915_GETPARAM, &get_param);
284 fprintf(stderr, "drv: Failed to get I915_PARAM_HAS_LLC\n");
291 return i915_add_combinations(drv);
294 static int i915_bo_create_for_modifier(struct bo *bo, uint32_t width, uint32_t height,
295 uint32_t format, uint64_t modifier)
300 struct drm_i915_gem_create gem_create;
301 struct drm_i915_gem_set_tiling gem_set_tiling;
304 case DRM_FORMAT_MOD_LINEAR:
305 bo->tiling = I915_TILING_NONE;
307 case I915_FORMAT_MOD_X_TILED:
308 bo->tiling = I915_TILING_X;
310 case I915_FORMAT_MOD_Y_TILED:
311 bo->tiling = I915_TILING_Y;
315 stride = drv_stride_from_format(format, width, 0);
317 ret = i915_align_dimensions(bo, bo->tiling, &stride, &height);
322 * HAL_PIXEL_FORMAT_YV12 requires the buffer height not be aligned, but we need to keep
323 * total size as with aligned height to ensure enough padding space after each plane to
324 * satisfy GPU alignment requirements.
326 * We do it by first calling drv_bo_from_format() with aligned height and
327 * DRM_FORMAT_YVU420, which allows height alignment, saving the total size it calculates
328 * and then calling it again with requested parameters.
330 * This relies on the fact that i965 driver uses separate surfaces for each plane and
331 * contents of padding bytes is not affected, as it is only used to satisfy GPU cache
334 * This is enforced by Mesa in src/intel/isl/isl_gen8.c, inside
335 * isl_gen8_choose_image_alignment_el(), which is used for GEN9 and GEN8.
337 if (format == DRM_FORMAT_YVU420_ANDROID) {
338 uint32_t unaligned_height = bo->height;
341 drv_bo_from_format(bo, stride, height, DRM_FORMAT_YVU420);
342 total_size = bo->total_size;
343 drv_bo_from_format(bo, stride, unaligned_height, format);
344 bo->total_size = total_size;
346 drv_bo_from_format(bo, stride, height, format);
350 * Quoting Mesa ISL library:
352 * - For linear surfaces, additional padding of 64 bytes is required at
353 * the bottom of the surface. This is in addition to the padding
356 if (bo->tiling == I915_TILING_NONE)
357 bo->total_size += 64;
359 memset(&gem_create, 0, sizeof(gem_create));
360 gem_create.size = bo->total_size;
362 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_CREATE, &gem_create);
364 fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_CREATE failed (size=%llu)\n",
369 for (plane = 0; plane < bo->num_planes; plane++)
370 bo->handles[plane].u32 = gem_create.handle;
372 memset(&gem_set_tiling, 0, sizeof(gem_set_tiling));
373 gem_set_tiling.handle = bo->handles[0].u32;
374 gem_set_tiling.tiling_mode = bo->tiling;
375 gem_set_tiling.stride = bo->strides[0];
377 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_SET_TILING, &gem_set_tiling);
379 struct drm_gem_close gem_close;
380 memset(&gem_close, 0, sizeof(gem_close));
381 gem_close.handle = bo->handles[0].u32;
382 drmIoctl(bo->drv->fd, DRM_IOCTL_GEM_CLOSE, &gem_close);
384 fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_SET_TILING failed with %d", errno);
391 static int i915_bo_create(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
394 struct combination *combo;
396 combo = drv_get_combination(bo->drv, format, use_flags);
400 return i915_bo_create_for_modifier(bo, width, height, format, combo->metadata.modifier);
403 static int i915_bo_create_with_modifiers(struct bo *bo, uint32_t width, uint32_t height,
404 uint32_t format, const uint64_t *modifiers, uint32_t count)
406 static const uint64_t modifier_order[] = {
407 I915_FORMAT_MOD_Y_TILED, I915_FORMAT_MOD_X_TILED, DRM_FORMAT_MOD_LINEAR,
411 modifier = drv_pick_modifier(modifiers, count, modifier_order, ARRAY_SIZE(modifier_order));
413 bo->format_modifiers[0] = modifier;
415 return i915_bo_create_for_modifier(bo, width, height, format, modifier);
418 static void i915_close(struct driver *drv)
424 static int i915_bo_import(struct bo *bo, struct drv_import_fd_data *data)
427 struct drm_i915_gem_get_tiling gem_get_tiling;
429 ret = drv_prime_bo_import(bo, data);
433 /* TODO(gsingh): export modifiers and get rid of backdoor tiling. */
434 memset(&gem_get_tiling, 0, sizeof(gem_get_tiling));
435 gem_get_tiling.handle = bo->handles[0].u32;
437 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_GET_TILING, &gem_get_tiling);
439 drv_gem_bo_destroy(bo);
440 fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_GET_TILING failed.");
444 bo->tiling = gem_get_tiling.tiling_mode;
448 static void *i915_bo_map(struct bo *bo, struct map_info *data, size_t plane, uint32_t map_flags)
453 if (bo->tiling == I915_TILING_NONE) {
454 struct drm_i915_gem_mmap gem_map;
455 memset(&gem_map, 0, sizeof(gem_map));
457 if ((bo->use_flags & BO_USE_SCANOUT) && !(bo->use_flags & BO_USE_RENDERSCRIPT))
458 gem_map.flags = I915_MMAP_WC;
460 gem_map.handle = bo->handles[0].u32;
462 gem_map.size = bo->total_size;
464 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_MMAP, &gem_map);
466 fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_MMAP failed\n");
470 addr = (void *)(uintptr_t)gem_map.addr_ptr;
472 struct drm_i915_gem_mmap_gtt gem_map;
473 memset(&gem_map, 0, sizeof(gem_map));
475 gem_map.handle = bo->handles[0].u32;
477 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_MMAP_GTT, &gem_map);
479 fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_MMAP_GTT failed\n");
483 addr = mmap(0, bo->total_size, drv_get_prot(map_flags), MAP_SHARED, bo->drv->fd,
487 if (addr == MAP_FAILED) {
488 fprintf(stderr, "drv: i915 GEM mmap failed\n");
492 data->length = bo->total_size;
496 static int i915_bo_invalidate(struct bo *bo, struct map_info *data)
499 struct drm_i915_gem_set_domain set_domain;
501 memset(&set_domain, 0, sizeof(set_domain));
502 set_domain.handle = bo->handles[0].u32;
503 if (bo->tiling == I915_TILING_NONE) {
504 set_domain.read_domains = I915_GEM_DOMAIN_CPU;
505 if (data->map_flags & BO_MAP_WRITE)
506 set_domain.write_domain = I915_GEM_DOMAIN_CPU;
508 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
509 if (data->map_flags & BO_MAP_WRITE)
510 set_domain.write_domain = I915_GEM_DOMAIN_GTT;
513 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_SET_DOMAIN, &set_domain);
515 fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_SET_DOMAIN with %d\n", ret);
522 static int i915_bo_flush(struct bo *bo, struct map_info *data)
524 struct i915_device *i915 = bo->drv->priv;
525 if (!i915->has_llc && bo->tiling == I915_TILING_NONE)
526 i915_clflush(data->addr, data->length);
531 static uint32_t i915_resolve_format(uint32_t format, uint64_t use_flags)
534 case DRM_FORMAT_FLEX_IMPLEMENTATION_DEFINED:
535 /* KBL camera subsystem requires NV12. */
536 if (use_flags & (BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE))
537 return DRM_FORMAT_NV12;
538 /*HACK: See b/28671744 */
539 return DRM_FORMAT_XBGR8888;
540 case DRM_FORMAT_FLEX_YCbCr_420_888:
541 /* KBL camera subsystem requires NV12. */
542 if (use_flags & (BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE))
543 return DRM_FORMAT_NV12;
544 return DRM_FORMAT_YVU420;
550 struct backend backend_i915 = {
554 .bo_create = i915_bo_create,
555 .bo_create_with_modifiers = i915_bo_create_with_modifiers,
556 .bo_destroy = drv_gem_bo_destroy,
557 .bo_import = i915_bo_import,
558 .bo_map = i915_bo_map,
559 .bo_unmap = drv_bo_munmap,
560 .bo_invalidate = i915_bo_invalidate,
561 .bo_flush = i915_bo_flush,
562 .resolve_format = i915_resolve_format,