i915.c

   1 /*
   2  * Copyright 2014 The Chromium OS Authors. All rights reserved.
   3  * Use of this source code is governed by a BSD-style license that can be
   4  * found in the LICENSE file.
   5  */
   6
   7 #ifdef DRV_I915
   8
   9 #include <assert.h>
  10 #include <errno.h>
  11 #include <i915_drm.h>
  12 #include <stdbool.h>
  13 #include <stdio.h>
  14 #include <string.h>
  15 #include <sys/mman.h>
  16 #include <unistd.h>
  17 #include <xf86drm.h>
  18
  19 #include "drv_priv.h"
  20 #include "helpers.h"
  21 #include "util.h"
  22
  23 #define I915_CACHELINE_SIZE 64
  24 #define I915_CACHELINE_MASK (I915_CACHELINE_SIZE - 1)
  25
  26 static const uint32_t scanout_render_formats[] = { DRM_FORMAT_ABGR2101010, DRM_FORMAT_ABGR8888,
  27                                                    DRM_FORMAT_ARGB2101010, DRM_FORMAT_ARGB8888,
  28                                                    DRM_FORMAT_RGB565,      DRM_FORMAT_XBGR2101010,
  29                                                    DRM_FORMAT_XBGR8888,    DRM_FORMAT_XRGB2101010,
  30                                                    DRM_FORMAT_XRGB8888 };
  31
  32 static const uint32_t render_formats[] = { DRM_FORMAT_ABGR16161616F };
  33
  34 static const uint32_t texture_only_formats[] = { DRM_FORMAT_R8, DRM_FORMAT_NV12, DRM_FORMAT_P010,
  35                                                  DRM_FORMAT_YVU420, DRM_FORMAT_YVU420_ANDROID };
  36
  37 static const uint64_t gen_modifier_order[] = { I915_FORMAT_MOD_Y_TILED, I915_FORMAT_MOD_X_TILED,
  38                                                DRM_FORMAT_MOD_LINEAR };
  39
  40 static const uint64_t gen11_modifier_order[] = { I915_FORMAT_MOD_Y_TILED_CCS,
  41                                                  I915_FORMAT_MOD_Y_TILED, I915_FORMAT_MOD_X_TILED,
  42                                                  DRM_FORMAT_MOD_LINEAR };
  43
  44 struct modifier_support_t {
  45         const uint64_t *order;
  46         uint32_t count;
  47 };
  48
  49 struct i915_device {
  50         uint32_t gen;
  51         int32_t has_llc;
  52         struct modifier_support_t modifier;
  53 };
  54
  55 static uint32_t i915_get_gen(int device_id)
  56 {
  57         const uint16_t gen3_ids[] = { 0x2582, 0x2592, 0x2772, 0x27A2, 0x27AE,
  58                                       0x29C2, 0x29B2, 0x29D2, 0xA001, 0xA011 };
  59         const uint16_t gen11_ids[] = { 0x4E71, 0x4E61, 0x4E51, 0x4E55, 0x4E57 };
  60
  61         unsigned i;
  62         for (i = 0; i < ARRAY_SIZE(gen3_ids); i++)
  63                 if (gen3_ids[i] == device_id)
  64                         return 3;
  65         /* Gen 11 */
  66         for (i = 0; i < ARRAY_SIZE(gen11_ids); i++)
  67                 if (gen11_ids[i] == device_id)
  68                         return 11;
  69
  70         return 4;
  71 }
  72
  73 static void i915_get_modifier_order(struct i915_device *i915)
  74 {
  75         if (i915->gen == 11) {
  76                 i915->modifier.order = gen11_modifier_order;
  77                 i915->modifier.count = ARRAY_SIZE(gen11_modifier_order);
  78         } else {
  79                 i915->modifier.order = gen_modifier_order;
  80                 i915->modifier.count = ARRAY_SIZE(gen_modifier_order);
  81         }
  82 }
  83
  84 static uint64_t unset_flags(uint64_t current_flags, uint64_t mask)
  85 {
  86         uint64_t value = current_flags & ~mask;
  87         return value;
  88 }
  89
  90 static int i915_add_combinations(struct driver *drv)
  91 {
  92         struct format_metadata metadata;
  93         uint64_t render, scanout_and_render, texture_only;
  94
  95         scanout_and_render = BO_USE_RENDER_MASK | BO_USE_SCANOUT;
  96         render = BO_USE_RENDER_MASK;
  97         texture_only = BO_USE_TEXTURE_MASK;
  98         uint64_t linear_mask = BO_USE_RENDERSCRIPT | BO_USE_LINEAR | BO_USE_PROTECTED |
  99                                BO_USE_SW_READ_OFTEN | BO_USE_SW_WRITE_OFTEN;
 100
 101         metadata.tiling = I915_TILING_NONE;
 102         metadata.priority = 1;
 103         metadata.modifier = DRM_FORMAT_MOD_LINEAR;
 104
 105         drv_add_combinations(drv, scanout_render_formats, ARRAY_SIZE(scanout_render_formats),
 106                              &metadata, scanout_and_render);
 107
 108         drv_add_combinations(drv, render_formats, ARRAY_SIZE(render_formats), &metadata, render);
 109
 110         drv_add_combinations(drv, texture_only_formats, ARRAY_SIZE(texture_only_formats), &metadata,
 111                              texture_only);
 112
 113         drv_modify_linear_combinations(drv);
 114
 115         /* NV12 format for camera, display, decoding and encoding. */
 116         /* IPU3 camera ISP supports only NV12 output. */
 117         drv_modify_combination(drv, DRM_FORMAT_NV12, &metadata,
 118                                BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE | BO_USE_SCANOUT |
 119                                    BO_USE_HW_VIDEO_DECODER | BO_USE_HW_VIDEO_ENCODER);
 120
 121         /* Android CTS tests require this. */
 122         drv_add_combination(drv, DRM_FORMAT_BGR888, &metadata, BO_USE_SW_MASK);
 123
 124         /*
 125          * R8 format is used for Android's HAL_PIXEL_FORMAT_BLOB and is used for JPEG snapshots
 126          * from camera and input/output from hardware decoder/encoder.
 127          */
 128         drv_modify_combination(drv, DRM_FORMAT_R8, &metadata,
 129                                BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE | BO_USE_HW_VIDEO_DECODER |
 130                                    BO_USE_HW_VIDEO_ENCODER);
 131
 132         render = unset_flags(render, linear_mask);
 133         scanout_and_render = unset_flags(scanout_and_render, linear_mask);
 134
 135         metadata.tiling = I915_TILING_X;
 136         metadata.priority = 2;
 137         metadata.modifier = I915_FORMAT_MOD_X_TILED;
 138
 139         drv_add_combinations(drv, render_formats, ARRAY_SIZE(render_formats), &metadata, render);
 140         drv_add_combinations(drv, scanout_render_formats, ARRAY_SIZE(scanout_render_formats),
 141                              &metadata, scanout_and_render);
 142
 143         metadata.tiling = I915_TILING_Y;
 144         metadata.priority = 3;
 145         metadata.modifier = I915_FORMAT_MOD_Y_TILED;
 146
 147         scanout_and_render =
 148             unset_flags(scanout_and_render, BO_USE_SW_READ_RARELY | BO_USE_SW_WRITE_RARELY);
 149 /* Support y-tiled NV12 and P010 for libva */
 150 #ifdef I915_SCANOUT_Y_TILED
 151         drv_add_combination(drv, DRM_FORMAT_NV12, &metadata,
 152                             BO_USE_TEXTURE | BO_USE_HW_VIDEO_DECODER | BO_USE_SCANOUT);
 153 #else
 154         drv_add_combination(drv, DRM_FORMAT_NV12, &metadata,
 155                             BO_USE_TEXTURE | BO_USE_HW_VIDEO_DECODER);
 156 #endif
 157         scanout_and_render = unset_flags(scanout_and_render, BO_USE_SCANOUT);
 158         drv_add_combination(drv, DRM_FORMAT_P010, &metadata,
 159                             BO_USE_TEXTURE | BO_USE_HW_VIDEO_DECODER);
 160
 161         drv_add_combinations(drv, render_formats, ARRAY_SIZE(render_formats), &metadata, render);
 162         drv_add_combinations(drv, scanout_render_formats, ARRAY_SIZE(scanout_render_formats),
 163                              &metadata, scanout_and_render);
 164         return 0;
 165 }
 166
 167 static int i915_align_dimensions(struct bo *bo, uint32_t tiling, uint32_t *stride,
 168                                  uint32_t *aligned_height)
 169 {
 170         struct i915_device *i915 = bo->drv->priv;
 171         uint32_t horizontal_alignment;
 172         uint32_t vertical_alignment;
 173
 174         switch (tiling) {
 175         default:
 176         case I915_TILING_NONE:
 177                 /*
 178                  * The Intel GPU doesn't need any alignment in linear mode,
 179                  * but libva requires the allocation stride to be aligned to
 180                  * 16 bytes and height to 4 rows. Further, we round up the
 181                  * horizontal alignment so that row start on a cache line (64
 182                  * bytes).
 183                  */
 184                 horizontal_alignment = 64;
 185                 vertical_alignment = 4;
 186                 break;
 187
 188         case I915_TILING_X:
 189                 horizontal_alignment = 512;
 190                 vertical_alignment = 8;
 191                 break;
 192
 193         case I915_TILING_Y:
 194                 if (i915->gen == 3) {
 195                         horizontal_alignment = 512;
 196                         vertical_alignment = 8;
 197                 } else {
 198                         horizontal_alignment = 128;
 199                         vertical_alignment = 32;
 200                 }
 201                 break;
 202         }
 203
 204         *aligned_height = ALIGN(*aligned_height, vertical_alignment);
 205         if (i915->gen > 3) {
 206                 *stride = ALIGN(*stride, horizontal_alignment);
 207         } else {
 208                 while (*stride > horizontal_alignment)
 209                         horizontal_alignment <<= 1;
 210
 211                 *stride = horizontal_alignment;
 212         }
 213
 214         if (i915->gen <= 3 && *stride > 8192)
 215                 return -EINVAL;
 216
 217         return 0;
 218 }
 219
 220 static void i915_clflush(void *start, size_t size)
 221 {
 222         void *p = (void *)(((uintptr_t)start) & ~I915_CACHELINE_MASK);
 223         void *end = (void *)((uintptr_t)start + size);
 224
 225         __builtin_ia32_mfence();
 226         while (p < end) {
 227                 __builtin_ia32_clflush(p);
 228                 p = (void *)((uintptr_t)p + I915_CACHELINE_SIZE);
 229         }
 230 }
 231
 232 static int i915_init(struct driver *drv)
 233 {
 234         int ret;
 235         int device_id;
 236         struct i915_device *i915;
 237         drm_i915_getparam_t get_param;
 238
 239         i915 = calloc(1, sizeof(*i915));
 240         if (!i915)
 241                 return -ENOMEM;
 242
 243         memset(&get_param, 0, sizeof(get_param));
 244         get_param.param = I915_PARAM_CHIPSET_ID;
 245         get_param.value = &device_id;
 246         ret = drmIoctl(drv->fd, DRM_IOCTL_I915_GETPARAM, &get_param);
 247         if (ret) {
 248                 drv_log("Failed to get I915_PARAM_CHIPSET_ID\n");
 249                 free(i915);
 250                 return -EINVAL;
 251         }
 252
 253         i915->gen = i915_get_gen(device_id);
 254         i915_get_modifier_order(i915);
 255
 256         memset(&get_param, 0, sizeof(get_param));
 257         get_param.param = I915_PARAM_HAS_LLC;
 258         get_param.value = &i915->has_llc;
 259         ret = drmIoctl(drv->fd, DRM_IOCTL_I915_GETPARAM, &get_param);
 260         if (ret) {
 261                 drv_log("Failed to get I915_PARAM_HAS_LLC\n");
 262                 free(i915);
 263                 return -EINVAL;
 264         }
 265
 266         drv->priv = i915;
 267
 268         return i915_add_combinations(drv);
 269 }
 270
 271 static int i915_bo_from_format(struct bo *bo, uint32_t width, uint32_t height, uint32_t format)
 272 {
 273         uint32_t offset;
 274         size_t plane;
 275         int ret, pagesize;
 276
 277         offset = 0;
 278         pagesize = getpagesize();
 279         for (plane = 0; plane < drv_num_planes_from_format(format); plane++) {
 280                 uint32_t stride = drv_stride_from_format(format, width, plane);
 281                 uint32_t plane_height = drv_height_from_format(format, height, plane);
 282
 283                 if (bo->meta.tiling != I915_TILING_NONE)
 284                         assert(IS_ALIGNED(offset, pagesize));
 285
 286                 ret = i915_align_dimensions(bo, bo->meta.tiling, &stride, &plane_height);
 287                 if (ret)
 288                         return ret;
 289
 290                 bo->meta.strides[plane] = stride;
 291                 bo->meta.sizes[plane] = stride * plane_height;
 292                 bo->meta.offsets[plane] = offset;
 293                 offset += bo->meta.sizes[plane];
 294         }
 295
 296         bo->meta.total_size = ALIGN(offset, pagesize);
 297
 298         return 0;
 299 }
 300
 301 static int i915_bo_compute_metadata(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
 302                                     uint64_t use_flags, const uint64_t *modifiers, uint32_t count)
 303 {
 304         uint64_t modifier;
 305         struct i915_device *i915 = bo->drv->priv;
 306         bool huge_bo = (i915->gen <= 11) && (width > 4096);
 307
 308         if (modifiers) {
 309                 modifier =
 310                     drv_pick_modifier(modifiers, count, i915->modifier.order, i915->modifier.count);
 311         } else {
 312                 struct combination *combo = drv_get_combination(bo->drv, format, use_flags);
 313                 if (!combo)
 314                         return -EINVAL;
 315                 modifier = combo->metadata.modifier;
 316         }
 317
 318         /*
 319          * i915 only supports linear/x-tiled above 4096 wide
 320          */
 321         if (huge_bo && modifier != I915_FORMAT_MOD_X_TILED && modifier != DRM_FORMAT_MOD_LINEAR) {
 322                 uint32_t i;
 323                 for (i = 0; modifiers && i < count; i++) {
 324                         if (modifiers[i] == I915_FORMAT_MOD_X_TILED)
 325                                 break;
 326                 }
 327                 if (i == count)
 328                         modifier = DRM_FORMAT_MOD_LINEAR;
 329                 else
 330                         modifier = I915_FORMAT_MOD_X_TILED;
 331         }
 332
 333         switch (modifier) {
 334         case DRM_FORMAT_MOD_LINEAR:
 335                 bo->meta.tiling = I915_TILING_NONE;
 336                 break;
 337         case I915_FORMAT_MOD_X_TILED:
 338                 bo->meta.tiling = I915_TILING_X;
 339                 break;
 340         case I915_FORMAT_MOD_Y_TILED:
 341         case I915_FORMAT_MOD_Y_TILED_CCS:
 342                 bo->meta.tiling = I915_TILING_Y;
 343                 break;
 344         }
 345
 346         bo->meta.format_modifiers[0] = modifier;
 347
 348         if (format == DRM_FORMAT_YVU420_ANDROID) {
 349                 /*
 350                  * We only need to be able to use this as a linear texture,
 351                  * which doesn't put any HW restrictions on how we lay it
 352                  * out. The Android format does require the stride to be a
 353                  * multiple of 16 and expects the Cr and Cb stride to be
 354                  * ALIGN(Y_stride / 2, 16), which we can make happen by
 355                  * aligning to 32 bytes here.
 356                  */
 357                 uint32_t stride = ALIGN(width, 32);
 358                 drv_bo_from_format(bo, stride, height, format);
 359         } else if (modifier == I915_FORMAT_MOD_Y_TILED_CCS) {
 360                 /*
 361                  * For compressed surfaces, we need a color control surface
 362                  * (CCS). Color compression is only supported for Y tiled
 363                  * surfaces, and for each 32x16 tiles in the main surface we
 364                  * need a tile in the control surface.  Y tiles are 128 bytes
 365                  * wide and 32 lines tall and we use that to first compute the
 366                  * width and height in tiles of the main surface. stride and
 367                  * height are already multiples of 128 and 32, respectively:
 368                  */
 369                 uint32_t stride = drv_stride_from_format(format, width, 0);
 370                 uint32_t width_in_tiles = DIV_ROUND_UP(stride, 128);
 371                 uint32_t height_in_tiles = DIV_ROUND_UP(height, 32);
 372                 uint32_t size = width_in_tiles * height_in_tiles * 4096;
 373                 uint32_t offset = 0;
 374
 375                 bo->meta.strides[0] = width_in_tiles * 128;
 376                 bo->meta.sizes[0] = size;
 377                 bo->meta.offsets[0] = offset;
 378                 offset += size;
 379
 380                 /*
 381                  * Now, compute the width and height in tiles of the control
 382                  * surface by dividing and rounding up.
 383                  */
 384                 uint32_t ccs_width_in_tiles = DIV_ROUND_UP(width_in_tiles, 32);
 385                 uint32_t ccs_height_in_tiles = DIV_ROUND_UP(height_in_tiles, 16);
 386                 uint32_t ccs_size = ccs_width_in_tiles * ccs_height_in_tiles * 4096;
 387
 388                 /*
 389                  * With stride and height aligned to y tiles, offset is
 390                  * already a multiple of 4096, which is the required alignment
 391                  * of the CCS.
 392                  */
 393                 bo->meta.strides[1] = ccs_width_in_tiles * 128;
 394                 bo->meta.sizes[1] = ccs_size;
 395                 bo->meta.offsets[1] = offset;
 396                 offset += ccs_size;
 397
 398                 bo->meta.num_planes = 2;
 399                 bo->meta.total_size = offset;
 400         } else {
 401                 i915_bo_from_format(bo, width, height, format);
 402         }
 403         return 0;
 404 }
 405
 406 static int i915_bo_create_from_metadata(struct bo *bo)
 407 {
 408         int ret;
 409         size_t plane;
 410         struct drm_i915_gem_create gem_create;
 411         struct drm_i915_gem_set_tiling gem_set_tiling;
 412
 413         memset(&gem_create, 0, sizeof(gem_create));
 414         gem_create.size = bo->meta.total_size;
 415
 416         ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_CREATE, &gem_create);
 417         if (ret) {
 418                 drv_log("DRM_IOCTL_I915_GEM_CREATE failed (size=%llu)\n", gem_create.size);
 419                 return -errno;
 420         }
 421
 422         for (plane = 0; plane < bo->meta.num_planes; plane++)
 423                 bo->handles[plane].u32 = gem_create.handle;
 424
 425         memset(&gem_set_tiling, 0, sizeof(gem_set_tiling));
 426         gem_set_tiling.handle = bo->handles[0].u32;
 427         gem_set_tiling.tiling_mode = bo->meta.tiling;
 428         gem_set_tiling.stride = bo->meta.strides[0];
 429
 430         ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_SET_TILING, &gem_set_tiling);
 431         if (ret) {
 432                 struct drm_gem_close gem_close;
 433                 memset(&gem_close, 0, sizeof(gem_close));
 434                 gem_close.handle = bo->handles[0].u32;
 435                 drmIoctl(bo->drv->fd, DRM_IOCTL_GEM_CLOSE, &gem_close);
 436
 437                 drv_log("DRM_IOCTL_I915_GEM_SET_TILING failed with %d\n", errno);
 438                 return -errno;
 439         }
 440
 441         return 0;
 442 }
 443
 444 static void i915_close(struct driver *drv)
 445 {
 446         free(drv->priv);
 447         drv->priv = NULL;
 448 }
 449
 450 static int i915_bo_import(struct bo *bo, struct drv_import_fd_data *data)
 451 {
 452         int ret;
 453         struct drm_i915_gem_get_tiling gem_get_tiling;
 454
 455         ret = drv_prime_bo_import(bo, data);
 456         if (ret)
 457                 return ret;
 458
 459         /* TODO(gsingh): export modifiers and get rid of backdoor tiling. */
 460         memset(&gem_get_tiling, 0, sizeof(gem_get_tiling));
 461         gem_get_tiling.handle = bo->handles[0].u32;
 462
 463         ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_GET_TILING, &gem_get_tiling);
 464         if (ret) {
 465                 drv_gem_bo_destroy(bo);
 466                 drv_log("DRM_IOCTL_I915_GEM_GET_TILING failed.\n");
 467                 return ret;
 468         }
 469
 470         bo->meta.tiling = gem_get_tiling.tiling_mode;
 471         return 0;
 472 }
 473
 474 static void *i915_bo_map(struct bo *bo, struct vma *vma, size_t plane, uint32_t map_flags)
 475 {
 476         int ret;
 477         void *addr;
 478
 479         if (bo->meta.format_modifiers[0] == I915_FORMAT_MOD_Y_TILED_CCS)
 480                 return MAP_FAILED;
 481
 482         if (bo->meta.tiling == I915_TILING_NONE) {
 483                 struct drm_i915_gem_mmap gem_map;
 484                 memset(&gem_map, 0, sizeof(gem_map));
 485
 486                 /* TODO(b/118799155): We don't seem to have a good way to
 487                  * detect the use cases for which WC mapping is really needed.
 488                  * The current heuristic seems overly coarse and may be slowing
 489                  * down some other use cases unnecessarily.
 490                  *
 491                  * For now, care must be taken not to use WC mappings for
 492                  * Renderscript and camera use cases, as they're
 493                  * performance-sensitive. */
 494                 if ((bo->meta.use_flags & BO_USE_SCANOUT) &&
 495                     !(bo->meta.use_flags &
 496                       (BO_USE_RENDERSCRIPT | BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE)))
 497                         gem_map.flags = I915_MMAP_WC;
 498
 499                 gem_map.handle = bo->handles[0].u32;
 500                 gem_map.offset = 0;
 501                 gem_map.size = bo->meta.total_size;
 502
 503                 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_MMAP, &gem_map);
 504                 if (ret) {
 505                         drv_log("DRM_IOCTL_I915_GEM_MMAP failed\n");
 506                         return MAP_FAILED;
 507                 }
 508
 509                 addr = (void *)(uintptr_t)gem_map.addr_ptr;
 510         } else {
 511                 struct drm_i915_gem_mmap_gtt gem_map;
 512                 memset(&gem_map, 0, sizeof(gem_map));
 513
 514                 gem_map.handle = bo->handles[0].u32;
 515
 516                 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_MMAP_GTT, &gem_map);
 517                 if (ret) {
 518                         drv_log("DRM_IOCTL_I915_GEM_MMAP_GTT failed\n");
 519                         return MAP_FAILED;
 520                 }
 521
 522                 addr = mmap(0, bo->meta.total_size, drv_get_prot(map_flags), MAP_SHARED,
 523                             bo->drv->fd, gem_map.offset);
 524         }
 525
 526         if (addr == MAP_FAILED) {
 527                 drv_log("i915 GEM mmap failed\n");
 528                 return addr;
 529         }
 530
 531         vma->length = bo->meta.total_size;
 532         return addr;
 533 }
 534
 535 static int i915_bo_invalidate(struct bo *bo, struct mapping *mapping)
 536 {
 537         int ret;
 538         struct drm_i915_gem_set_domain set_domain;
 539
 540         memset(&set_domain, 0, sizeof(set_domain));
 541         set_domain.handle = bo->handles[0].u32;
 542         if (bo->meta.tiling == I915_TILING_NONE) {
 543                 set_domain.read_domains = I915_GEM_DOMAIN_CPU;
 544                 if (mapping->vma->map_flags & BO_MAP_WRITE)
 545                         set_domain.write_domain = I915_GEM_DOMAIN_CPU;
 546         } else {
 547                 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
 548                 if (mapping->vma->map_flags & BO_MAP_WRITE)
 549                         set_domain.write_domain = I915_GEM_DOMAIN_GTT;
 550         }
 551
 552         ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_SET_DOMAIN, &set_domain);
 553         if (ret) {
 554                 drv_log("DRM_IOCTL_I915_GEM_SET_DOMAIN with %d\n", ret);
 555                 return ret;
 556         }
 557
 558         return 0;
 559 }
 560
 561 static int i915_bo_flush(struct bo *bo, struct mapping *mapping)
 562 {
 563         struct i915_device *i915 = bo->drv->priv;
 564         if (!i915->has_llc && bo->meta.tiling == I915_TILING_NONE)
 565                 i915_clflush(mapping->vma->addr, mapping->vma->length);
 566
 567         return 0;
 568 }
 569
 570 static uint32_t i915_resolve_format(struct driver *drv, uint32_t format, uint64_t use_flags)
 571 {
 572         switch (format) {
 573         case DRM_FORMAT_FLEX_IMPLEMENTATION_DEFINED:
 574                 /* KBL camera subsystem requires NV12. */
 575                 if (use_flags & (BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE))
 576                         return DRM_FORMAT_NV12;
 577                 /*HACK: See b/28671744 */
 578                 return DRM_FORMAT_XBGR8888;
 579         case DRM_FORMAT_FLEX_YCbCr_420_888:
 580                 /*
 581                  * KBL camera subsystem requires NV12. Our other use cases
 582                  * don't care:
 583                  * - Hardware video supports NV12,
 584                  * - USB Camera HALv3 supports NV12,
 585                  * - USB Camera HALv1 doesn't use this format.
 586                  * Moreover, NV12 is preferred for video, due to overlay
 587                  * support on SKL+.
 588                  */
 589                 return DRM_FORMAT_NV12;
 590         default:
 591                 return format;
 592         }
 593 }
 594
 595 const struct backend backend_i915 = {
 596         .name = "i915",
 597         .init = i915_init,
 598         .close = i915_close,
 599         .bo_compute_metadata = i915_bo_compute_metadata,
 600         .bo_create_from_metadata = i915_bo_create_from_metadata,
 601         .bo_destroy = drv_gem_bo_destroy,
 602         .bo_import = i915_bo_import,
 603         .bo_map = i915_bo_map,
 604         .bo_unmap = drv_bo_munmap,
 605         .bo_invalidate = i915_bo_invalidate,
 606         .bo_flush = i915_bo_flush,
 607         .resolve_format = i915_resolve_format,
 608 };
 609
 610 #endif