i915.c

   1 /*
   2  * Copyright 2014 The Chromium OS Authors. All rights reserved.
   3  * Use of this source code is governed by a BSD-style license that can be
   4  * found in the LICENSE file.
   5  */
   6
   7 #ifdef DRV_I915
   8
   9 #include <assert.h>
  10 #include <errno.h>
  11 #include <stdbool.h>
  12 #include <stdio.h>
  13 #include <string.h>
  14 #include <sys/mman.h>
  15 #include <unistd.h>
  16 #include <xf86drm.h>
  17
  18 #include "drv_priv.h"
  19 #include "external/i915_drm.h"
  20 #include "helpers.h"
  21 #include "util.h"
  22
  23 #define I915_CACHELINE_SIZE 64
  24 #define I915_CACHELINE_MASK (I915_CACHELINE_SIZE - 1)
  25
  26 static const uint32_t scanout_render_formats[] = { DRM_FORMAT_ABGR2101010, DRM_FORMAT_ABGR8888,
  27                                                    DRM_FORMAT_ARGB2101010, DRM_FORMAT_ARGB8888,
  28                                                    DRM_FORMAT_RGB565,      DRM_FORMAT_XBGR2101010,
  29                                                    DRM_FORMAT_XBGR8888,    DRM_FORMAT_XRGB2101010,
  30                                                    DRM_FORMAT_XRGB8888 };
  31
  32 static const uint32_t render_formats[] = { DRM_FORMAT_ABGR16161616F };
  33
  34 static const uint32_t texture_only_formats[] = { DRM_FORMAT_R8, DRM_FORMAT_NV12, DRM_FORMAT_P010,
  35                                                  DRM_FORMAT_YVU420, DRM_FORMAT_YVU420_ANDROID };
  36
  37 static const uint64_t gen_modifier_order[] = { I915_FORMAT_MOD_Y_TILED, I915_FORMAT_MOD_X_TILED,
  38                                                DRM_FORMAT_MOD_LINEAR };
  39
  40 static const uint64_t gen11_modifier_order[] = { I915_FORMAT_MOD_Y_TILED_CCS,
  41                                                  I915_FORMAT_MOD_Y_TILED, I915_FORMAT_MOD_X_TILED,
  42                                                  DRM_FORMAT_MOD_LINEAR };
  43
  44 struct modifier_support_t {
  45         const uint64_t *order;
  46         uint32_t count;
  47 };
  48
  49 struct i915_device {
  50         uint32_t gen;
  51         int32_t has_llc;
  52         int32_t has_hw_protection;
  53         struct modifier_support_t modifier;
  54 };
  55
  56 static uint32_t i915_get_gen(int device_id)
  57 {
  58         const uint16_t gen3_ids[] = { 0x2582, 0x2592, 0x2772, 0x27A2, 0x27AE,
  59                                       0x29C2, 0x29B2, 0x29D2, 0xA001, 0xA011 };
  60         const uint16_t gen11_ids[] = { 0x4E71, 0x4E61, 0x4E51, 0x4E55, 0x4E57 };
  61         const uint16_t gen12_ids[] = { 0x9A40, 0x9A49, 0x9A59, 0x9A60, 0x9A68, 0x9A70,
  62                                        0x9A78, 0x9AC0, 0x9AC9, 0x9AD9, 0x9AF8 };
  63         unsigned i;
  64         for (i = 0; i < ARRAY_SIZE(gen3_ids); i++)
  65                 if (gen3_ids[i] == device_id)
  66                         return 3;
  67         /* Gen 11 */
  68         for (i = 0; i < ARRAY_SIZE(gen11_ids); i++)
  69                 if (gen11_ids[i] == device_id)
  70                         return 11;
  71
  72         /* Gen 12 */
  73         for (i = 0; i < ARRAY_SIZE(gen12_ids); i++)
  74                 if (gen12_ids[i] == device_id)
  75                         return 12;
  76
  77         return 4;
  78 }
  79
  80 static void i915_get_modifier_order(struct i915_device *i915)
  81 {
  82         if (i915->gen == 11) {
  83                 i915->modifier.order = gen11_modifier_order;
  84                 i915->modifier.count = ARRAY_SIZE(gen11_modifier_order);
  85         } else {
  86                 i915->modifier.order = gen_modifier_order;
  87                 i915->modifier.count = ARRAY_SIZE(gen_modifier_order);
  88         }
  89 }
  90
  91 static uint64_t unset_flags(uint64_t current_flags, uint64_t mask)
  92 {
  93         uint64_t value = current_flags & ~mask;
  94         return value;
  95 }
  96
  97 static int i915_add_combinations(struct driver *drv)
  98 {
  99         struct format_metadata metadata;
 100         uint64_t render, scanout_and_render, texture_only, hw_protected;
 101         struct i915_device *i915 = drv->priv;
 102
 103         scanout_and_render = BO_USE_RENDER_MASK | BO_USE_SCANOUT;
 104         render = BO_USE_RENDER_MASK;
 105         texture_only = BO_USE_TEXTURE_MASK;
 106         // HW protected buffers also need to be scanned out.
 107         hw_protected = i915->has_hw_protection ? (BO_USE_PROTECTED | BO_USE_SCANOUT) : 0;
 108
 109         uint64_t linear_mask =
 110             BO_USE_RENDERSCRIPT | BO_USE_LINEAR | BO_USE_SW_READ_OFTEN | BO_USE_SW_WRITE_OFTEN;
 111
 112         metadata.tiling = I915_TILING_NONE;
 113         metadata.priority = 1;
 114         metadata.modifier = DRM_FORMAT_MOD_LINEAR;
 115
 116         drv_add_combinations(drv, scanout_render_formats, ARRAY_SIZE(scanout_render_formats),
 117                              &metadata, scanout_and_render);
 118
 119         drv_add_combinations(drv, render_formats, ARRAY_SIZE(render_formats), &metadata, render);
 120
 121         drv_add_combinations(drv, texture_only_formats, ARRAY_SIZE(texture_only_formats), &metadata,
 122                              texture_only);
 123
 124         drv_modify_linear_combinations(drv);
 125
 126         /* NV12 format for camera, display, decoding and encoding. */
 127         /* IPU3 camera ISP supports only NV12 output. */
 128         drv_modify_combination(drv, DRM_FORMAT_NV12, &metadata,
 129                                BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE | BO_USE_SCANOUT |
 130                                    BO_USE_HW_VIDEO_DECODER | BO_USE_HW_VIDEO_ENCODER |
 131                                    hw_protected);
 132
 133         /* Android CTS tests require this. */
 134         drv_add_combination(drv, DRM_FORMAT_BGR888, &metadata, BO_USE_SW_MASK);
 135
 136         /*
 137          * R8 format is used for Android's HAL_PIXEL_FORMAT_BLOB and is used for JPEG snapshots
 138          * from camera and input/output from hardware decoder/encoder.
 139          */
 140         drv_modify_combination(drv, DRM_FORMAT_R8, &metadata,
 141                                BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE | BO_USE_HW_VIDEO_DECODER |
 142                                    BO_USE_HW_VIDEO_ENCODER);
 143
 144         render = unset_flags(render, linear_mask);
 145         scanout_and_render = unset_flags(scanout_and_render, linear_mask);
 146
 147         metadata.tiling = I915_TILING_X;
 148         metadata.priority = 2;
 149         metadata.modifier = I915_FORMAT_MOD_X_TILED;
 150
 151         drv_add_combinations(drv, render_formats, ARRAY_SIZE(render_formats), &metadata, render);
 152         drv_add_combinations(drv, scanout_render_formats, ARRAY_SIZE(scanout_render_formats),
 153                              &metadata, scanout_and_render);
 154
 155         metadata.tiling = I915_TILING_Y;
 156         metadata.priority = 3;
 157         metadata.modifier = I915_FORMAT_MOD_Y_TILED;
 158
 159         scanout_and_render =
 160             unset_flags(scanout_and_render, BO_USE_SW_READ_RARELY | BO_USE_SW_WRITE_RARELY);
 161 /* Support y-tiled NV12 and P010 for libva */
 162 #ifdef I915_SCANOUT_Y_TILED
 163         uint64_t nv12_usage =
 164             BO_USE_TEXTURE | BO_USE_HW_VIDEO_DECODER | BO_USE_SCANOUT | hw_protected;
 165         uint64_t p010_usage = BO_USE_TEXTURE | BO_USE_HW_VIDEO_DECODER | hw_protected;
 166 #else
 167         uint64_t nv12_usage = BO_USE_TEXTURE | BO_USE_HW_VIDEO_DECODER;
 168         uint64_t p010_usage = nv12_usage;
 169 #endif
 170         drv_add_combination(drv, DRM_FORMAT_NV12, &metadata, nv12_usage);
 171         drv_add_combination(drv, DRM_FORMAT_P010, &metadata, p010_usage);
 172
 173         scanout_and_render = unset_flags(scanout_and_render, BO_USE_SCANOUT);
 174
 175         drv_add_combinations(drv, render_formats, ARRAY_SIZE(render_formats), &metadata, render);
 176         drv_add_combinations(drv, scanout_render_formats, ARRAY_SIZE(scanout_render_formats),
 177                              &metadata, scanout_and_render);
 178         return 0;
 179 }
 180
 181 static int i915_align_dimensions(struct bo *bo, uint32_t tiling, uint32_t *stride,
 182                                  uint32_t *aligned_height)
 183 {
 184         struct i915_device *i915 = bo->drv->priv;
 185         uint32_t horizontal_alignment;
 186         uint32_t vertical_alignment;
 187
 188         switch (tiling) {
 189         default:
 190         case I915_TILING_NONE:
 191                 /*
 192                  * The Intel GPU doesn't need any alignment in linear mode,
 193                  * but libva requires the allocation stride to be aligned to
 194                  * 16 bytes and height to 4 rows. Further, we round up the
 195                  * horizontal alignment so that row start on a cache line (64
 196                  * bytes).
 197                  */
 198 #ifdef LINEAR_ALIGN_256
 199                 /*
 200                  * If we want to import these buffers to amdgpu they need to
 201                  * their match LINEAR_ALIGNED requirement of 256 byte alignement.
 202                  */
 203                 horizontal_alignment = 256;
 204 #else
 205                 horizontal_alignment = 64;
 206 #endif
 207                 vertical_alignment = 4;
 208                 break;
 209
 210         case I915_TILING_X:
 211                 horizontal_alignment = 512;
 212                 vertical_alignment = 8;
 213                 break;
 214
 215         case I915_TILING_Y:
 216                 if (i915->gen == 3) {
 217                         horizontal_alignment = 512;
 218                         vertical_alignment = 8;
 219                 } else {
 220                         horizontal_alignment = 128;
 221                         vertical_alignment = 32;
 222                 }
 223                 break;
 224         }
 225
 226         *aligned_height = ALIGN(*aligned_height, vertical_alignment);
 227         if (i915->gen > 3) {
 228                 *stride = ALIGN(*stride, horizontal_alignment);
 229         } else {
 230                 while (*stride > horizontal_alignment)
 231                         horizontal_alignment <<= 1;
 232
 233                 *stride = horizontal_alignment;
 234         }
 235
 236         if (i915->gen <= 3 && *stride > 8192)
 237                 return -EINVAL;
 238
 239         return 0;
 240 }
 241
 242 static void i915_clflush(void *start, size_t size)
 243 {
 244         void *p = (void *)(((uintptr_t)start) & ~I915_CACHELINE_MASK);
 245         void *end = (void *)((uintptr_t)start + size);
 246
 247         __builtin_ia32_mfence();
 248         while (p < end) {
 249                 __builtin_ia32_clflush(p);
 250                 p = (void *)((uintptr_t)p + I915_CACHELINE_SIZE);
 251         }
 252 }
 253
 254 static int i915_init(struct driver *drv)
 255 {
 256         int ret;
 257         int device_id;
 258         struct i915_device *i915;
 259         drm_i915_getparam_t get_param = { 0 };
 260
 261         i915 = calloc(1, sizeof(*i915));
 262         if (!i915)
 263                 return -ENOMEM;
 264
 265         get_param.param = I915_PARAM_CHIPSET_ID;
 266         get_param.value = &device_id;
 267         ret = drmIoctl(drv->fd, DRM_IOCTL_I915_GETPARAM, &get_param);
 268         if (ret) {
 269                 drv_log("Failed to get I915_PARAM_CHIPSET_ID\n");
 270                 free(i915);
 271                 return -EINVAL;
 272         }
 273
 274         i915->gen = i915_get_gen(device_id);
 275         i915_get_modifier_order(i915);
 276
 277         memset(&get_param, 0, sizeof(get_param));
 278         get_param.param = I915_PARAM_HAS_LLC;
 279         get_param.value = &i915->has_llc;
 280         ret = drmIoctl(drv->fd, DRM_IOCTL_I915_GETPARAM, &get_param);
 281         if (ret) {
 282                 drv_log("Failed to get I915_PARAM_HAS_LLC\n");
 283                 free(i915);
 284                 return -EINVAL;
 285         }
 286
 287         if (i915->gen >= 12)
 288                 i915->has_hw_protection = 1;
 289
 290         drv->priv = i915;
 291         return i915_add_combinations(drv);
 292 }
 293
 294 static int i915_bo_from_format(struct bo *bo, uint32_t width, uint32_t height, uint32_t format)
 295 {
 296         uint32_t offset;
 297         size_t plane;
 298         int ret, pagesize;
 299
 300         offset = 0;
 301         pagesize = getpagesize();
 302         for (plane = 0; plane < drv_num_planes_from_format(format); plane++) {
 303                 uint32_t stride = drv_stride_from_format(format, width, plane);
 304                 uint32_t plane_height = drv_height_from_format(format, height, plane);
 305
 306                 if (bo->meta.tiling != I915_TILING_NONE)
 307                         assert(IS_ALIGNED(offset, pagesize));
 308
 309                 ret = i915_align_dimensions(bo, bo->meta.tiling, &stride, &plane_height);
 310                 if (ret)
 311                         return ret;
 312
 313                 bo->meta.strides[plane] = stride;
 314                 bo->meta.sizes[plane] = stride * plane_height;
 315                 bo->meta.offsets[plane] = offset;
 316                 offset += bo->meta.sizes[plane];
 317         }
 318
 319         bo->meta.total_size = ALIGN(offset, pagesize);
 320
 321         return 0;
 322 }
 323
 324 static int i915_bo_compute_metadata(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
 325                                     uint64_t use_flags, const uint64_t *modifiers, uint32_t count)
 326 {
 327         uint64_t modifier;
 328         struct i915_device *i915 = bo->drv->priv;
 329         bool huge_bo = (i915->gen < 11) && (width > 4096);
 330
 331         if (modifiers) {
 332                 modifier =
 333                     drv_pick_modifier(modifiers, count, i915->modifier.order, i915->modifier.count);
 334         } else {
 335                 struct combination *combo = drv_get_combination(bo->drv, format, use_flags);
 336                 if (!combo)
 337                         return -EINVAL;
 338                 modifier = combo->metadata.modifier;
 339         }
 340
 341         /*
 342          * i915 only supports linear/x-tiled above 4096 wide on Gen9/Gen10 GPU.
 343          * VAAPI decode in NV12 Y tiled format so skip modifier change for NV12/P010 huge bo.
 344          */
 345         if (huge_bo && format != DRM_FORMAT_NV12 && format != DRM_FORMAT_P010 &&
 346             modifier != I915_FORMAT_MOD_X_TILED && modifier != DRM_FORMAT_MOD_LINEAR) {
 347                 uint32_t i;
 348                 for (i = 0; modifiers && i < count; i++) {
 349                         if (modifiers[i] == I915_FORMAT_MOD_X_TILED)
 350                                 break;
 351                 }
 352                 if (i == count)
 353                         modifier = DRM_FORMAT_MOD_LINEAR;
 354                 else
 355                         modifier = I915_FORMAT_MOD_X_TILED;
 356         }
 357
 358         /*
 359          * Skip I915_FORMAT_MOD_Y_TILED_CCS modifier if compression is disabled
 360          * Pick y tiled modifier if it has been passed in, otherwise use linear
 361          */
 362         if (!bo->drv->compression && modifier == I915_FORMAT_MOD_Y_TILED_CCS) {
 363                 uint32_t i;
 364                 for (i = 0; modifiers && i < count; i++) {
 365                         if (modifiers[i] == I915_FORMAT_MOD_Y_TILED)
 366                                 break;
 367                 }
 368                 if (i == count)
 369                         modifier = DRM_FORMAT_MOD_LINEAR;
 370                 else
 371                         modifier = I915_FORMAT_MOD_Y_TILED;
 372         }
 373
 374         switch (modifier) {
 375         case DRM_FORMAT_MOD_LINEAR:
 376                 bo->meta.tiling = I915_TILING_NONE;
 377                 break;
 378         case I915_FORMAT_MOD_X_TILED:
 379                 bo->meta.tiling = I915_TILING_X;
 380                 break;
 381         case I915_FORMAT_MOD_Y_TILED:
 382         case I915_FORMAT_MOD_Y_TILED_CCS:
 383                 bo->meta.tiling = I915_TILING_Y;
 384                 break;
 385         }
 386
 387         bo->meta.format_modifiers[0] = modifier;
 388
 389         if (format == DRM_FORMAT_YVU420_ANDROID) {
 390                 /*
 391                  * We only need to be able to use this as a linear texture,
 392                  * which doesn't put any HW restrictions on how we lay it
 393                  * out. The Android format does require the stride to be a
 394                  * multiple of 16 and expects the Cr and Cb stride to be
 395                  * ALIGN(Y_stride / 2, 16), which we can make happen by
 396                  * aligning to 32 bytes here.
 397                  */
 398                 uint32_t stride = ALIGN(width, 32);
 399                 drv_bo_from_format(bo, stride, height, format);
 400         } else if (modifier == I915_FORMAT_MOD_Y_TILED_CCS) {
 401                 /*
 402                  * For compressed surfaces, we need a color control surface
 403                  * (CCS). Color compression is only supported for Y tiled
 404                  * surfaces, and for each 32x16 tiles in the main surface we
 405                  * need a tile in the control surface.  Y tiles are 128 bytes
 406                  * wide and 32 lines tall and we use that to first compute the
 407                  * width and height in tiles of the main surface. stride and
 408                  * height are already multiples of 128 and 32, respectively:
 409                  */
 410                 uint32_t stride = drv_stride_from_format(format, width, 0);
 411                 uint32_t width_in_tiles = DIV_ROUND_UP(stride, 128);
 412                 uint32_t height_in_tiles = DIV_ROUND_UP(height, 32);
 413                 uint32_t size = width_in_tiles * height_in_tiles * 4096;
 414                 uint32_t offset = 0;
 415
 416                 bo->meta.strides[0] = width_in_tiles * 128;
 417                 bo->meta.sizes[0] = size;
 418                 bo->meta.offsets[0] = offset;
 419                 offset += size;
 420
 421                 /*
 422                  * Now, compute the width and height in tiles of the control
 423                  * surface by dividing and rounding up.
 424                  */
 425                 uint32_t ccs_width_in_tiles = DIV_ROUND_UP(width_in_tiles, 32);
 426                 uint32_t ccs_height_in_tiles = DIV_ROUND_UP(height_in_tiles, 16);
 427                 uint32_t ccs_size = ccs_width_in_tiles * ccs_height_in_tiles * 4096;
 428
 429                 /*
 430                  * With stride and height aligned to y tiles, offset is
 431                  * already a multiple of 4096, which is the required alignment
 432                  * of the CCS.
 433                  */
 434                 bo->meta.strides[1] = ccs_width_in_tiles * 128;
 435                 bo->meta.sizes[1] = ccs_size;
 436                 bo->meta.offsets[1] = offset;
 437                 offset += ccs_size;
 438
 439                 bo->meta.num_planes = 2;
 440                 bo->meta.total_size = offset;
 441         } else {
 442                 i915_bo_from_format(bo, width, height, format);
 443         }
 444         return 0;
 445 }
 446
 447 static int i915_bo_create_from_metadata(struct bo *bo)
 448 {
 449         int ret;
 450         size_t plane;
 451         uint32_t gem_handle;
 452         struct drm_i915_gem_set_tiling gem_set_tiling = { 0 };
 453         struct i915_device *i915 = bo->drv->priv;
 454
 455         if (i915->has_hw_protection && (bo->meta.use_flags & BO_USE_PROTECTED)) {
 456                 struct drm_i915_gem_object_param protected_param = {
 457                         .param = I915_OBJECT_PARAM | I915_PARAM_PROTECTED_CONTENT,
 458                         .data = 1,
 459                 };
 460
 461                 struct drm_i915_gem_create_ext_setparam setparam_protected = {
 462                         .base = { .name = I915_GEM_CREATE_EXT_SETPARAM },
 463                         .param = protected_param,
 464                 };
 465
 466                 struct drm_i915_gem_create_ext create_ext = {
 467                         .size = bo->meta.total_size,
 468                         .extensions = (uintptr_t)&setparam_protected,
 469                 };
 470
 471                 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_CREATE_EXT, &create_ext);
 472                 if (ret) {
 473                         drv_log("DRM_IOCTL_I915_GEM_CREATE_EXT failed (size=%llu)\n",
 474                                 create_ext.size);
 475                         return -errno;
 476                 }
 477
 478                 gem_handle = create_ext.handle;
 479         } else {
 480                 struct drm_i915_gem_create gem_create = { 0 };
 481                 gem_create.size = bo->meta.total_size;
 482                 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_CREATE, &gem_create);
 483                 if (ret) {
 484                         drv_log("DRM_IOCTL_I915_GEM_CREATE failed (size=%llu)\n", gem_create.size);
 485                         return -errno;
 486                 }
 487
 488                 gem_handle = gem_create.handle;
 489         }
 490
 491         for (plane = 0; plane < bo->meta.num_planes; plane++)
 492                 bo->handles[plane].u32 = gem_handle;
 493
 494         gem_set_tiling.handle = bo->handles[0].u32;
 495         gem_set_tiling.tiling_mode = bo->meta.tiling;
 496         gem_set_tiling.stride = bo->meta.strides[0];
 497
 498         ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_SET_TILING, &gem_set_tiling);
 499         if (ret) {
 500                 struct drm_gem_close gem_close = { 0 };
 501                 gem_close.handle = bo->handles[0].u32;
 502                 drmIoctl(bo->drv->fd, DRM_IOCTL_GEM_CLOSE, &gem_close);
 503
 504                 drv_log("DRM_IOCTL_I915_GEM_SET_TILING failed with %d\n", errno);
 505                 return -errno;
 506         }
 507
 508         return 0;
 509 }
 510
 511 static void i915_close(struct driver *drv)
 512 {
 513         free(drv->priv);
 514         drv->priv = NULL;
 515 }
 516
 517 static int i915_bo_import(struct bo *bo, struct drv_import_fd_data *data)
 518 {
 519         int ret;
 520         struct drm_i915_gem_get_tiling gem_get_tiling = { 0 };
 521
 522         ret = drv_prime_bo_import(bo, data);
 523         if (ret)
 524                 return ret;
 525
 526         /* TODO(gsingh): export modifiers and get rid of backdoor tiling. */
 527         gem_get_tiling.handle = bo->handles[0].u32;
 528
 529         ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_GET_TILING, &gem_get_tiling);
 530         if (ret) {
 531                 drv_gem_bo_destroy(bo);
 532                 drv_log("DRM_IOCTL_I915_GEM_GET_TILING failed.\n");
 533                 return ret;
 534         }
 535
 536         bo->meta.tiling = gem_get_tiling.tiling_mode;
 537         return 0;
 538 }
 539
 540 static void *i915_bo_map(struct bo *bo, struct vma *vma, size_t plane, uint32_t map_flags)
 541 {
 542         int ret;
 543         void *addr = MAP_FAILED;
 544
 545         if (bo->meta.format_modifiers[0] == I915_FORMAT_MOD_Y_TILED_CCS)
 546                 return MAP_FAILED;
 547
 548         if (bo->meta.tiling == I915_TILING_NONE) {
 549                 struct drm_i915_gem_mmap gem_map = { 0 };
 550                 /* TODO(b/118799155): We don't seem to have a good way to
 551                  * detect the use cases for which WC mapping is really needed.
 552                  * The current heuristic seems overly coarse and may be slowing
 553                  * down some other use cases unnecessarily.
 554                  *
 555                  * For now, care must be taken not to use WC mappings for
 556                  * Renderscript and camera use cases, as they're
 557                  * performance-sensitive. */
 558                 if ((bo->meta.use_flags & BO_USE_SCANOUT) &&
 559                     !(bo->meta.use_flags &
 560                       (BO_USE_RENDERSCRIPT | BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE)))
 561                         gem_map.flags = I915_MMAP_WC;
 562
 563                 gem_map.handle = bo->handles[0].u32;
 564                 gem_map.offset = 0;
 565                 gem_map.size = bo->meta.total_size;
 566
 567                 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_MMAP, &gem_map);
 568                 /* DRM_IOCTL_I915_GEM_MMAP mmaps the underlying shm
 569                  * file and returns a user space address directly, ie,
 570                  * doesn't go through mmap. If we try that on a
 571                  * dma-buf that doesn't have a shm file, i915.ko
 572                  * returns ENXIO.  Fall through to
 573                  * DRM_IOCTL_I915_GEM_MMAP_GTT in that case, which
 574                  * will mmap on the drm fd instead. */
 575                 if (ret == 0)
 576                         addr = (void *)(uintptr_t)gem_map.addr_ptr;
 577         }
 578
 579         if (addr == MAP_FAILED) {
 580                 struct drm_i915_gem_mmap_gtt gem_map = { 0 };
 581
 582                 gem_map.handle = bo->handles[0].u32;
 583                 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_MMAP_GTT, &gem_map);
 584                 if (ret) {
 585                         drv_log("DRM_IOCTL_I915_GEM_MMAP_GTT failed\n");
 586                         return MAP_FAILED;
 587                 }
 588
 589                 addr = mmap(0, bo->meta.total_size, drv_get_prot(map_flags), MAP_SHARED,
 590                             bo->drv->fd, gem_map.offset);
 591         }
 592
 593         if (addr == MAP_FAILED) {
 594                 drv_log("i915 GEM mmap failed\n");
 595                 return addr;
 596         }
 597
 598         vma->length = bo->meta.total_size;
 599         return addr;
 600 }
 601
 602 static int i915_bo_invalidate(struct bo *bo, struct mapping *mapping)
 603 {
 604         int ret;
 605         struct drm_i915_gem_set_domain set_domain = { 0 };
 606
 607         set_domain.handle = bo->handles[0].u32;
 608         if (bo->meta.tiling == I915_TILING_NONE) {
 609                 set_domain.read_domains = I915_GEM_DOMAIN_CPU;
 610                 if (mapping->vma->map_flags & BO_MAP_WRITE)
 611                         set_domain.write_domain = I915_GEM_DOMAIN_CPU;
 612         } else {
 613                 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
 614                 if (mapping->vma->map_flags & BO_MAP_WRITE)
 615                         set_domain.write_domain = I915_GEM_DOMAIN_GTT;
 616         }
 617
 618         ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_SET_DOMAIN, &set_domain);
 619         if (ret) {
 620                 drv_log("DRM_IOCTL_I915_GEM_SET_DOMAIN with %d\n", ret);
 621                 return ret;
 622         }
 623
 624         return 0;
 625 }
 626
 627 static int i915_bo_flush(struct bo *bo, struct mapping *mapping)
 628 {
 629         struct i915_device *i915 = bo->drv->priv;
 630         if (!i915->has_llc && bo->meta.tiling == I915_TILING_NONE)
 631                 i915_clflush(mapping->vma->addr, mapping->vma->length);
 632
 633         return 0;
 634 }
 635
 636 static uint32_t i915_resolve_format(struct driver *drv, uint32_t format, uint64_t use_flags)
 637 {
 638         switch (format) {
 639         case DRM_FORMAT_FLEX_IMPLEMENTATION_DEFINED:
 640                 /* KBL camera subsystem requires NV12. */
 641                 if (use_flags & (BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE))
 642                         return DRM_FORMAT_NV12;
 643                 /*HACK: See b/28671744 */
 644                 return DRM_FORMAT_XBGR8888;
 645         case DRM_FORMAT_FLEX_YCbCr_420_888:
 646                 /*
 647                  * KBL camera subsystem requires NV12. Our other use cases
 648                  * don't care:
 649                  * - Hardware video supports NV12,
 650                  * - USB Camera HALv3 supports NV12,
 651                  * - USB Camera HALv1 doesn't use this format.
 652                  * Moreover, NV12 is preferred for video, due to overlay
 653                  * support on SKL+.
 654                  */
 655                 return DRM_FORMAT_NV12;
 656         default:
 657                 return format;
 658         }
 659 }
 660
 661 const struct backend backend_i915 = {
 662         .name = "i915",
 663         .init = i915_init,
 664         .close = i915_close,
 665         .bo_compute_metadata = i915_bo_compute_metadata,
 666         .bo_create_from_metadata = i915_bo_create_from_metadata,
 667         .bo_destroy = drv_gem_bo_destroy,
 668         .bo_import = i915_bo_import,
 669         .bo_map = i915_bo_map,
 670         .bo_unmap = drv_bo_munmap,
 671         .bo_invalidate = i915_bo_invalidate,
 672         .bo_flush = i915_bo_flush,
 673         .resolve_format = i915_resolve_format,
 674 };
 675
 676 #endif