2 * Copyright 2014 The Chromium OS Authors. All rights reserved.
3 * Use of this source code is governed by a BSD-style license that can be
4 * found in the LICENSE file.
20 #define I915_CACHELINE_SIZE 64
21 #define I915_CACHELINE_MASK (I915_CACHELINE_SIZE - 1)
23 static const uint32_t render_target_formats[] = { DRM_FORMAT_ARGB1555, DRM_FORMAT_ABGR8888,
24 DRM_FORMAT_ARGB8888, DRM_FORMAT_RGB565,
25 DRM_FORMAT_XBGR8888, DRM_FORMAT_XRGB1555,
26 DRM_FORMAT_XRGB8888 };
28 static const uint32_t tileable_texture_source_formats[] = { DRM_FORMAT_GR88, DRM_FORMAT_R8,
29 DRM_FORMAT_UYVY, DRM_FORMAT_YUYV };
31 static const uint32_t texture_source_formats[] = { DRM_FORMAT_YVU420, DRM_FORMAT_YVU420_ANDROID };
38 static uint32_t i915_get_gen(int device_id)
40 const uint16_t gen3_ids[] = { 0x2582, 0x2592, 0x2772, 0x27A2, 0x27AE,
41 0x29C2, 0x29B2, 0x29D2, 0xA001, 0xA011 };
43 for (i = 0; i < ARRAY_SIZE(gen3_ids); i++)
44 if (gen3_ids[i] == device_id)
50 static int i915_add_kms_item(struct driver *drv, const struct kms_item *item)
53 struct combination *combo;
56 * Older hardware can't scanout Y-tiled formats. Newer devices can, and
57 * report this functionality via format modifiers.
59 for (i = 0; i < drv->backend->combos.size; i++) {
60 combo = &drv->backend->combos.data[i];
61 if (combo->format == item->format) {
62 if ((combo->metadata.tiling == I915_TILING_Y &&
63 item->modifier == I915_FORMAT_MOD_Y_TILED) ||
64 (combo->metadata.tiling == I915_TILING_X &&
65 item->modifier == I915_FORMAT_MOD_X_TILED)) {
66 combo->metadata.modifier = item->modifier;
67 combo->usage |= item->usage;
68 } else if (combo->metadata.tiling != I915_TILING_Y) {
69 combo->usage |= item->usage;
77 static int i915_add_combinations(struct driver *drv)
80 uint32_t i, num_items;
81 struct kms_item *items;
82 struct format_metadata metadata;
83 uint64_t render_flags, texture_flags;
85 render_flags = BO_USE_RENDER_MASK;
86 texture_flags = BO_USE_TEXTURE_MASK;
88 metadata.tiling = I915_TILING_NONE;
89 metadata.priority = 1;
90 metadata.modifier = DRM_FORMAT_MOD_NONE;
92 ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
93 &metadata, render_flags);
97 ret = drv_add_combinations(drv, texture_source_formats, ARRAY_SIZE(texture_source_formats),
98 &metadata, texture_flags);
102 ret = drv_add_combinations(drv, tileable_texture_source_formats,
103 ARRAY_SIZE(tileable_texture_source_formats), &metadata,
108 drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
109 drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
111 render_flags &= ~BO_USE_SW_WRITE_OFTEN;
112 render_flags &= ~BO_USE_SW_READ_OFTEN;
113 render_flags &= ~BO_USE_LINEAR;
115 texture_flags &= ~BO_USE_SW_WRITE_OFTEN;
116 texture_flags &= ~BO_USE_SW_READ_OFTEN;
117 texture_flags &= ~BO_USE_LINEAR;
119 metadata.tiling = I915_TILING_X;
120 metadata.priority = 2;
122 ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
123 &metadata, render_flags);
127 ret = drv_add_combinations(drv, tileable_texture_source_formats,
128 ARRAY_SIZE(tileable_texture_source_formats), &metadata,
133 metadata.tiling = I915_TILING_Y;
134 metadata.priority = 3;
136 ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
137 &metadata, render_flags);
141 ret = drv_add_combinations(drv, tileable_texture_source_formats,
142 ARRAY_SIZE(tileable_texture_source_formats), &metadata,
147 items = drv_query_kms(drv, &num_items);
148 if (!items || !num_items)
151 for (i = 0; i < num_items; i++) {
152 ret = i915_add_kms_item(drv, &items[i]);
163 static int i915_align_dimensions(struct bo *bo, uint32_t tiling, uint32_t *stride,
164 uint32_t *aligned_height)
166 struct i915_device *i915 = bo->drv->priv;
167 uint32_t horizontal_alignment = 4;
168 uint32_t vertical_alignment = 4;
172 case I915_TILING_NONE:
173 horizontal_alignment = 64;
177 horizontal_alignment = 512;
178 vertical_alignment = 8;
182 if (i915->gen == 3) {
183 horizontal_alignment = 512;
184 vertical_alignment = 8;
186 horizontal_alignment = 128;
187 vertical_alignment = 32;
192 *aligned_height = ALIGN(bo->height, vertical_alignment);
194 *stride = ALIGN(*stride, horizontal_alignment);
196 while (*stride > horizontal_alignment)
197 horizontal_alignment <<= 1;
199 *stride = horizontal_alignment;
202 if (i915->gen <= 3 && *stride > 8192)
208 static void i915_clflush(void *start, size_t size)
210 void *p = (void *)(((uintptr_t)start) & ~I915_CACHELINE_MASK);
211 void *end = (void *)((uintptr_t)start + size);
213 __builtin_ia32_mfence();
215 __builtin_ia32_clflush(p);
216 p = (void *)((uintptr_t)p + I915_CACHELINE_SIZE);
220 static int i915_init(struct driver *drv)
224 struct i915_device *i915;
225 drm_i915_getparam_t get_param;
227 i915 = calloc(1, sizeof(*i915));
231 memset(&get_param, 0, sizeof(get_param));
232 get_param.param = I915_PARAM_CHIPSET_ID;
233 get_param.value = &device_id;
234 ret = drmIoctl(drv->fd, DRM_IOCTL_I915_GETPARAM, &get_param);
236 fprintf(stderr, "drv: Failed to get I915_PARAM_CHIPSET_ID\n");
241 i915->gen = i915_get_gen(device_id);
243 memset(&get_param, 0, sizeof(get_param));
244 get_param.param = I915_PARAM_HAS_LLC;
245 get_param.value = &i915->has_llc;
246 ret = drmIoctl(drv->fd, DRM_IOCTL_I915_GETPARAM, &get_param);
248 fprintf(stderr, "drv: Failed to get I915_PARAM_HAS_LLC\n");
255 return i915_add_combinations(drv);
258 static int i915_bo_create(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
264 struct drm_i915_gem_create gem_create;
265 struct drm_i915_gem_set_tiling gem_set_tiling;
267 if (flags & (BO_USE_CURSOR | BO_USE_LINEAR | BO_USE_SW_READ_OFTEN | BO_USE_SW_WRITE_OFTEN))
268 bo->tiling = I915_TILING_NONE;
269 else if (flags & BO_USE_SCANOUT)
270 bo->tiling = I915_TILING_X;
272 bo->tiling = I915_TILING_Y;
274 if (format == DRM_FORMAT_YVU420 || format == DRM_FORMAT_YVU420_ANDROID)
275 bo->tiling = I915_TILING_NONE;
277 stride = drv_stride_from_format(format, width, 0);
279 ret = i915_align_dimensions(bo, bo->tiling, &stride, &height);
284 * Align the Y plane to 128 bytes so the chroma planes would be aligned
285 * to 64 byte boundaries. This is an Intel HW requirement.
287 if (format == DRM_FORMAT_YVU420)
288 stride = ALIGN(stride, 128);
291 * HAL_PIXEL_FORMAT_YV12 requires that the buffer's height not be aligned.
293 if (format == DRM_FORMAT_YVU420_ANDROID)
296 drv_bo_from_format(bo, stride, height, format);
298 memset(&gem_create, 0, sizeof(gem_create));
299 gem_create.size = bo->total_size;
301 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_CREATE, &gem_create);
303 fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_CREATE failed (size=%llu)\n",
308 for (plane = 0; plane < bo->num_planes; plane++)
309 bo->handles[plane].u32 = gem_create.handle;
311 memset(&gem_set_tiling, 0, sizeof(gem_set_tiling));
312 gem_set_tiling.handle = bo->handles[0].u32;
313 gem_set_tiling.tiling_mode = bo->tiling;
314 gem_set_tiling.stride = bo->strides[0];
316 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_SET_TILING, &gem_set_tiling);
318 struct drm_gem_close gem_close;
319 memset(&gem_close, 0, sizeof(gem_close));
320 gem_close.handle = bo->handles[0].u32;
321 drmIoctl(bo->drv->fd, DRM_IOCTL_GEM_CLOSE, &gem_close);
323 fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_SET_TILING failed with %d", errno);
330 static void i915_close(struct driver *drv)
336 static int i915_bo_import(struct bo *bo, struct drv_import_fd_data *data)
339 struct drm_i915_gem_get_tiling gem_get_tiling;
341 ret = drv_prime_bo_import(bo, data);
345 /* TODO(gsingh): export modifiers and get rid of backdoor tiling. */
346 memset(&gem_get_tiling, 0, sizeof(gem_get_tiling));
347 gem_get_tiling.handle = bo->handles[0].u32;
349 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_GET_TILING, &gem_get_tiling);
351 fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_GET_TILING failed.");
355 bo->tiling = gem_get_tiling.tiling_mode;
359 static void *i915_bo_map(struct bo *bo, struct map_info *data, size_t plane)
363 struct drm_i915_gem_set_domain set_domain;
365 memset(&set_domain, 0, sizeof(set_domain));
366 set_domain.handle = bo->handles[0].u32;
367 if (bo->tiling == I915_TILING_NONE) {
368 struct drm_i915_gem_mmap gem_map;
369 memset(&gem_map, 0, sizeof(gem_map));
371 gem_map.handle = bo->handles[0].u32;
373 gem_map.size = bo->total_size;
375 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_MMAP, &gem_map);
377 fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_MMAP failed\n");
381 addr = (void *)(uintptr_t)gem_map.addr_ptr;
382 set_domain.read_domains = I915_GEM_DOMAIN_CPU;
383 set_domain.write_domain = I915_GEM_DOMAIN_CPU;
386 struct drm_i915_gem_mmap_gtt gem_map;
387 memset(&gem_map, 0, sizeof(gem_map));
389 gem_map.handle = bo->handles[0].u32;
391 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_MMAP_GTT, &gem_map);
393 fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_MMAP_GTT failed\n");
397 addr = mmap(0, bo->total_size, PROT_READ | PROT_WRITE, MAP_SHARED, bo->drv->fd,
400 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
401 set_domain.write_domain = I915_GEM_DOMAIN_GTT;
404 if (addr == MAP_FAILED) {
405 fprintf(stderr, "drv: i915 GEM mmap failed\n");
409 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_SET_DOMAIN, &set_domain);
411 fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_SET_DOMAIN failed\n");
415 data->length = bo->total_size;
419 static int i915_bo_unmap(struct bo *bo, struct map_info *data)
421 struct i915_device *i915 = bo->drv->priv;
422 if (!i915->has_llc && bo->tiling == I915_TILING_NONE)
423 i915_clflush(data->addr, data->length);
425 return munmap(data->addr, data->length);
428 static uint32_t i915_resolve_format(uint32_t format)
431 case DRM_FORMAT_FLEX_IMPLEMENTATION_DEFINED:
432 /*HACK: See b/28671744 */
433 return DRM_FORMAT_XBGR8888;
434 case DRM_FORMAT_FLEX_YCbCr_420_888:
435 return DRM_FORMAT_YVU420;
441 struct backend backend_i915 = {
445 .bo_create = i915_bo_create,
446 .bo_destroy = drv_gem_bo_destroy,
447 .bo_import = i915_bo_import,
448 .bo_map = i915_bo_map,
449 .bo_unmap = i915_bo_unmap,
450 .resolve_format = i915_resolve_format,