i915.c

   1 /*
   2  * Copyright 2014 The Chromium OS Authors. All rights reserved.
   3  * Use of this source code is governed by a BSD-style license that can be
   4  * found in the LICENSE file.
   5  */
   6
   7 #ifdef DRV_I915
   8
   9 #include <errno.h>
  10 #include <i915_drm.h>
  11 #include <stdio.h>
  12 #include <string.h>
  13 #include <sys/mman.h>
  14 #include <xf86drm.h>
  15
  16 #include "drv_priv.h"
  17 #include "helpers.h"
  18 #include "util.h"
  19
  20 #define I915_CACHELINE_SIZE 64
  21 #define I915_CACHELINE_MASK (I915_CACHELINE_SIZE - 1)
  22
  23 static const uint32_t render_target_formats[] = { DRM_FORMAT_ARGB1555, DRM_FORMAT_ABGR8888,
  24                                                   DRM_FORMAT_ARGB8888, DRM_FORMAT_RGB565,
  25                                                   DRM_FORMAT_XBGR8888, DRM_FORMAT_XRGB1555,
  26                                                   DRM_FORMAT_XRGB8888 };
  27
  28 static const uint32_t tileable_texture_source_formats[] = { DRM_FORMAT_GR88, DRM_FORMAT_NV12,
  29                                                             DRM_FORMAT_R8, DRM_FORMAT_UYVY,
  30                                                             DRM_FORMAT_YUYV };
  31
  32 static const uint32_t texture_source_formats[] = { DRM_FORMAT_YVU420, DRM_FORMAT_YVU420_ANDROID };
  33
  34 struct i915_device {
  35         uint32_t gen;
  36         int32_t has_llc;
  37 };
  38
  39 static uint32_t i915_get_gen(int device_id)
  40 {
  41         const uint16_t gen3_ids[] = { 0x2582, 0x2592, 0x2772, 0x27A2, 0x27AE,
  42                                       0x29C2, 0x29B2, 0x29D2, 0xA001, 0xA011 };
  43         unsigned i;
  44         for (i = 0; i < ARRAY_SIZE(gen3_ids); i++)
  45                 if (gen3_ids[i] == device_id)
  46                         return 3;
  47
  48         return 4;
  49 }
  50
  51 static int i915_add_kms_item(struct driver *drv, const struct kms_item *item)
  52 {
  53         uint32_t i;
  54         struct combination *combo;
  55
  56         /*
  57          * Older hardware can't scanout Y-tiled formats. Newer devices can, and
  58          * report this functionality via format modifiers.
  59          */
  60         for (i = 0; i < drv->backend->combos.size; i++) {
  61                 combo = &drv->backend->combos.data[i];
  62                 if (combo->format != item->format)
  63                         continue;
  64
  65                 if (item->modifier == DRM_FORMAT_MOD_NONE &&
  66                     combo->metadata.tiling == I915_TILING_X) {
  67                         /*
  68                          * FIXME: drv_query_kms() does not report the available modifiers
  69                          * yet, but we know that all hardware can scanout from X-tiled
  70                          * buffers, so let's add this to our combinations, except for
  71                          * cursor, which must not be tiled.
  72                          */
  73                         combo->usage |= item->usage & ~BO_USE_CURSOR;
  74                 }
  75
  76                 if (combo->metadata.modifier == item->modifier)
  77                         combo->usage |= item->usage;
  78         }
  79
  80         return 0;
  81 }
  82
  83 static int i915_add_combinations(struct driver *drv)
  84 {
  85         int ret;
  86         uint32_t i, num_items;
  87         struct kms_item *items;
  88         struct format_metadata metadata;
  89         uint64_t render_flags, texture_flags;
  90
  91         render_flags = BO_USE_RENDER_MASK;
  92         texture_flags = BO_USE_TEXTURE_MASK;
  93
  94         metadata.tiling = I915_TILING_NONE;
  95         metadata.priority = 1;
  96         metadata.modifier = DRM_FORMAT_MOD_NONE;
  97
  98         ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
  99                                    &metadata, render_flags);
 100         if (ret)
 101                 return ret;
 102
 103         ret = drv_add_combinations(drv, texture_source_formats, ARRAY_SIZE(texture_source_formats),
 104                                    &metadata, texture_flags);
 105         if (ret)
 106                 return ret;
 107
 108         ret = drv_add_combinations(drv, tileable_texture_source_formats,
 109                                    ARRAY_SIZE(tileable_texture_source_formats), &metadata,
 110                                    texture_flags);
 111         if (ret)
 112                 return ret;
 113
 114         drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
 115         drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
 116
 117         /* IPU3 camera ISP supports only NV12 output. */
 118         drv_modify_combination(drv, DRM_FORMAT_NV12, &metadata,
 119                                BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE);
 120         /*
 121          * R8 format is used for Android's HAL_PIXEL_FORMAT_BLOB and is used for JPEG snapshots
 122          * from camera.
 123          */
 124         drv_modify_combination(drv, DRM_FORMAT_R8, &metadata,
 125                                BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE);
 126
 127         render_flags &= ~BO_USE_SW_WRITE_OFTEN;
 128         render_flags &= ~BO_USE_SW_READ_OFTEN;
 129         render_flags &= ~BO_USE_LINEAR;
 130
 131         texture_flags &= ~BO_USE_SW_WRITE_OFTEN;
 132         texture_flags &= ~BO_USE_SW_READ_OFTEN;
 133         texture_flags &= ~BO_USE_LINEAR;
 134
 135         metadata.tiling = I915_TILING_X;
 136         metadata.priority = 2;
 137         metadata.modifier = I915_FORMAT_MOD_X_TILED;
 138
 139         ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
 140                                    &metadata, render_flags);
 141         if (ret)
 142                 return ret;
 143
 144         ret = drv_add_combinations(drv, tileable_texture_source_formats,
 145                                    ARRAY_SIZE(tileable_texture_source_formats), &metadata,
 146                                    texture_flags);
 147         if (ret)
 148                 return ret;
 149
 150         metadata.tiling = I915_TILING_Y;
 151         metadata.priority = 3;
 152         metadata.modifier = I915_FORMAT_MOD_Y_TILED;
 153
 154         ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
 155                                    &metadata, render_flags);
 156         if (ret)
 157                 return ret;
 158
 159         ret = drv_add_combinations(drv, tileable_texture_source_formats,
 160                                    ARRAY_SIZE(tileable_texture_source_formats), &metadata,
 161                                    texture_flags);
 162         if (ret)
 163                 return ret;
 164
 165         items = drv_query_kms(drv, &num_items);
 166         if (!items || !num_items)
 167                 return 0;
 168
 169         for (i = 0; i < num_items; i++) {
 170                 ret = i915_add_kms_item(drv, &items[i]);
 171                 if (ret) {
 172                         free(items);
 173                         return ret;
 174                 }
 175         }
 176
 177         free(items);
 178         return 0;
 179 }
 180
 181 static int i915_align_dimensions(struct bo *bo, uint32_t tiling, uint32_t *stride,
 182                                  uint32_t *aligned_height)
 183 {
 184         struct i915_device *i915 = bo->drv->priv;
 185         uint32_t horizontal_alignment = 4;
 186         uint32_t vertical_alignment = 4;
 187
 188         switch (tiling) {
 189         default:
 190         case I915_TILING_NONE:
 191                 horizontal_alignment = 64;
 192                 break;
 193
 194         case I915_TILING_X:
 195                 horizontal_alignment = 512;
 196                 vertical_alignment = 8;
 197                 break;
 198
 199         case I915_TILING_Y:
 200                 if (i915->gen == 3) {
 201                         horizontal_alignment = 512;
 202                         vertical_alignment = 8;
 203                 } else {
 204                         horizontal_alignment = 128;
 205                         vertical_alignment = 32;
 206                 }
 207                 break;
 208         }
 209
 210         /*
 211          * The alignment calculated above is based on the full size luma plane and to have chroma
 212          * planes properly aligned with subsampled formats, we need to multiply luma alignment by
 213          * subsampling factor.
 214          */
 215         switch (bo->format) {
 216         case DRM_FORMAT_YVU420_ANDROID:
 217         case DRM_FORMAT_YVU420:
 218                 horizontal_alignment *= 2;
 219                 /* Fall through */
 220         case DRM_FORMAT_NV12:
 221                 vertical_alignment *= 2;
 222                 break;
 223         }
 224
 225         *aligned_height = ALIGN(bo->height, vertical_alignment);
 226         if (i915->gen > 3) {
 227                 *stride = ALIGN(*stride, horizontal_alignment);
 228         } else {
 229                 while (*stride > horizontal_alignment)
 230                         horizontal_alignment <<= 1;
 231
 232                 *stride = horizontal_alignment;
 233         }
 234
 235         if (i915->gen <= 3 && *stride > 8192)
 236                 return -EINVAL;
 237
 238         return 0;
 239 }
 240
 241 static void i915_clflush(void *start, size_t size)
 242 {
 243         void *p = (void *)(((uintptr_t)start) & ~I915_CACHELINE_MASK);
 244         void *end = (void *)((uintptr_t)start + size);
 245
 246         __builtin_ia32_mfence();
 247         while (p < end) {
 248                 __builtin_ia32_clflush(p);
 249                 p = (void *)((uintptr_t)p + I915_CACHELINE_SIZE);
 250         }
 251 }
 252
 253 static int i915_init(struct driver *drv)
 254 {
 255         int ret;
 256         int device_id;
 257         struct i915_device *i915;
 258         drm_i915_getparam_t get_param;
 259
 260         i915 = calloc(1, sizeof(*i915));
 261         if (!i915)
 262                 return -ENOMEM;
 263
 264         memset(&get_param, 0, sizeof(get_param));
 265         get_param.param = I915_PARAM_CHIPSET_ID;
 266         get_param.value = &device_id;
 267         ret = drmIoctl(drv->fd, DRM_IOCTL_I915_GETPARAM, &get_param);
 268         if (ret) {
 269                 fprintf(stderr, "drv: Failed to get I915_PARAM_CHIPSET_ID\n");
 270                 free(i915);
 271                 return -EINVAL;
 272         }
 273
 274         i915->gen = i915_get_gen(device_id);
 275
 276         memset(&get_param, 0, sizeof(get_param));
 277         get_param.param = I915_PARAM_HAS_LLC;
 278         get_param.value = &i915->has_llc;
 279         ret = drmIoctl(drv->fd, DRM_IOCTL_I915_GETPARAM, &get_param);
 280         if (ret) {
 281                 fprintf(stderr, "drv: Failed to get I915_PARAM_HAS_LLC\n");
 282                 free(i915);
 283                 return -EINVAL;
 284         }
 285
 286         drv->priv = i915;
 287
 288         return i915_add_combinations(drv);
 289 }
 290
 291 static int i915_bo_create(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
 292                           uint32_t flags)
 293 {
 294         int ret;
 295         size_t plane;
 296         uint32_t stride;
 297         struct drm_i915_gem_create gem_create;
 298         struct drm_i915_gem_set_tiling gem_set_tiling;
 299         struct combination *combo;
 300
 301         combo = drv_get_combination(bo->drv, format, flags);
 302         if (!combo)
 303                 return -EINVAL;
 304
 305         bo->tiling = combo->metadata.tiling;
 306
 307         stride = drv_stride_from_format(format, width, 0);
 308
 309         ret = i915_align_dimensions(bo, bo->tiling, &stride, &height);
 310         if (ret)
 311                 return ret;
 312
 313         /*
 314          * HAL_PIXEL_FORMAT_YV12 requires the buffer height not be aligned, but we need to keep
 315          * total size as with aligned height to ensure enough padding space after each plane to
 316          * satisfy GPU alignment requirements.
 317          *
 318          * We do it by first calling drv_bo_from_format() with aligned height and
 319          * DRM_FORMAT_YVU420, which allows height alignment, saving the total size it calculates
 320          * and then calling it again with requested parameters.
 321          *
 322          * This relies on the fact that i965 driver uses separate surfaces for each plane and
 323          * contents of padding bytes is not affected, as it is only used to satisfy GPU cache
 324          * requests.
 325          *
 326          * This is enforced by Mesa in src/intel/isl/isl_gen8.c, inside
 327          * isl_gen8_choose_image_alignment_el(), which is used for GEN9 and GEN8.
 328          */
 329         if (format == DRM_FORMAT_YVU420_ANDROID) {
 330                 uint32_t unaligned_height = bo->height;
 331                 size_t total_size;
 332
 333                 drv_bo_from_format(bo, stride, height, DRM_FORMAT_YVU420);
 334                 total_size = bo->total_size;
 335                 drv_bo_from_format(bo, stride, unaligned_height, format);
 336                 bo->total_size = total_size;
 337         } else {
 338                 drv_bo_from_format(bo, stride, height, format);
 339         }
 340
 341         /*
 342          * Quoting Mesa ISL library:
 343          *
 344          *    - For linear surfaces, additional padding of 64 bytes is required at
 345          *      the bottom of the surface. This is in addition to the padding
 346          *      required above.
 347          */
 348         if (bo->tiling == I915_TILING_NONE)
 349                 bo->total_size += 64;
 350
 351         memset(&gem_create, 0, sizeof(gem_create));
 352         gem_create.size = bo->total_size;
 353
 354         ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_CREATE, &gem_create);
 355         if (ret) {
 356                 fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_CREATE failed (size=%llu)\n",
 357                         gem_create.size);
 358                 return ret;
 359         }
 360
 361         for (plane = 0; plane < bo->num_planes; plane++)
 362                 bo->handles[plane].u32 = gem_create.handle;
 363
 364         memset(&gem_set_tiling, 0, sizeof(gem_set_tiling));
 365         gem_set_tiling.handle = bo->handles[0].u32;
 366         gem_set_tiling.tiling_mode = bo->tiling;
 367         gem_set_tiling.stride = bo->strides[0];
 368
 369         ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_SET_TILING, &gem_set_tiling);
 370         if (ret) {
 371                 struct drm_gem_close gem_close;
 372                 memset(&gem_close, 0, sizeof(gem_close));
 373                 gem_close.handle = bo->handles[0].u32;
 374                 drmIoctl(bo->drv->fd, DRM_IOCTL_GEM_CLOSE, &gem_close);
 375
 376                 fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_SET_TILING failed with %d", errno);
 377                 return -errno;
 378         }
 379
 380         return 0;
 381 }
 382
 383 static void i915_close(struct driver *drv)
 384 {
 385         free(drv->priv);
 386         drv->priv = NULL;
 387 }
 388
 389 static int i915_bo_import(struct bo *bo, struct drv_import_fd_data *data)
 390 {
 391         int ret;
 392         struct drm_i915_gem_get_tiling gem_get_tiling;
 393
 394         ret = drv_prime_bo_import(bo, data);
 395         if (ret)
 396                 return ret;
 397
 398         /* TODO(gsingh): export modifiers and get rid of backdoor tiling. */
 399         memset(&gem_get_tiling, 0, sizeof(gem_get_tiling));
 400         gem_get_tiling.handle = bo->handles[0].u32;
 401
 402         ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_GET_TILING, &gem_get_tiling);
 403         if (ret) {
 404                 drv_gem_bo_destroy(bo);
 405                 fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_GET_TILING failed.");
 406                 return ret;
 407         }
 408
 409         bo->tiling = gem_get_tiling.tiling_mode;
 410         return 0;
 411 }
 412
 413 static void *i915_bo_map(struct bo *bo, struct map_info *data, size_t plane, int prot)
 414 {
 415         int ret;
 416         void *addr;
 417         struct drm_i915_gem_set_domain set_domain;
 418
 419         memset(&set_domain, 0, sizeof(set_domain));
 420         set_domain.handle = bo->handles[0].u32;
 421         if (bo->tiling == I915_TILING_NONE) {
 422                 struct drm_i915_gem_mmap gem_map;
 423                 memset(&gem_map, 0, sizeof(gem_map));
 424
 425                 gem_map.handle = bo->handles[0].u32;
 426                 gem_map.offset = 0;
 427                 gem_map.size = bo->total_size;
 428
 429                 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_MMAP, &gem_map);
 430                 if (ret) {
 431                         fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_MMAP failed\n");
 432                         return MAP_FAILED;
 433                 }
 434
 435                 addr = (void *)(uintptr_t)gem_map.addr_ptr;
 436                 set_domain.read_domains = I915_GEM_DOMAIN_CPU;
 437                 set_domain.write_domain = I915_GEM_DOMAIN_CPU;
 438
 439         } else {
 440                 struct drm_i915_gem_mmap_gtt gem_map;
 441                 memset(&gem_map, 0, sizeof(gem_map));
 442
 443                 gem_map.handle = bo->handles[0].u32;
 444
 445                 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_MMAP_GTT, &gem_map);
 446                 if (ret) {
 447                         fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_MMAP_GTT failed\n");
 448                         return MAP_FAILED;
 449                 }
 450
 451                 addr = mmap(0, bo->total_size, prot, MAP_SHARED, bo->drv->fd, gem_map.offset);
 452                 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
 453                 set_domain.write_domain = I915_GEM_DOMAIN_GTT;
 454         }
 455
 456         if (addr == MAP_FAILED) {
 457                 fprintf(stderr, "drv: i915 GEM mmap failed\n");
 458                 return addr;
 459         }
 460
 461         ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_SET_DOMAIN, &set_domain);
 462         if (ret) {
 463                 fprintf(stderr, "drv: DRM_IOCTL_I915_GEM_SET_DOMAIN failed\n");
 464                 return MAP_FAILED;
 465         }
 466
 467         data->length = bo->total_size;
 468         return addr;
 469 }
 470
 471 static int i915_bo_unmap(struct bo *bo, struct map_info *data)
 472 {
 473         struct i915_device *i915 = bo->drv->priv;
 474         if (!i915->has_llc && bo->tiling == I915_TILING_NONE)
 475                 i915_clflush(data->addr, data->length);
 476
 477         return munmap(data->addr, data->length);
 478 }
 479
 480 static uint32_t i915_resolve_format(uint32_t format, uint64_t usage)
 481 {
 482         switch (format) {
 483         case DRM_FORMAT_FLEX_IMPLEMENTATION_DEFINED:
 484                 /* KBL camera subsystem requires NV12. */
 485                 if (usage & (BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE))
 486                         return DRM_FORMAT_NV12;
 487                 /*HACK: See b/28671744 */
 488                 return DRM_FORMAT_XBGR8888;
 489         case DRM_FORMAT_FLEX_YCbCr_420_888:
 490                 /* KBL camera subsystem requires NV12. */
 491                 if (usage & (BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE))
 492                         return DRM_FORMAT_NV12;
 493                 return DRM_FORMAT_YVU420;
 494         default:
 495                 return format;
 496         }
 497 }
 498
 499 struct backend backend_i915 = {
 500         .name = "i915",
 501         .init = i915_init,
 502         .close = i915_close,
 503         .bo_create = i915_bo_create,
 504         .bo_destroy = drv_gem_bo_destroy,
 505         .bo_import = i915_bo_import,
 506         .bo_map = i915_bo_map,
 507         .bo_unmap = i915_bo_unmap,
 508         .resolve_format = i915_resolve_format,
 509 };
 510
 511 #endif