i915.c

   1 /*
   2  * Copyright 2014 The Chromium OS Authors. All rights reserved.
   3  * Use of this source code is governed by a BSD-style license that can be
   4  * found in the LICENSE file.
   5  */
   6
   7 #ifdef DRV_I915
   8
   9 #include <assert.h>
  10 #include <errno.h>
  11 #include <stdbool.h>
  12 #include <stdio.h>
  13 #include <string.h>
  14 #include <sys/mman.h>
  15 #include <unistd.h>
  16 #include <xf86drm.h>
  17
  18 #include "drv_priv.h"
  19 #include "external/i915_drm.h"
  20 #include "helpers.h"
  21 #include "util.h"
  22
  23 #define I915_CACHELINE_SIZE 64
  24 #define I915_CACHELINE_MASK (I915_CACHELINE_SIZE - 1)
  25
  26 static const uint32_t scanout_render_formats[] = { DRM_FORMAT_ABGR2101010, DRM_FORMAT_ABGR8888,
  27                                                    DRM_FORMAT_ARGB2101010, DRM_FORMAT_ARGB8888,
  28                                                    DRM_FORMAT_RGB565,      DRM_FORMAT_XBGR2101010,
  29                                                    DRM_FORMAT_XBGR8888,    DRM_FORMAT_XRGB2101010,
  30                                                    DRM_FORMAT_XRGB8888 };
  31
  32 static const uint32_t render_formats[] = { DRM_FORMAT_ABGR16161616F };
  33
  34 static const uint32_t texture_only_formats[] = { DRM_FORMAT_R8, DRM_FORMAT_NV12, DRM_FORMAT_P010,
  35                                                  DRM_FORMAT_YVU420, DRM_FORMAT_YVU420_ANDROID };
  36
  37 static const uint64_t gen_modifier_order[] = { I915_FORMAT_MOD_Y_TILED, I915_FORMAT_MOD_X_TILED,
  38                                                DRM_FORMAT_MOD_LINEAR };
  39
  40 static const uint64_t gen11_modifier_order[] = { I915_FORMAT_MOD_Y_TILED_CCS,
  41                                                  I915_FORMAT_MOD_Y_TILED, I915_FORMAT_MOD_X_TILED,
  42                                                  DRM_FORMAT_MOD_LINEAR };
  43
  44 struct modifier_support_t {
  45         const uint64_t *order;
  46         uint32_t count;
  47 };
  48
  49 struct i915_device {
  50         uint32_t gen;
  51         int32_t has_llc;
  52         int32_t has_hw_protection;
  53         struct modifier_support_t modifier;
  54 };
  55
  56 static uint32_t i915_get_gen(int device_id)
  57 {
  58         const uint16_t gen3_ids[] = { 0x2582, 0x2592, 0x2772, 0x27A2, 0x27AE,
  59                                       0x29C2, 0x29B2, 0x29D2, 0xA001, 0xA011 };
  60         const uint16_t gen11_ids[] = { 0x4E71, 0x4E61, 0x4E51, 0x4E55, 0x4E57 };
  61         const uint16_t gen12_ids[] = { 0x9A40, 0x9A49, 0x9A59, 0x9A60, 0x9A68, 0x9A70,
  62                                        0x9A78, 0x9AC0, 0x9AC9, 0x9AD9, 0x9AF8 };
  63         unsigned i;
  64         for (i = 0; i < ARRAY_SIZE(gen3_ids); i++)
  65                 if (gen3_ids[i] == device_id)
  66                         return 3;
  67         /* Gen 11 */
  68         for (i = 0; i < ARRAY_SIZE(gen11_ids); i++)
  69                 if (gen11_ids[i] == device_id)
  70                         return 11;
  71
  72         /* Gen 12 */
  73         for (i = 0; i < ARRAY_SIZE(gen12_ids); i++)
  74                 if (gen12_ids[i] == device_id)
  75                         return 12;
  76
  77         return 4;
  78 }
  79
  80 static void i915_get_modifier_order(struct i915_device *i915)
  81 {
  82         if (i915->gen == 11) {
  83                 i915->modifier.order = gen11_modifier_order;
  84                 i915->modifier.count = ARRAY_SIZE(gen11_modifier_order);
  85         } else {
  86                 i915->modifier.order = gen_modifier_order;
  87                 i915->modifier.count = ARRAY_SIZE(gen_modifier_order);
  88         }
  89 }
  90
  91 static uint64_t unset_flags(uint64_t current_flags, uint64_t mask)
  92 {
  93         uint64_t value = current_flags & ~mask;
  94         return value;
  95 }
  96
  97 static int i915_add_combinations(struct driver *drv)
  98 {
  99         struct format_metadata metadata;
 100         uint64_t render, scanout_and_render, texture_only, hw_protected;
 101         struct i915_device *i915 = drv->priv;
 102
 103         scanout_and_render = BO_USE_RENDER_MASK | BO_USE_SCANOUT;
 104         render = BO_USE_RENDER_MASK;
 105         texture_only = BO_USE_TEXTURE_MASK;
 106         hw_protected = (i915->has_hw_protection) ? BO_USE_PROTECTED : 0;
 107
 108         uint64_t linear_mask =
 109             BO_USE_RENDERSCRIPT | BO_USE_LINEAR | BO_USE_SW_READ_OFTEN | BO_USE_SW_WRITE_OFTEN;
 110
 111         metadata.tiling = I915_TILING_NONE;
 112         metadata.priority = 1;
 113         metadata.modifier = DRM_FORMAT_MOD_LINEAR;
 114
 115         drv_add_combinations(drv, scanout_render_formats, ARRAY_SIZE(scanout_render_formats),
 116                              &metadata, scanout_and_render);
 117
 118         drv_add_combinations(drv, render_formats, ARRAY_SIZE(render_formats), &metadata, render);
 119
 120         drv_add_combinations(drv, texture_only_formats, ARRAY_SIZE(texture_only_formats), &metadata,
 121                              texture_only);
 122
 123         drv_modify_linear_combinations(drv);
 124
 125         /* NV12 format for camera, display, decoding and encoding. */
 126         /* IPU3 camera ISP supports only NV12 output. */
 127         drv_modify_combination(drv, DRM_FORMAT_NV12, &metadata,
 128                                BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE | BO_USE_SCANOUT |
 129                                    BO_USE_HW_VIDEO_DECODER | BO_USE_HW_VIDEO_ENCODER |
 130                                    hw_protected);
 131
 132         /* Android CTS tests require this. */
 133         drv_add_combination(drv, DRM_FORMAT_BGR888, &metadata, BO_USE_SW_MASK);
 134
 135         /*
 136          * R8 format is used for Android's HAL_PIXEL_FORMAT_BLOB and is used for JPEG snapshots
 137          * from camera and input/output from hardware decoder/encoder.
 138          */
 139         drv_modify_combination(drv, DRM_FORMAT_R8, &metadata,
 140                                BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE | BO_USE_HW_VIDEO_DECODER |
 141                                    BO_USE_HW_VIDEO_ENCODER);
 142
 143         render = unset_flags(render, linear_mask);
 144         scanout_and_render = unset_flags(scanout_and_render, linear_mask);
 145
 146         metadata.tiling = I915_TILING_X;
 147         metadata.priority = 2;
 148         metadata.modifier = I915_FORMAT_MOD_X_TILED;
 149
 150         drv_add_combinations(drv, render_formats, ARRAY_SIZE(render_formats), &metadata, render);
 151         drv_add_combinations(drv, scanout_render_formats, ARRAY_SIZE(scanout_render_formats),
 152                              &metadata, scanout_and_render);
 153
 154         metadata.tiling = I915_TILING_Y;
 155         metadata.priority = 3;
 156         metadata.modifier = I915_FORMAT_MOD_Y_TILED;
 157
 158         scanout_and_render =
 159             unset_flags(scanout_and_render, BO_USE_SW_READ_RARELY | BO_USE_SW_WRITE_RARELY);
 160 /* Support y-tiled NV12 and P010 for libva */
 161 #ifdef I915_SCANOUT_Y_TILED
 162         drv_add_combination(drv, DRM_FORMAT_NV12, &metadata,
 163                             BO_USE_TEXTURE | BO_USE_HW_VIDEO_DECODER | BO_USE_SCANOUT |
 164                                 hw_protected);
 165 #else
 166         drv_add_combination(drv, DRM_FORMAT_NV12, &metadata,
 167                             BO_USE_TEXTURE | BO_USE_HW_VIDEO_DECODER);
 168 #endif
 169         scanout_and_render = unset_flags(scanout_and_render, BO_USE_SCANOUT);
 170         drv_add_combination(drv, DRM_FORMAT_P010, &metadata,
 171                             BO_USE_TEXTURE | BO_USE_HW_VIDEO_DECODER);
 172
 173         drv_add_combinations(drv, render_formats, ARRAY_SIZE(render_formats), &metadata, render);
 174         drv_add_combinations(drv, scanout_render_formats, ARRAY_SIZE(scanout_render_formats),
 175                              &metadata, scanout_and_render);
 176         return 0;
 177 }
 178
 179 static int i915_align_dimensions(struct bo *bo, uint32_t tiling, uint32_t *stride,
 180                                  uint32_t *aligned_height)
 181 {
 182         struct i915_device *i915 = bo->drv->priv;
 183         uint32_t horizontal_alignment;
 184         uint32_t vertical_alignment;
 185
 186         switch (tiling) {
 187         default:
 188         case I915_TILING_NONE:
 189                 /*
 190                  * The Intel GPU doesn't need any alignment in linear mode,
 191                  * but libva requires the allocation stride to be aligned to
 192                  * 16 bytes and height to 4 rows. Further, we round up the
 193                  * horizontal alignment so that row start on a cache line (64
 194                  * bytes).
 195                  */
 196                 horizontal_alignment = 64;
 197                 vertical_alignment = 4;
 198                 break;
 199
 200         case I915_TILING_X:
 201                 horizontal_alignment = 512;
 202                 vertical_alignment = 8;
 203                 break;
 204
 205         case I915_TILING_Y:
 206                 if (i915->gen == 3) {
 207                         horizontal_alignment = 512;
 208                         vertical_alignment = 8;
 209                 } else {
 210                         horizontal_alignment = 128;
 211                         vertical_alignment = 32;
 212                 }
 213                 break;
 214         }
 215
 216         *aligned_height = ALIGN(*aligned_height, vertical_alignment);
 217         if (i915->gen > 3) {
 218                 *stride = ALIGN(*stride, horizontal_alignment);
 219         } else {
 220                 while (*stride > horizontal_alignment)
 221                         horizontal_alignment <<= 1;
 222
 223                 *stride = horizontal_alignment;
 224         }
 225
 226         if (i915->gen <= 3 && *stride > 8192)
 227                 return -EINVAL;
 228
 229         return 0;
 230 }
 231
 232 static void i915_clflush(void *start, size_t size)
 233 {
 234         void *p = (void *)(((uintptr_t)start) & ~I915_CACHELINE_MASK);
 235         void *end = (void *)((uintptr_t)start + size);
 236
 237         __builtin_ia32_mfence();
 238         while (p < end) {
 239                 __builtin_ia32_clflush(p);
 240                 p = (void *)((uintptr_t)p + I915_CACHELINE_SIZE);
 241         }
 242 }
 243
 244 static int i915_init(struct driver *drv)
 245 {
 246         int ret;
 247         int device_id;
 248         struct i915_device *i915;
 249         drm_i915_getparam_t get_param = { 0 };
 250
 251         i915 = calloc(1, sizeof(*i915));
 252         if (!i915)
 253                 return -ENOMEM;
 254
 255         get_param.param = I915_PARAM_CHIPSET_ID;
 256         get_param.value = &device_id;
 257         ret = drmIoctl(drv->fd, DRM_IOCTL_I915_GETPARAM, &get_param);
 258         if (ret) {
 259                 drv_log("Failed to get I915_PARAM_CHIPSET_ID\n");
 260                 free(i915);
 261                 return -EINVAL;
 262         }
 263
 264         i915->gen = i915_get_gen(device_id);
 265         i915_get_modifier_order(i915);
 266
 267         memset(&get_param, 0, sizeof(get_param));
 268         get_param.param = I915_PARAM_HAS_LLC;
 269         get_param.value = &i915->has_llc;
 270         ret = drmIoctl(drv->fd, DRM_IOCTL_I915_GETPARAM, &get_param);
 271         if (ret) {
 272                 drv_log("Failed to get I915_PARAM_HAS_LLC\n");
 273                 free(i915);
 274                 return -EINVAL;
 275         }
 276
 277         if (i915->gen >= 12)
 278                 i915->has_hw_protection = 1;
 279
 280         drv->priv = i915;
 281         return i915_add_combinations(drv);
 282 }
 283
 284 static int i915_bo_from_format(struct bo *bo, uint32_t width, uint32_t height, uint32_t format)
 285 {
 286         uint32_t offset;
 287         size_t plane;
 288         int ret, pagesize;
 289
 290         offset = 0;
 291         pagesize = getpagesize();
 292         for (plane = 0; plane < drv_num_planes_from_format(format); plane++) {
 293                 uint32_t stride = drv_stride_from_format(format, width, plane);
 294                 uint32_t plane_height = drv_height_from_format(format, height, plane);
 295
 296                 if (bo->meta.tiling != I915_TILING_NONE)
 297                         assert(IS_ALIGNED(offset, pagesize));
 298
 299                 ret = i915_align_dimensions(bo, bo->meta.tiling, &stride, &plane_height);
 300                 if (ret)
 301                         return ret;
 302
 303                 bo->meta.strides[plane] = stride;
 304                 bo->meta.sizes[plane] = stride * plane_height;
 305                 bo->meta.offsets[plane] = offset;
 306                 offset += bo->meta.sizes[plane];
 307         }
 308
 309         bo->meta.total_size = ALIGN(offset, pagesize);
 310
 311         return 0;
 312 }
 313
 314 static int i915_bo_compute_metadata(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
 315                                     uint64_t use_flags, const uint64_t *modifiers, uint32_t count)
 316 {
 317         uint64_t modifier;
 318         struct i915_device *i915 = bo->drv->priv;
 319         bool huge_bo = (i915->gen < 11) && (width > 4096);
 320
 321         if (modifiers) {
 322                 modifier =
 323                     drv_pick_modifier(modifiers, count, i915->modifier.order, i915->modifier.count);
 324         } else {
 325                 struct combination *combo = drv_get_combination(bo->drv, format, use_flags);
 326                 if (!combo)
 327                         return -EINVAL;
 328                 modifier = combo->metadata.modifier;
 329         }
 330
 331         /*
 332          * i915 only supports linear/x-tiled above 4096 wide on Gen9/Gen10 GPU.
 333          * VAAPI decode in NV12 Y tiled format so skip modifier change for NV12/P010 huge bo.
 334          */
 335         if (huge_bo && format != DRM_FORMAT_NV12 && format != DRM_FORMAT_P010 &&
 336             modifier != I915_FORMAT_MOD_X_TILED && modifier != DRM_FORMAT_MOD_LINEAR) {
 337                 uint32_t i;
 338                 for (i = 0; modifiers && i < count; i++) {
 339                         if (modifiers[i] == I915_FORMAT_MOD_X_TILED)
 340                                 break;
 341                 }
 342                 if (i == count)
 343                         modifier = DRM_FORMAT_MOD_LINEAR;
 344                 else
 345                         modifier = I915_FORMAT_MOD_X_TILED;
 346         }
 347
 348         switch (modifier) {
 349         case DRM_FORMAT_MOD_LINEAR:
 350                 bo->meta.tiling = I915_TILING_NONE;
 351                 break;
 352         case I915_FORMAT_MOD_X_TILED:
 353                 bo->meta.tiling = I915_TILING_X;
 354                 break;
 355         case I915_FORMAT_MOD_Y_TILED:
 356         case I915_FORMAT_MOD_Y_TILED_CCS:
 357                 bo->meta.tiling = I915_TILING_Y;
 358                 break;
 359         }
 360
 361         bo->meta.format_modifiers[0] = modifier;
 362
 363         if (format == DRM_FORMAT_YVU420_ANDROID) {
 364                 /*
 365                  * We only need to be able to use this as a linear texture,
 366                  * which doesn't put any HW restrictions on how we lay it
 367                  * out. The Android format does require the stride to be a
 368                  * multiple of 16 and expects the Cr and Cb stride to be
 369                  * ALIGN(Y_stride / 2, 16), which we can make happen by
 370                  * aligning to 32 bytes here.
 371                  */
 372                 uint32_t stride = ALIGN(width, 32);
 373                 drv_bo_from_format(bo, stride, height, format);
 374         } else if (modifier == I915_FORMAT_MOD_Y_TILED_CCS) {
 375                 /*
 376                  * For compressed surfaces, we need a color control surface
 377                  * (CCS). Color compression is only supported for Y tiled
 378                  * surfaces, and for each 32x16 tiles in the main surface we
 379                  * need a tile in the control surface.  Y tiles are 128 bytes
 380                  * wide and 32 lines tall and we use that to first compute the
 381                  * width and height in tiles of the main surface. stride and
 382                  * height are already multiples of 128 and 32, respectively:
 383                  */
 384                 uint32_t stride = drv_stride_from_format(format, width, 0);
 385                 uint32_t width_in_tiles = DIV_ROUND_UP(stride, 128);
 386                 uint32_t height_in_tiles = DIV_ROUND_UP(height, 32);
 387                 uint32_t size = width_in_tiles * height_in_tiles * 4096;
 388                 uint32_t offset = 0;
 389
 390                 bo->meta.strides[0] = width_in_tiles * 128;
 391                 bo->meta.sizes[0] = size;
 392                 bo->meta.offsets[0] = offset;
 393                 offset += size;
 394
 395                 /*
 396                  * Now, compute the width and height in tiles of the control
 397                  * surface by dividing and rounding up.
 398                  */
 399                 uint32_t ccs_width_in_tiles = DIV_ROUND_UP(width_in_tiles, 32);
 400                 uint32_t ccs_height_in_tiles = DIV_ROUND_UP(height_in_tiles, 16);
 401                 uint32_t ccs_size = ccs_width_in_tiles * ccs_height_in_tiles * 4096;
 402
 403                 /*
 404                  * With stride and height aligned to y tiles, offset is
 405                  * already a multiple of 4096, which is the required alignment
 406                  * of the CCS.
 407                  */
 408                 bo->meta.strides[1] = ccs_width_in_tiles * 128;
 409                 bo->meta.sizes[1] = ccs_size;
 410                 bo->meta.offsets[1] = offset;
 411                 offset += ccs_size;
 412
 413                 bo->meta.num_planes = 2;
 414                 bo->meta.total_size = offset;
 415         } else {
 416                 i915_bo_from_format(bo, width, height, format);
 417         }
 418         return 0;
 419 }
 420
 421 static int i915_bo_create_from_metadata(struct bo *bo)
 422 {
 423         int ret;
 424         size_t plane;
 425         uint32_t gem_handle;
 426         struct drm_i915_gem_set_tiling gem_set_tiling = { 0 };
 427         struct i915_device *i915 = bo->drv->priv;
 428
 429         if (i915->has_hw_protection && (bo->meta.use_flags & BO_USE_PROTECTED)) {
 430                 struct drm_i915_gem_object_param protected_param = {
 431                         .param = I915_OBJECT_PARAM | I915_PARAM_PROTECTED_CONTENT,
 432                         .data = 1,
 433                 };
 434
 435                 struct drm_i915_gem_create_ext_setparam setparam_protected = {
 436                         .base = { .name = I915_GEM_CREATE_EXT_SETPARAM },
 437                         .param = protected_param,
 438                 };
 439
 440                 struct drm_i915_gem_create_ext create_ext = {
 441                         .size = bo->meta.total_size,
 442                         .extensions = (uintptr_t)&setparam_protected,
 443                 };
 444
 445                 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_CREATE_EXT, &create_ext);
 446                 if (ret) {
 447                         drv_log("DRM_IOCTL_I915_GEM_CREATE_EXT failed (size=%llu)\n",
 448                                 create_ext.size);
 449                         return -errno;
 450                 }
 451
 452                 gem_handle = create_ext.handle;
 453         } else {
 454                 struct drm_i915_gem_create gem_create = { 0 };
 455                 gem_create.size = bo->meta.total_size;
 456                 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_CREATE, &gem_create);
 457                 if (ret) {
 458                         drv_log("DRM_IOCTL_I915_GEM_CREATE failed (size=%llu)\n", gem_create.size);
 459                         return -errno;
 460                 }
 461
 462                 gem_handle = gem_create.handle;
 463         }
 464
 465         for (plane = 0; plane < bo->meta.num_planes; plane++)
 466                 bo->handles[plane].u32 = gem_handle;
 467
 468         gem_set_tiling.handle = bo->handles[0].u32;
 469         gem_set_tiling.tiling_mode = bo->meta.tiling;
 470         gem_set_tiling.stride = bo->meta.strides[0];
 471
 472         ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_SET_TILING, &gem_set_tiling);
 473         if (ret) {
 474                 struct drm_gem_close gem_close = { 0 };
 475                 gem_close.handle = bo->handles[0].u32;
 476                 drmIoctl(bo->drv->fd, DRM_IOCTL_GEM_CLOSE, &gem_close);
 477
 478                 drv_log("DRM_IOCTL_I915_GEM_SET_TILING failed with %d\n", errno);
 479                 return -errno;
 480         }
 481
 482         return 0;
 483 }
 484
 485 static void i915_close(struct driver *drv)
 486 {
 487         free(drv->priv);
 488         drv->priv = NULL;
 489 }
 490
 491 static int i915_bo_import(struct bo *bo, struct drv_import_fd_data *data)
 492 {
 493         int ret;
 494         struct drm_i915_gem_get_tiling gem_get_tiling = { 0 };
 495
 496         ret = drv_prime_bo_import(bo, data);
 497         if (ret)
 498                 return ret;
 499
 500         /* TODO(gsingh): export modifiers and get rid of backdoor tiling. */
 501         gem_get_tiling.handle = bo->handles[0].u32;
 502
 503         ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_GET_TILING, &gem_get_tiling);
 504         if (ret) {
 505                 drv_gem_bo_destroy(bo);
 506                 drv_log("DRM_IOCTL_I915_GEM_GET_TILING failed.\n");
 507                 return ret;
 508         }
 509
 510         bo->meta.tiling = gem_get_tiling.tiling_mode;
 511         return 0;
 512 }
 513
 514 static void *i915_bo_map(struct bo *bo, struct vma *vma, size_t plane, uint32_t map_flags)
 515 {
 516         int ret;
 517         void *addr;
 518
 519         if (bo->meta.format_modifiers[0] == I915_FORMAT_MOD_Y_TILED_CCS)
 520                 return MAP_FAILED;
 521
 522         if (bo->meta.tiling == I915_TILING_NONE) {
 523                 struct drm_i915_gem_mmap gem_map = { 0 };
 524                 /* TODO(b/118799155): We don't seem to have a good way to
 525                  * detect the use cases for which WC mapping is really needed.
 526                  * The current heuristic seems overly coarse and may be slowing
 527                  * down some other use cases unnecessarily.
 528                  *
 529                  * For now, care must be taken not to use WC mappings for
 530                  * Renderscript and camera use cases, as they're
 531                  * performance-sensitive. */
 532                 if ((bo->meta.use_flags & BO_USE_SCANOUT) &&
 533                     !(bo->meta.use_flags &
 534                       (BO_USE_RENDERSCRIPT | BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE)))
 535                         gem_map.flags = I915_MMAP_WC;
 536
 537                 gem_map.handle = bo->handles[0].u32;
 538                 gem_map.offset = 0;
 539                 gem_map.size = bo->meta.total_size;
 540
 541                 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_MMAP, &gem_map);
 542                 if (ret) {
 543                         drv_log("DRM_IOCTL_I915_GEM_MMAP failed\n");
 544                         return MAP_FAILED;
 545                 }
 546
 547                 addr = (void *)(uintptr_t)gem_map.addr_ptr;
 548         } else {
 549                 struct drm_i915_gem_mmap_gtt gem_map = { 0 };
 550
 551                 gem_map.handle = bo->handles[0].u32;
 552                 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_MMAP_GTT, &gem_map);
 553                 if (ret) {
 554                         drv_log("DRM_IOCTL_I915_GEM_MMAP_GTT failed\n");
 555                         return MAP_FAILED;
 556                 }
 557
 558                 addr = mmap(0, bo->meta.total_size, drv_get_prot(map_flags), MAP_SHARED,
 559                             bo->drv->fd, gem_map.offset);
 560         }
 561
 562         if (addr == MAP_FAILED) {
 563                 drv_log("i915 GEM mmap failed\n");
 564                 return addr;
 565         }
 566
 567         vma->length = bo->meta.total_size;
 568         return addr;
 569 }
 570
 571 static int i915_bo_invalidate(struct bo *bo, struct mapping *mapping)
 572 {
 573         int ret;
 574         struct drm_i915_gem_set_domain set_domain = { 0 };
 575
 576         set_domain.handle = bo->handles[0].u32;
 577         if (bo->meta.tiling == I915_TILING_NONE) {
 578                 set_domain.read_domains = I915_GEM_DOMAIN_CPU;
 579                 if (mapping->vma->map_flags & BO_MAP_WRITE)
 580                         set_domain.write_domain = I915_GEM_DOMAIN_CPU;
 581         } else {
 582                 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
 583                 if (mapping->vma->map_flags & BO_MAP_WRITE)
 584                         set_domain.write_domain = I915_GEM_DOMAIN_GTT;
 585         }
 586
 587         ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_SET_DOMAIN, &set_domain);
 588         if (ret) {
 589                 drv_log("DRM_IOCTL_I915_GEM_SET_DOMAIN with %d\n", ret);
 590                 return ret;
 591         }
 592
 593         return 0;
 594 }
 595
 596 static int i915_bo_flush(struct bo *bo, struct mapping *mapping)
 597 {
 598         struct i915_device *i915 = bo->drv->priv;
 599         if (!i915->has_llc && bo->meta.tiling == I915_TILING_NONE)
 600                 i915_clflush(mapping->vma->addr, mapping->vma->length);
 601
 602         return 0;
 603 }
 604
 605 static uint32_t i915_resolve_format(struct driver *drv, uint32_t format, uint64_t use_flags)
 606 {
 607         switch (format) {
 608         case DRM_FORMAT_FLEX_IMPLEMENTATION_DEFINED:
 609                 /* KBL camera subsystem requires NV12. */
 610                 if (use_flags & (BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE))
 611                         return DRM_FORMAT_NV12;
 612                 /*HACK: See b/28671744 */
 613                 return DRM_FORMAT_XBGR8888;
 614         case DRM_FORMAT_FLEX_YCbCr_420_888:
 615                 /*
 616                  * KBL camera subsystem requires NV12. Our other use cases
 617                  * don't care:
 618                  * - Hardware video supports NV12,
 619                  * - USB Camera HALv3 supports NV12,
 620                  * - USB Camera HALv1 doesn't use this format.
 621                  * Moreover, NV12 is preferred for video, due to overlay
 622                  * support on SKL+.
 623                  */
 624                 return DRM_FORMAT_NV12;
 625         default:
 626                 return format;
 627         }
 628 }
 629
 630 const struct backend backend_i915 = {
 631         .name = "i915",
 632         .init = i915_init,
 633         .close = i915_close,
 634         .bo_compute_metadata = i915_bo_compute_metadata,
 635         .bo_create_from_metadata = i915_bo_create_from_metadata,
 636         .bo_destroy = drv_gem_bo_destroy,
 637         .bo_import = i915_bo_import,
 638         .bo_map = i915_bo_map,
 639         .bo_unmap = drv_bo_munmap,
 640         .bo_invalidate = i915_bo_invalidate,
 641         .bo_flush = i915_bo_flush,
 642         .resolve_format = i915_resolve_format,
 643 };
 644
 645 #endif