mediatek.c

   1 /*
   2  * Copyright 2015 The Chromium OS Authors. All rights reserved.
   3  * Use of this source code is governed by a BSD-style license that can be
   4  * found in the LICENSE file.
   5  */
   6
   7 #ifdef DRV_MEDIATEK
   8
   9 #include <stdio.h>
  10 #include <string.h>
  11 #include <sys/mman.h>
  12 #include <xf86drm.h>
  13 #include <mediatek_drm.h>
  14
  15 #include "drv_priv.h"
  16 #include "helpers.h"
  17 #include "util.h"
  18
  19 static struct supported_combination combos[6] = {
  20         {DRM_FORMAT_ABGR8888, DRM_FORMAT_MOD_NONE,
  21                 BO_USE_LINEAR | BO_USE_RENDERING | BO_USE_SW_READ_OFTEN | BO_USE_SW_WRITE_OFTEN |
  22                 BO_USE_SW_READ_RARELY | BO_USE_SW_WRITE_RARELY},
  23         {DRM_FORMAT_ARGB8888, DRM_FORMAT_MOD_NONE,
  24                 BO_USE_CURSOR | BO_USE_LINEAR | BO_USE_RENDERING | BO_USE_SW_READ_OFTEN |
  25                 BO_USE_SW_WRITE_OFTEN | BO_USE_SW_READ_RARELY | BO_USE_SW_WRITE_RARELY},
  26         {DRM_FORMAT_RGB565, DRM_FORMAT_MOD_NONE,
  27                 BO_USE_RENDERING | BO_USE_SW_READ_OFTEN | BO_USE_SW_WRITE_OFTEN |
  28                 BO_USE_SW_READ_RARELY | BO_USE_SW_WRITE_RARELY},
  29         {DRM_FORMAT_XBGR8888, DRM_FORMAT_MOD_NONE,
  30                 BO_USE_RENDERING | BO_USE_SW_READ_OFTEN | BO_USE_SW_WRITE_OFTEN |
  31                 BO_USE_SW_READ_RARELY | BO_USE_SW_WRITE_RARELY},
  32         {DRM_FORMAT_XRGB8888, DRM_FORMAT_MOD_NONE,
  33                 BO_USE_CURSOR | BO_USE_LINEAR | BO_USE_RENDERING | BO_USE_SW_READ_OFTEN |
  34                 BO_USE_SW_WRITE_OFTEN | BO_USE_SW_READ_RARELY | BO_USE_SW_WRITE_RARELY},
  35         {DRM_FORMAT_YVU420, DRM_FORMAT_MOD_NONE,
  36                 BO_USE_LINEAR | BO_USE_RENDERING | BO_USE_SW_READ_OFTEN | BO_USE_SW_WRITE_OFTEN |
  37                 BO_USE_SW_READ_RARELY | BO_USE_SW_WRITE_RARELY},
  38 };
  39
  40 static int mediatek_init(struct driver *drv)
  41 {
  42         drv_insert_combinations(drv, combos, ARRAY_SIZE(combos));
  43         return drv_add_kms_flags(drv);
  44 }
  45
  46 static int mediatek_bo_create(struct bo *bo, uint32_t width, uint32_t height,
  47                               uint32_t format, uint32_t flags)
  48 {
  49         int ret;
  50         size_t plane;
  51         struct drm_mtk_gem_create gem_create;
  52         uint32_t bytes_per_pixel = drv_stride_from_format(format, 1, 0);
  53
  54         /*
  55          * Since the ARM L1 cache line size is 64 bytes, align to that as a
  56          * performance optimization.
  57          */
  58         width = ALIGN(width, DIV_ROUND_UP(64, bytes_per_pixel));
  59         drv_bo_from_format(bo, width, height, format);
  60
  61         memset(&gem_create, 0, sizeof(gem_create));
  62         gem_create.size = bo->total_size;
  63
  64         ret = drmIoctl(bo->drv->fd, DRM_IOCTL_MTK_GEM_CREATE, &gem_create);
  65         if (ret) {
  66                 fprintf(stderr, "drv: DRM_IOCTL_MTK_GEM_CREATE failed "
  67                                 "(size=%llu)\n", gem_create.size);
  68                 return ret;
  69         }
  70
  71         for (plane = 0; plane < bo->num_planes; plane++)
  72                 bo->handles[plane].u32 = gem_create.handle;
  73
  74         return 0;
  75 }
  76
  77 static void *mediatek_bo_map(struct bo *bo, struct map_info *data, size_t plane)
  78 {
  79         int ret;
  80         struct drm_mtk_gem_map_off gem_map;
  81
  82         memset(&gem_map, 0, sizeof(gem_map));
  83         gem_map.handle = bo->handles[0].u32;
  84
  85         ret = drmIoctl(bo->drv->fd, DRM_IOCTL_MTK_GEM_MAP_OFFSET, &gem_map);
  86         if (ret) {
  87                 fprintf(stderr,"drv: DRM_IOCTL_MTK_GEM_MAP_OFFSET failed\n");
  88                 return MAP_FAILED;
  89         }
  90
  91         data->length = bo->total_size;
  92
  93         return mmap(0, bo->total_size, PROT_READ | PROT_WRITE, MAP_SHARED,
  94                     bo->drv->fd, gem_map.offset);
  95 }
  96
  97 static uint32_t mediatek_resolve_format(uint32_t format)
  98 {
  99         switch (format) {
 100         case DRM_FORMAT_FLEX_IMPLEMENTATION_DEFINED:
 101                 /*HACK: See b/28671744 */
 102                 return DRM_FORMAT_XBGR8888;
 103         case DRM_FORMAT_FLEX_YCbCr_420_888:
 104                 return DRM_FORMAT_YVU420;
 105         default:
 106                 return format;
 107         }
 108 }
 109
 110 struct backend backend_mediatek =
 111 {
 112         .name = "mediatek",
 113         .init = mediatek_init,
 114         .bo_create = mediatek_bo_create,
 115         .bo_destroy = drv_gem_bo_destroy,
 116         .bo_import = drv_prime_bo_import,
 117         .bo_map = mediatek_bo_map,
 118         .resolve_format = mediatek_resolve_format,
 119 };
 120
 121 #endif