tegra.c

   1 /*
   2  * Copyright 2014 The Chromium OS Authors. All rights reserved.
   3  * Use of this source code is governed by a BSD-style license that can be
   4  * found in the LICENSE file.
   5  */
   6
   7 #ifdef DRV_TEGRA
   8
   9 #include <stdio.h>
  10 #include <string.h>
  11 #include <sys/mman.h>
  12 #include <xf86drm.h>
  13 #include <tegra_drm.h>
  14
  15 #include "drv_priv.h"
  16 #include "helpers.h"
  17 #include "util.h"
  18
  19 /*
  20  * GOB (Group Of Bytes) is the basic unit of the blocklinear layout.
  21  * GOBs are arranged to blocks, where the height of the block (measured
  22  * in GOBs) is configurable.
  23  */
  24 #define NV_BLOCKLINEAR_GOB_HEIGHT 8
  25 #define NV_BLOCKLINEAR_GOB_WIDTH 64
  26 #define NV_DEFAULT_BLOCK_HEIGHT_LOG2 4
  27 #define NV_PREFERRED_PAGE_SIZE (128 * 1024)
  28
  29 enum nv_mem_kind
  30 {
  31         NV_MEM_KIND_PITCH = 0,
  32         NV_MEM_KIND_C32_2CRA = 0xdb,
  33         NV_MEM_KIND_GENERIC_16Bx2 = 0xfe,
  34 };
  35
  36 enum tegra_map_type {
  37         TEGRA_READ_TILED_BUFFER = 0,
  38         TEGRA_WRITE_TILED_BUFFER = 1,
  39 };
  40
  41 struct tegra_private_map_data {
  42         void *tiled;
  43         void *untiled;
  44 };
  45
  46 static const uint32_t supported_formats[] = {
  47         DRM_FORMAT_ARGB8888, DRM_FORMAT_XRGB8888
  48 };
  49
  50 static int compute_block_height_log2(int height)
  51 {
  52         int block_height_log2 = NV_DEFAULT_BLOCK_HEIGHT_LOG2;
  53
  54         if (block_height_log2 > 0) {
  55                 /* Shrink, if a smaller block height could cover the whole
  56                  * surface height. */
  57                 int proposed = NV_BLOCKLINEAR_GOB_HEIGHT << (block_height_log2 - 1);
  58                 while (proposed >= height) {
  59                         block_height_log2--;
  60                         if (block_height_log2 == 0)
  61                                 break;
  62                         proposed /= 2;
  63                 }
  64         }
  65         return block_height_log2;
  66 }
  67
  68 static void compute_layout_blocklinear(int width, int height, int format,
  69                                        enum nv_mem_kind *kind,
  70                                        uint32_t *block_height_log2,
  71                                        uint32_t *stride, uint32_t *size)
  72 {
  73         int pitch = drv_stride_from_format(format, width, 0);
  74
  75         /* Align to blocklinear blocks. */
  76         pitch = ALIGN(pitch, NV_BLOCKLINEAR_GOB_WIDTH);
  77
  78         /* Compute padded height. */
  79         *block_height_log2 = compute_block_height_log2(height);
  80         int block_height = 1 << *block_height_log2;
  81         int padded_height =
  82                 ALIGN(height, NV_BLOCKLINEAR_GOB_HEIGHT * block_height);
  83
  84         int bytes = pitch * padded_height;
  85
  86         /* Pad the allocation to the preferred page size.
  87          * This will reduce the required page table size (see discussion in NV
  88          * bug 1321091), and also acts as a WAR for NV bug 1325421.
  89          */
  90         bytes = ALIGN(bytes, NV_PREFERRED_PAGE_SIZE);
  91
  92         *kind = NV_MEM_KIND_C32_2CRA;
  93         *stride = pitch;
  94         *size = bytes;
  95 }
  96
  97 static void compute_layout_linear(int width, int height, int format,
  98                                   uint32_t *stride, uint32_t *size)
  99 {
 100         *stride = ALIGN(drv_stride_from_format(format, width, 0), 64);
 101         *size = *stride * height;
 102 }
 103
 104 static void transfer_tile(struct bo *bo, uint8_t *tiled, uint8_t *untiled,
 105                           enum tegra_map_type type, uint32_t bytes_per_pixel,
 106                           uint32_t gob_top, uint32_t gob_left,
 107                           uint32_t gob_size_pixels)
 108 {
 109         uint8_t *tmp;
 110         uint32_t x, y, k;
 111         for (k = 0; k < gob_size_pixels; k++) {
 112                 /*
 113                  * Given the kth pixel starting from the tile specified by
 114                  * gob_top and gob_left, unswizzle to get the standard (x, y)
 115                  * representation.
 116                  */
 117                 x = gob_left + (((k >> 3) & 8) | ((k >> 1) & 4) | (k & 3));
 118                 y = gob_top + ((k >> 7 << 3) | ((k >> 3) & 6) | ((k >> 2) & 1));
 119
 120                 tmp = untiled + (y * bo->strides[0]) + (x * bytes_per_pixel);
 121
 122                 if (type == TEGRA_READ_TILED_BUFFER)
 123                         memcpy(tmp, tiled, bytes_per_pixel);
 124                 else if (type == TEGRA_WRITE_TILED_BUFFER)
 125                         memcpy(tiled, tmp, bytes_per_pixel);
 126
 127                 /* Move on to next pixel. */
 128                 tiled += bytes_per_pixel;
 129         }
 130 }
 131
 132 static void transfer_tiled_memory(struct bo *bo, uint8_t *tiled,
 133                                   uint8_t *untiled, enum tegra_map_type type)
 134 {
 135         uint32_t gob_width, gob_height, gob_size_bytes, gob_size_pixels,
 136                  gob_count_x, gob_count_y, gob_top, gob_left;
 137         uint32_t i, j, offset;
 138         uint8_t *tmp;
 139         uint32_t bytes_per_pixel = drv_stride_from_format(bo->format, 1, 0);
 140
 141         /*
 142          * The blocklinear format consists of 8*(2^n) x 64 byte sized tiles,
 143          * where 0 <= n <= 4.
 144          */
 145         gob_width = DIV_ROUND_UP(NV_BLOCKLINEAR_GOB_WIDTH, bytes_per_pixel);
 146         gob_height = NV_BLOCKLINEAR_GOB_HEIGHT *
 147                      (1 << NV_DEFAULT_BLOCK_HEIGHT_LOG2);
 148         /* Calculate the height from maximum possible gob height */
 149         while (gob_height > NV_BLOCKLINEAR_GOB_HEIGHT
 150                && gob_height >= 2 * bo->height)
 151                 gob_height /= 2;
 152
 153         gob_size_bytes = gob_height * NV_BLOCKLINEAR_GOB_WIDTH;
 154         gob_size_pixels = gob_height * gob_width;
 155
 156         gob_count_x = DIV_ROUND_UP(bo->strides[0], NV_BLOCKLINEAR_GOB_WIDTH);
 157         gob_count_y = DIV_ROUND_UP(bo->height, gob_height);
 158
 159         offset = 0;
 160         for (j = 0; j < gob_count_y; j++) {
 161                 gob_top = j * gob_height;
 162                 for (i = 0; i < gob_count_x; i++) {
 163                         tmp = tiled + offset;
 164                         gob_left = i * gob_width;
 165
 166                         transfer_tile(bo, tmp, untiled, type, bytes_per_pixel,
 167                                       gob_top, gob_left, gob_size_pixels);
 168
 169                         offset += gob_size_bytes;
 170                 }
 171         }
 172 }
 173
 174 static int tegra_init(struct driver *drv)
 175 {
 176         int ret;
 177         struct format_metadata metadata;
 178         uint64_t flags = BO_COMMON_USE_MASK;
 179
 180         metadata.tiling = NV_MEM_KIND_PITCH;
 181         metadata.priority = 1;
 182         metadata.modifier = DRM_FORMAT_MOD_NONE;
 183
 184         ret = drv_add_combinations(drv, supported_formats,
 185                                    ARRAY_SIZE(supported_formats), &metadata,
 186                                    flags);
 187         if (ret)
 188                 return ret;
 189
 190         drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata,
 191                                BO_USE_CURSOR | BO_USE_SCANOUT);
 192         drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata,
 193                                BO_USE_CURSOR | BO_USE_SCANOUT);
 194
 195         flags &= ~BO_USE_SW_WRITE_OFTEN;
 196         flags &= ~BO_USE_SW_READ_OFTEN;
 197         flags &= ~BO_USE_LINEAR;
 198
 199         metadata.tiling = NV_MEM_KIND_C32_2CRA;
 200         metadata.priority = 2;
 201
 202         ret = drv_add_combinations(drv, supported_formats,
 203                                    ARRAY_SIZE(supported_formats), &metadata,
 204                                    flags);
 205         if (ret)
 206                 return ret;
 207
 208         drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata,
 209                                BO_USE_SCANOUT);
 210         drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata,
 211                                BO_USE_SCANOUT);
 212         return 0;
 213 }
 214
 215 static int tegra_bo_create(struct bo *bo, uint32_t width, uint32_t height,
 216                            uint32_t format, uint32_t flags)
 217 {
 218         uint32_t size, stride, block_height_log2 = 0;
 219         enum nv_mem_kind kind = NV_MEM_KIND_PITCH;
 220         struct drm_tegra_gem_create gem_create;
 221         int ret;
 222
 223         if (flags & (BO_USE_CURSOR | BO_USE_LINEAR |
 224                      BO_USE_SW_READ_OFTEN | BO_USE_SW_WRITE_OFTEN))
 225                 compute_layout_linear(width, height, format, &stride, &size);
 226         else
 227                 compute_layout_blocklinear(width, height, format, &kind,
 228                                            &block_height_log2, &stride, &size);
 229
 230         memset(&gem_create, 0, sizeof(gem_create));
 231         gem_create.size = size;
 232         gem_create.flags = 0;
 233
 234         ret = drmIoctl(bo->drv->fd, DRM_IOCTL_TEGRA_GEM_CREATE, &gem_create);
 235         if (ret) {
 236                 fprintf(stderr, "drv: DRM_IOCTL_TEGRA_GEM_CREATE failed "
 237                                 "(size=%zu)\n", size);
 238                 return ret;
 239         }
 240
 241         bo->handles[0].u32 = gem_create.handle;
 242         bo->offsets[0] = 0;
 243         bo->total_size = bo->sizes[0] = size;
 244         bo->strides[0] = stride;
 245
 246         if (kind != NV_MEM_KIND_PITCH) {
 247                 struct drm_tegra_gem_set_tiling gem_tile;
 248
 249                 memset(&gem_tile, 0, sizeof(gem_tile));
 250                 gem_tile.handle = bo->handles[0].u32;
 251                 gem_tile.mode = DRM_TEGRA_GEM_TILING_MODE_BLOCK;
 252                 gem_tile.value = block_height_log2;
 253
 254                 ret = drmCommandWriteRead(bo->drv->fd, DRM_TEGRA_GEM_SET_TILING,
 255                                           &gem_tile, sizeof(gem_tile));
 256                 if (ret < 0) {
 257                         drv_gem_bo_destroy(bo);
 258                         return ret;
 259                 }
 260
 261                 /* Encode blocklinear parameters for EGLImage creation. */
 262                 bo->tiling = (kind & 0xff) |
 263                              ((block_height_log2 & 0xf) << 8);
 264                 bo->format_modifiers[0] = fourcc_mod_code(NV, bo->tiling);
 265         }
 266
 267         return 0;
 268 }
 269
 270 static void *tegra_bo_map(struct bo *bo, struct map_info *data, size_t plane)
 271 {
 272         int ret;
 273         struct drm_tegra_gem_mmap gem_map;
 274         struct tegra_private_map_data *priv;
 275
 276         memset(&gem_map, 0, sizeof(gem_map));
 277         gem_map.handle = bo->handles[0].u32;
 278
 279         ret = drmCommandWriteRead(bo->drv->fd, DRM_TEGRA_GEM_MMAP, &gem_map,
 280                                   sizeof(gem_map));
 281         if (ret < 0) {
 282                 fprintf(stderr, "drv: DRM_TEGRA_GEM_MMAP failed\n");
 283                 return MAP_FAILED;
 284         }
 285
 286         void *addr = mmap(0, bo->total_size, PROT_READ | PROT_WRITE, MAP_SHARED,
 287                           bo->drv->fd, gem_map.offset);
 288
 289         data->length = bo->total_size;
 290
 291         if ((bo->tiling & 0xFF) == NV_MEM_KIND_C32_2CRA && addr != MAP_FAILED) {
 292                 priv = calloc(1, sizeof(*priv));
 293                 priv->untiled = calloc(1, bo->total_size);
 294                 priv->tiled = addr;
 295                 data->priv = priv;
 296                 transfer_tiled_memory(bo, priv->tiled, priv->untiled,
 297                                       TEGRA_READ_TILED_BUFFER);
 298                 addr = priv->untiled;
 299         }
 300
 301         return addr;
 302 }
 303
 304 static int tegra_bo_unmap(struct bo *bo, struct map_info *data)
 305 {
 306         if (data->priv) {
 307                 struct tegra_private_map_data *priv = data->priv;
 308                 transfer_tiled_memory(bo, priv->tiled, priv->untiled,
 309                                       TEGRA_WRITE_TILED_BUFFER);
 310                 data->addr = priv->tiled;
 311                 free(priv->untiled);
 312                 free(priv);
 313                 data->priv = NULL;
 314         }
 315
 316         return munmap(data->addr, data->length);
 317 }
 318
 319 struct backend backend_tegra =
 320 {
 321         .name = "tegra",
 322         .init = tegra_init,
 323         .bo_create = tegra_bo_create,
 324         .bo_destroy = drv_gem_bo_destroy,
 325         .bo_import = drv_prime_bo_import,
 326         .bo_map = tegra_bo_map,
 327         .bo_unmap = tegra_bo_unmap,
 328 };
 329
 330 #endif