tegra.c

   1 /*
   2  * Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
   3  * Use of this source code is governed by a BSD-style license that can be
   4  * found in the LICENSE file.
   5  */
   6
   7 #ifdef DRV_TEGRA
   8
   9 #include <stdio.h>
  10 #include <string.h>
  11 #include <sys/mman.h>
  12 #include <xf86drm.h>
  13 #include <tegra_drm.h>
  14
  15 #include "drv_priv.h"
  16 #include "helpers.h"
  17 #include "util.h"
  18
  19 /*
  20  * GOB (Group Of Bytes) is the basic unit of the blocklinear layout.
  21  * GOBs are arranged to blocks, where the height of the block (measured
  22  * in GOBs) is configurable.
  23  */
  24 #define NV_BLOCKLINEAR_GOB_HEIGHT 8
  25 #define NV_BLOCKLINEAR_GOB_WIDTH 64
  26 #define NV_DEFAULT_BLOCK_HEIGHT_LOG2 4
  27 #define NV_PREFERRED_PAGE_SIZE (128 * 1024)
  28
  29 enum nv_mem_kind
  30 {
  31         NV_MEM_KIND_PITCH = 0,
  32         NV_MEM_KIND_C32_2CRA = 0xdb,
  33         NV_MEM_KIND_GENERIC_16Bx2 = 0xfe,
  34 };
  35
  36 static int compute_block_height_log2(int height)
  37 {
  38         int block_height_log2 = NV_DEFAULT_BLOCK_HEIGHT_LOG2;
  39
  40         if (block_height_log2 > 0) {
  41                 /* Shrink, if a smaller block height could cover the whole
  42                  * surface height. */
  43                 int proposed = NV_BLOCKLINEAR_GOB_HEIGHT << (block_height_log2 - 1);
  44                 while (proposed >= height) {
  45                         block_height_log2--;
  46                         if (block_height_log2 == 0)
  47                                 break;
  48                         proposed /= 2;
  49                 }
  50         }
  51         return block_height_log2;
  52 }
  53
  54 static void compute_layout_blocklinear(int width, int height, int format,
  55                                        enum nv_mem_kind *kind,
  56                                        uint32_t *block_height_log2,
  57                                        uint32_t *stride, uint32_t *size)
  58 {
  59         int pitch = drv_stride_from_format(format, width, 0);
  60
  61         /* Align to blocklinear blocks. */
  62         pitch = ALIGN(pitch, NV_BLOCKLINEAR_GOB_WIDTH);
  63
  64         /* Compute padded height. */
  65         *block_height_log2 = compute_block_height_log2(height);
  66         int block_height = 1 << *block_height_log2;
  67         int padded_height =
  68                 ALIGN(height, NV_BLOCKLINEAR_GOB_HEIGHT * block_height);
  69
  70         int bytes = pitch * padded_height;
  71
  72         /* Pad the allocation to the preferred page size.
  73          * This will reduce the required page table size (see discussion in NV
  74          * bug 1321091), and also acts as a WAR for NV bug 1325421.
  75          */
  76         bytes = ALIGN(bytes, NV_PREFERRED_PAGE_SIZE);
  77
  78         *kind = NV_MEM_KIND_C32_2CRA;
  79         *stride = pitch;
  80         *size = bytes;
  81 }
  82
  83 static void compute_layout_linear(int width, int height, int format,
  84                                   uint32_t *stride, uint32_t *size)
  85 {
  86         *stride = drv_stride_from_format(format, width, 0);
  87         *size = *stride * height;
  88 }
  89
  90 static int tegra_bo_create(struct bo *bo, uint32_t width, uint32_t height,
  91                            uint32_t format, uint32_t flags)
  92 {
  93         uint32_t size, stride, block_height_log2 = 0;
  94         enum nv_mem_kind kind = NV_MEM_KIND_PITCH;
  95         struct drm_tegra_gem_create gem_create;
  96         int ret;
  97
  98         if (flags & DRV_BO_USE_RENDERING)
  99                 compute_layout_blocklinear(width, height, format, &kind,
 100                                            &block_height_log2, &stride, &size);
 101         else
 102                 compute_layout_linear(width, height, format, &stride, &size);
 103
 104         memset(&gem_create, 0, sizeof(gem_create));
 105         gem_create.size = size;
 106         gem_create.flags = 0;
 107
 108         ret = drmIoctl(bo->drv->fd, DRM_IOCTL_TEGRA_GEM_CREATE, &gem_create);
 109         if (ret) {
 110                 fprintf(stderr, "drv: DRM_IOCTL_TEGRA_GEM_CREATE failed "
 111                                 "(size=%zu)\n", size);
 112                 return ret;
 113         }
 114
 115         bo->handles[0].u32 = gem_create.handle;
 116         bo->offsets[0] = 0;
 117         bo->sizes[0] = size;
 118         bo->strides[0] = stride;
 119
 120         if (kind != NV_MEM_KIND_PITCH) {
 121                 struct drm_tegra_gem_set_tiling gem_tile;
 122
 123                 memset(&gem_tile, 0, sizeof(gem_tile));
 124                 gem_tile.handle = bo->handles[0].u32;
 125                 gem_tile.mode = DRM_TEGRA_GEM_TILING_MODE_BLOCK;
 126                 gem_tile.value = block_height_log2;
 127
 128                 ret = drmCommandWriteRead(bo->drv->fd, DRM_TEGRA_GEM_SET_TILING,
 129                                           &gem_tile, sizeof(gem_tile));
 130                 if (ret < 0) {
 131                         drv_gem_bo_destroy(bo);
 132                         return ret;
 133                 }
 134
 135                 /* Encode blocklinear parameters for EGLImage creation. */
 136                 bo->tiling = (kind & 0xff) |
 137                              ((block_height_log2 & 0xf) << 8);
 138                 bo->format_modifiers[0] = drv_fourcc_mod_code(NV, bo->tiling);
 139         }
 140
 141         return 0;
 142 }
 143
 144 static void *tegra_bo_map(struct bo *bo)
 145 {
 146         int ret;
 147         struct drm_tegra_gem_mmap gem_map;
 148
 149         memset(&gem_map, 0, sizeof(gem_map));
 150         gem_map.handle = bo->handles[0].u32;
 151
 152         ret = drmCommandWriteRead(bo->drv->fd, DRM_TEGRA_GEM_MMAP, &gem_map,
 153                                   sizeof(gem_map));
 154         if (ret < 0) {
 155                 fprintf(stderr, "drv: DRM_TEGRA_GEM_MMAP failed\n");
 156                 return MAP_FAILED;
 157         }
 158
 159         return mmap(0, bo->sizes[0], PROT_READ | PROT_WRITE, MAP_SHARED,
 160                     bo->drv->fd, gem_map.offset);
 161 }
 162
 163 const struct backend backend_tegra =
 164 {
 165         .name = "tegra",
 166         .bo_create = tegra_bo_create,
 167         .bo_destroy = drv_gem_bo_destroy,
 168         .bo_map = tegra_bo_map,
 169         .format_list = {
 170                 /* Linear support */
 171                 {DRV_FORMAT_XRGB8888, DRV_BO_USE_SCANOUT | DRV_BO_USE_CURSOR |
 172                                       DRV_BO_USE_LINEAR | DRV_BO_USE_SW_READ_OFTEN |
 173                                       DRV_BO_USE_SW_WRITE_OFTEN},
 174                 {DRV_FORMAT_ARGB8888, DRV_BO_USE_SCANOUT | DRV_BO_USE_CURSOR |
 175                                       DRV_BO_USE_LINEAR | DRV_BO_USE_SW_READ_OFTEN |
 176                                       DRV_BO_USE_SW_WRITE_OFTEN},
 177                 /* Blocklinear support */
 178                 {DRV_FORMAT_XRGB8888, DRV_BO_USE_SCANOUT | DRV_BO_USE_RENDERING |
 179                                       DRV_BO_USE_HW_TEXTURE | DRV_BO_USE_HW_RENDER |
 180                                       DRV_BO_USE_HW_2D | DRV_BO_USE_SW_READ_RARELY |
 181                                       DRV_BO_USE_SW_WRITE_RARELY},
 182                 {DRV_FORMAT_ARGB8888, DRV_BO_USE_SCANOUT | DRV_BO_USE_RENDERING |
 183                                       DRV_BO_USE_HW_TEXTURE | DRV_BO_USE_HW_RENDER |
 184                                       DRV_BO_USE_HW_2D | DRV_BO_USE_SW_READ_RARELY |
 185                                       DRV_BO_USE_SW_WRITE_RARELY},
 186         }
 187 };
 188
 189 #endif