virtio_gpu.c

   1 /*
   2  * Copyright 2017 The Chromium OS Authors. All rights reserved.
   3  * Use of this source code is governed by a BSD-style license that can be
   4  * found in the LICENSE file.
   5  */
   6
   7 #include <assert.h>
   8 #include <errno.h>
   9 #include <stdint.h>
  10 #include <stdio.h>
  11 #include <string.h>
  12 #include <sys/mman.h>
  13 #include <xf86drm.h>
  14
  15 #include "drv_priv.h"
  16 #include "external/virgl_hw.h"
  17 #include "external/virgl_protocol.h"
  18 #include "external/virtgpu_drm.h"
  19 #include "helpers.h"
  20 #include "util.h"
  21
  22 #ifndef PAGE_SIZE
  23 #define PAGE_SIZE 0x1000
  24 #endif
  25 #define PIPE_TEXTURE_2D 2
  26
  27 #define MESA_LLVMPIPE_TILE_ORDER 6
  28 #define MESA_LLVMPIPE_TILE_SIZE (1 << MESA_LLVMPIPE_TILE_ORDER)
  29
  30 struct feature {
  31         uint64_t feature;
  32         const char *name;
  33         uint32_t enabled;
  34 };
  35
  36 enum feature_id {
  37         feat_3d,
  38         feat_capset_fix,
  39         feat_resource_blob,
  40         feat_host_visible,
  41         feat_host_cross_device,
  42         feat_max,
  43 };
  44
  45 #define FEATURE(x)                                                                                 \
  46         (struct feature)                                                                           \
  47         {                                                                                          \
  48                 x, #x, 0                                                                           \
  49         }
  50
  51 static struct feature features[] = {
  52         FEATURE(VIRTGPU_PARAM_3D_FEATURES),   FEATURE(VIRTGPU_PARAM_CAPSET_QUERY_FIX),
  53         FEATURE(VIRTGPU_PARAM_RESOURCE_BLOB), FEATURE(VIRTGPU_PARAM_HOST_VISIBLE),
  54         FEATURE(VIRTGPU_PARAM_CROSS_DEVICE),
  55 };
  56
  57 static const uint32_t render_target_formats[] = { DRM_FORMAT_ABGR8888, DRM_FORMAT_ARGB8888,
  58                                                   DRM_FORMAT_RGB565, DRM_FORMAT_XBGR8888,
  59                                                   DRM_FORMAT_XRGB8888 };
  60
  61 static const uint32_t dumb_texture_source_formats[] = {
  62         DRM_FORMAT_R8,   DRM_FORMAT_R16,  DRM_FORMAT_YVU420,
  63         DRM_FORMAT_NV12, DRM_FORMAT_NV21, DRM_FORMAT_YVU420_ANDROID
  64 };
  65
  66 static const uint32_t texture_source_formats[] = { DRM_FORMAT_NV12, DRM_FORMAT_NV21,
  67                                                    DRM_FORMAT_R8,   DRM_FORMAT_R16,
  68                                                    DRM_FORMAT_RG88, DRM_FORMAT_YVU420_ANDROID };
  69
  70 struct virtio_gpu_priv {
  71         int caps_is_v2;
  72         union virgl_caps caps;
  73         int host_gbm_enabled;
  74 };
  75
  76 static uint32_t translate_format(uint32_t drm_fourcc)
  77 {
  78         switch (drm_fourcc) {
  79         case DRM_FORMAT_BGR888:
  80         case DRM_FORMAT_RGB888:
  81                 return VIRGL_FORMAT_R8G8B8_UNORM;
  82         case DRM_FORMAT_XRGB8888:
  83                 return VIRGL_FORMAT_B8G8R8X8_UNORM;
  84         case DRM_FORMAT_ARGB8888:
  85                 return VIRGL_FORMAT_B8G8R8A8_UNORM;
  86         case DRM_FORMAT_XBGR8888:
  87                 return VIRGL_FORMAT_R8G8B8X8_UNORM;
  88         case DRM_FORMAT_ABGR8888:
  89                 return VIRGL_FORMAT_R8G8B8A8_UNORM;
  90         case DRM_FORMAT_ABGR16161616F:
  91                 return VIRGL_FORMAT_R16G16B16A16_UNORM;
  92         case DRM_FORMAT_RGB565:
  93                 return VIRGL_FORMAT_B5G6R5_UNORM;
  94         case DRM_FORMAT_R8:
  95                 return VIRGL_FORMAT_R8_UNORM;
  96         case DRM_FORMAT_RG88:
  97                 return VIRGL_FORMAT_R8G8_UNORM;
  98         case DRM_FORMAT_NV12:
  99                 return VIRGL_FORMAT_NV12;
 100         case DRM_FORMAT_NV21:
 101                 return VIRGL_FORMAT_NV21;
 102         case DRM_FORMAT_YVU420:
 103         case DRM_FORMAT_YVU420_ANDROID:
 104                 return VIRGL_FORMAT_YV12;
 105         default:
 106                 return 0;
 107         }
 108 }
 109
 110 static bool virtio_gpu_bitmask_supports_format(struct virgl_supported_format_mask *supported,
 111                                                uint32_t drm_format)
 112 {
 113         uint32_t virgl_format = translate_format(drm_format);
 114         if (!virgl_format) {
 115                 return false;
 116         }
 117
 118         uint32_t bitmask_index = virgl_format / 32;
 119         uint32_t bit_index = virgl_format % 32;
 120         return supported->bitmask[bitmask_index] & (1 << bit_index);
 121 }
 122
 123 // The metadata generated here for emulated buffers is slightly different than the metadata
 124 // generated by drv_bo_from_format. In order to simplify transfers in the flush and invalidate
 125 // functions below, the emulated buffers are oversized. For example, ignoring stride alignment
 126 // requirements to demonstrate, a 6x6 YUV420 image buffer might have the following layout from
 127 // drv_bo_from_format:
 128 //
 129 // | Y | Y | Y | Y | Y | Y |
 130 // | Y | Y | Y | Y | Y | Y |
 131 // | Y | Y | Y | Y | Y | Y |
 132 // | Y | Y | Y | Y | Y | Y |
 133 // | Y | Y | Y | Y | Y | Y |
 134 // | Y | Y | Y | Y | Y | Y |
 135 // | U | U | U | U | U | U |
 136 // | U | U | U | V | V | V |
 137 // | V | V | V | V | V | V |
 138 //
 139 // where each plane immediately follows the previous plane in memory. This layout makes it
 140 // difficult to compute the transfers needed for example when the middle 2x2 region of the
 141 // image is locked and needs to be flushed/invalidated.
 142 //
 143 // Emulated multi-plane buffers instead have a layout of:
 144 //
 145 // | Y | Y | Y | Y | Y | Y |
 146 // | Y | Y | Y | Y | Y | Y |
 147 // | Y | Y | Y | Y | Y | Y |
 148 // | Y | Y | Y | Y | Y | Y |
 149 // | Y | Y | Y | Y | Y | Y |
 150 // | Y | Y | Y | Y | Y | Y |
 151 // | U | U | U |   |   |   |
 152 // | U | U | U |   |   |   |
 153 // | U | U | U |   |   |   |
 154 // | V | V | V |   |   |   |
 155 // | V | V | V |   |   |   |
 156 // | V | V | V |   |   |   |
 157 //
 158 // where each plane is placed as a sub-image (albeit with a very large stride) in order to
 159 // simplify transfers into 3 sub-image transfers for the above example.
 160 //
 161 // Additional note: the V-plane is not placed to the right of the U-plane due to some
 162 // observed failures in media framework code which assumes the V-plane is not
 163 // "row-interlaced" with the U-plane.
 164 static void virtio_gpu_get_emulated_metadata(const struct bo *bo, struct bo_metadata *metadata)
 165 {
 166         uint32_t y_plane_height;
 167         uint32_t c_plane_height;
 168         uint32_t original_width = bo->meta.width;
 169         uint32_t original_height = bo->meta.height;
 170
 171         metadata->format = DRM_FORMAT_R8;
 172         switch (bo->meta.format) {
 173         case DRM_FORMAT_NV12:
 174         case DRM_FORMAT_NV21:
 175                 // Bi-planar
 176                 metadata->num_planes = 2;
 177
 178                 y_plane_height = original_height;
 179                 c_plane_height = DIV_ROUND_UP(original_height, 2);
 180
 181                 metadata->width = original_width;
 182                 metadata->height = y_plane_height + c_plane_height;
 183
 184                 // Y-plane (full resolution)
 185                 metadata->strides[0] = metadata->width;
 186                 metadata->offsets[0] = 0;
 187                 metadata->sizes[0] = metadata->width * y_plane_height;
 188
 189                 // CbCr-plane  (half resolution, interleaved, placed below Y-plane)
 190                 metadata->strides[1] = metadata->width;
 191                 metadata->offsets[1] = metadata->offsets[0] + metadata->sizes[0];
 192                 metadata->sizes[1] = metadata->width * c_plane_height;
 193
 194                 metadata->total_size = metadata->width * metadata->height;
 195                 break;
 196         case DRM_FORMAT_YVU420:
 197         case DRM_FORMAT_YVU420_ANDROID:
 198                 // Tri-planar
 199                 metadata->num_planes = 3;
 200
 201                 y_plane_height = original_height;
 202                 c_plane_height = DIV_ROUND_UP(original_height, 2);
 203
 204                 metadata->width = ALIGN(original_width, 32);
 205                 metadata->height = y_plane_height + (2 * c_plane_height);
 206
 207                 // Y-plane (full resolution)
 208                 metadata->strides[0] = metadata->width;
 209                 metadata->offsets[0] = 0;
 210                 metadata->sizes[0] = metadata->width * original_height;
 211
 212                 // Cb-plane (half resolution, placed below Y-plane)
 213                 metadata->strides[1] = metadata->width;
 214                 metadata->offsets[1] = metadata->offsets[0] + metadata->sizes[0];
 215                 metadata->sizes[1] = metadata->width * c_plane_height;
 216
 217                 // Cr-plane (half resolution, placed below Cb-plane)
 218                 metadata->strides[2] = metadata->width;
 219                 metadata->offsets[2] = metadata->offsets[1] + metadata->sizes[1];
 220                 metadata->sizes[2] = metadata->width * c_plane_height;
 221
 222                 metadata->total_size = metadata->width * metadata->height;
 223                 break;
 224         default:
 225                 break;
 226         }
 227 }
 228
 229 struct virtio_transfers_params {
 230         size_t xfers_needed;
 231         struct rectangle xfer_boxes[DRV_MAX_PLANES];
 232 };
 233
 234 static void virtio_gpu_get_emulated_transfers_params(const struct bo *bo,
 235                                                      const struct rectangle *transfer_box,
 236                                                      struct virtio_transfers_params *xfer_params)
 237 {
 238         uint32_t y_plane_height;
 239         uint32_t c_plane_height;
 240         struct bo_metadata emulated_metadata;
 241
 242         if (transfer_box->x == 0 && transfer_box->y == 0 && transfer_box->width == bo->meta.width &&
 243             transfer_box->height == bo->meta.height) {
 244                 virtio_gpu_get_emulated_metadata(bo, &emulated_metadata);
 245
 246                 xfer_params->xfers_needed = 1;
 247                 xfer_params->xfer_boxes[0].x = 0;
 248                 xfer_params->xfer_boxes[0].y = 0;
 249                 xfer_params->xfer_boxes[0].width = emulated_metadata.width;
 250                 xfer_params->xfer_boxes[0].height = emulated_metadata.height;
 251
 252                 return;
 253         }
 254
 255         switch (bo->meta.format) {
 256         case DRM_FORMAT_NV12:
 257         case DRM_FORMAT_NV21:
 258                 // Bi-planar
 259                 xfer_params->xfers_needed = 2;
 260
 261                 y_plane_height = bo->meta.height;
 262                 c_plane_height = DIV_ROUND_UP(bo->meta.height, 2);
 263
 264                 // Y-plane (full resolution)
 265                 xfer_params->xfer_boxes[0].x = transfer_box->x;
 266                 xfer_params->xfer_boxes[0].y = transfer_box->y;
 267                 xfer_params->xfer_boxes[0].width = transfer_box->width;
 268                 xfer_params->xfer_boxes[0].height = transfer_box->height;
 269
 270                 // CbCr-plane (half resolution, interleaved, placed below Y-plane)
 271                 xfer_params->xfer_boxes[1].x = transfer_box->x;
 272                 xfer_params->xfer_boxes[1].y = transfer_box->y + y_plane_height;
 273                 xfer_params->xfer_boxes[1].width = transfer_box->width;
 274                 xfer_params->xfer_boxes[1].height = DIV_ROUND_UP(transfer_box->height, 2);
 275
 276                 break;
 277         case DRM_FORMAT_YVU420:
 278         case DRM_FORMAT_YVU420_ANDROID:
 279                 // Tri-planar
 280                 xfer_params->xfers_needed = 3;
 281
 282                 y_plane_height = bo->meta.height;
 283                 c_plane_height = DIV_ROUND_UP(bo->meta.height, 2);
 284
 285                 // Y-plane (full resolution)
 286                 xfer_params->xfer_boxes[0].x = transfer_box->x;
 287                 xfer_params->xfer_boxes[0].y = transfer_box->y;
 288                 xfer_params->xfer_boxes[0].width = transfer_box->width;
 289                 xfer_params->xfer_boxes[0].height = transfer_box->height;
 290
 291                 // Cb-plane (half resolution, placed below Y-plane)
 292                 xfer_params->xfer_boxes[1].x = transfer_box->x;
 293                 xfer_params->xfer_boxes[1].y = transfer_box->y + y_plane_height;
 294                 xfer_params->xfer_boxes[1].width = DIV_ROUND_UP(transfer_box->width, 2);
 295                 xfer_params->xfer_boxes[1].height = DIV_ROUND_UP(transfer_box->height, 2);
 296
 297                 // Cr-plane (half resolution, placed below Cb-plane)
 298                 xfer_params->xfer_boxes[2].x = transfer_box->x;
 299                 xfer_params->xfer_boxes[2].y = transfer_box->y + y_plane_height + c_plane_height;
 300                 xfer_params->xfer_boxes[2].width = DIV_ROUND_UP(transfer_box->width, 2);
 301                 xfer_params->xfer_boxes[2].height = DIV_ROUND_UP(transfer_box->height, 2);
 302
 303                 break;
 304         }
 305 }
 306
 307 static bool virtio_gpu_supports_combination_natively(struct driver *drv, uint32_t drm_format,
 308                                                      uint64_t use_flags)
 309 {
 310         struct virtio_gpu_priv *priv = (struct virtio_gpu_priv *)drv->priv;
 311
 312         if (priv->caps.max_version == 0) {
 313                 return true;
 314         }
 315
 316         if ((use_flags & BO_USE_RENDERING) &&
 317             !virtio_gpu_bitmask_supports_format(&priv->caps.v1.render, drm_format)) {
 318                 return false;
 319         }
 320
 321         if ((use_flags & BO_USE_TEXTURE) &&
 322             !virtio_gpu_bitmask_supports_format(&priv->caps.v1.sampler, drm_format)) {
 323                 return false;
 324         }
 325
 326         if ((use_flags & BO_USE_SCANOUT) && priv->caps_is_v2 &&
 327             !virtio_gpu_bitmask_supports_format(&priv->caps.v2.scanout, drm_format)) {
 328                 return false;
 329         }
 330
 331         return true;
 332 }
 333
 334 // For virtio backends that do not support formats natively (e.g. multi-planar formats are not
 335 // supported in virglrenderer when gbm is unavailable on the host machine), whether or not the
 336 // format and usage combination can be handled as a blob (byte buffer).
 337 static bool virtio_gpu_supports_combination_through_emulation(struct driver *drv,
 338                                                               uint32_t drm_format,
 339                                                               uint64_t use_flags)
 340 {
 341         struct virtio_gpu_priv *priv = (struct virtio_gpu_priv *)drv->priv;
 342
 343         // Only enable emulation on non-gbm virtio backends.
 344         if (priv->host_gbm_enabled) {
 345                 return false;
 346         }
 347
 348         if (use_flags & (BO_USE_RENDERING | BO_USE_SCANOUT)) {
 349                 return false;
 350         }
 351
 352         if (!virtio_gpu_supports_combination_natively(drv, DRM_FORMAT_R8, use_flags)) {
 353                 return false;
 354         }
 355
 356         return drm_format == DRM_FORMAT_NV12 || drm_format == DRM_FORMAT_NV21 ||
 357                drm_format == DRM_FORMAT_YVU420 || drm_format == DRM_FORMAT_YVU420_ANDROID;
 358 }
 359
 360 // Adds the given buffer combination to the list of supported buffer combinations if the
 361 // combination is supported by the virtio backend.
 362 static void virtio_gpu_add_combination(struct driver *drv, uint32_t drm_format,
 363                                        struct format_metadata *metadata, uint64_t use_flags)
 364 {
 365         struct virtio_gpu_priv *priv = (struct virtio_gpu_priv *)drv->priv;
 366
 367         if (features[feat_3d].enabled && priv->caps.max_version >= 1) {
 368                 if ((use_flags & BO_USE_SCANOUT) && priv->caps_is_v2 &&
 369                     !virtio_gpu_supports_combination_natively(drv, drm_format, use_flags)) {
 370                         drv_log("Scanout format: %d\n", drm_format);
 371                         use_flags &= ~BO_USE_SCANOUT;
 372                 }
 373
 374                 if (!virtio_gpu_supports_combination_natively(drv, drm_format, use_flags) &&
 375                     !virtio_gpu_supports_combination_through_emulation(drv, drm_format,
 376                                                                        use_flags)) {
 377                         drv_log("Skipping unsupported combination format:%d\n", drm_format);
 378                         return;
 379                 }
 380         }
 381
 382         drv_add_combination(drv, drm_format, metadata, use_flags);
 383 }
 384
 385 // Adds each given buffer combination to the list of supported buffer combinations if the
 386 // combination supported by the virtio backend.
 387 static void virtio_gpu_add_combinations(struct driver *drv, const uint32_t *drm_formats,
 388                                         uint32_t num_formats, struct format_metadata *metadata,
 389                                         uint64_t use_flags)
 390 {
 391         uint32_t i;
 392
 393         for (i = 0; i < num_formats; i++) {
 394                 virtio_gpu_add_combination(drv, drm_formats[i], metadata, use_flags);
 395         }
 396 }
 397
 398 static int virtio_dumb_bo_create(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
 399                                  uint64_t use_flags)
 400 {
 401         if (bo->meta.format != DRM_FORMAT_R8) {
 402                 width = ALIGN(width, MESA_LLVMPIPE_TILE_SIZE);
 403                 height = ALIGN(height, MESA_LLVMPIPE_TILE_SIZE);
 404         }
 405
 406         return drv_dumb_bo_create_ex(bo, width, height, format, use_flags, BO_QUIRK_DUMB32BPP);
 407 }
 408
 409 static inline void handle_flag(uint64_t *flag, uint64_t check_flag, uint32_t *bind,
 410                                uint32_t virgl_bind)
 411 {
 412         if ((*flag) & check_flag) {
 413                 (*flag) &= ~check_flag;
 414                 (*bind) |= virgl_bind;
 415         }
 416 }
 417
 418 static uint32_t use_flags_to_bind(uint64_t use_flags)
 419 {
 420         /* In crosvm, VIRGL_BIND_SHARED means minigbm will allocate, not virglrenderer. */
 421         uint32_t bind = VIRGL_BIND_SHARED;
 422
 423         handle_flag(&use_flags, BO_USE_TEXTURE, &bind, VIRGL_BIND_SAMPLER_VIEW);
 424         handle_flag(&use_flags, BO_USE_RENDERING, &bind, VIRGL_BIND_RENDER_TARGET);
 425         handle_flag(&use_flags, BO_USE_SCANOUT, &bind, VIRGL_BIND_SCANOUT);
 426         handle_flag(&use_flags, BO_USE_CURSOR, &bind, VIRGL_BIND_CURSOR);
 427         handle_flag(&use_flags, BO_USE_LINEAR, &bind, VIRGL_BIND_LINEAR);
 428
 429         if (use_flags & BO_USE_PROTECTED) {
 430                 handle_flag(&use_flags, BO_USE_PROTECTED, &bind, VIRGL_BIND_MINIGBM_PROTECTED);
 431         } else {
 432                 // Make sure we don't set both flags, since that could be mistaken for
 433                 // protected. Give OFTEN priority over RARELY.
 434                 if (use_flags & BO_USE_SW_READ_OFTEN) {
 435                         handle_flag(&use_flags, BO_USE_SW_READ_OFTEN, &bind,
 436                                     VIRGL_BIND_MINIGBM_SW_READ_OFTEN);
 437                 } else {
 438                         handle_flag(&use_flags, BO_USE_SW_READ_RARELY, &bind,
 439                                     VIRGL_BIND_MINIGBM_SW_READ_RARELY);
 440                 }
 441                 if (use_flags & BO_USE_SW_WRITE_OFTEN) {
 442                         handle_flag(&use_flags, BO_USE_SW_WRITE_OFTEN, &bind,
 443                                     VIRGL_BIND_MINIGBM_SW_WRITE_OFTEN);
 444                 } else {
 445                         handle_flag(&use_flags, BO_USE_SW_WRITE_RARELY, &bind,
 446                                     VIRGL_BIND_MINIGBM_SW_WRITE_RARELY);
 447                 }
 448         }
 449
 450         handle_flag(&use_flags, BO_USE_CAMERA_WRITE, &bind, VIRGL_BIND_MINIGBM_CAMERA_WRITE);
 451         handle_flag(&use_flags, BO_USE_CAMERA_READ, &bind, VIRGL_BIND_MINIGBM_CAMERA_READ);
 452         handle_flag(&use_flags, BO_USE_HW_VIDEO_DECODER, &bind,
 453                     VIRGL_BIND_MINIGBM_HW_VIDEO_DECODER);
 454         handle_flag(&use_flags, BO_USE_HW_VIDEO_ENCODER, &bind,
 455                     VIRGL_BIND_MINIGBM_HW_VIDEO_ENCODER);
 456
 457         if (use_flags) {
 458                 drv_log("Unhandled bo use flag: %llx\n", (unsigned long long)use_flags);
 459         }
 460
 461         return bind;
 462 }
 463
 464 static int virtio_virgl_bo_create(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
 465                                   uint64_t use_flags)
 466 {
 467         int ret;
 468         size_t i;
 469         uint32_t stride;
 470         struct drm_virtgpu_resource_create res_create;
 471         struct bo_metadata emulated_metadata;
 472
 473         if (virtio_gpu_supports_combination_natively(bo->drv, format, use_flags)) {
 474                 stride = drv_stride_from_format(format, width, 0);
 475                 drv_bo_from_format(bo, stride, height, format);
 476         } else {
 477                 assert(
 478                     virtio_gpu_supports_combination_through_emulation(bo->drv, format, use_flags));
 479
 480                 virtio_gpu_get_emulated_metadata(bo, &emulated_metadata);
 481
 482                 format = emulated_metadata.format;
 483                 width = emulated_metadata.width;
 484                 height = emulated_metadata.height;
 485                 for (i = 0; i < emulated_metadata.num_planes; i++) {
 486                         bo->meta.strides[i] = emulated_metadata.strides[i];
 487                         bo->meta.offsets[i] = emulated_metadata.offsets[i];
 488                         bo->meta.sizes[i] = emulated_metadata.sizes[i];
 489                 }
 490                 bo->meta.total_size = emulated_metadata.total_size;
 491         }
 492
 493         /*
 494          * Setting the target is intended to ensure this resource gets bound as a 2D
 495          * texture in the host renderer's GL state. All of these resource properties are
 496          * sent unchanged by the kernel to the host, which in turn sends them unchanged to
 497          * virglrenderer. When virglrenderer makes a resource, it will convert the target
 498          * enum to the equivalent one in GL and then bind the resource to that target.
 499          */
 500         memset(&res_create, 0, sizeof(res_create));
 501
 502         res_create.target = PIPE_TEXTURE_2D;
 503         res_create.format = translate_format(format);
 504         res_create.bind = use_flags_to_bind(use_flags);
 505         res_create.width = width;
 506         res_create.height = height;
 507
 508         /* For virgl 3D */
 509         res_create.depth = 1;
 510         res_create.array_size = 1;
 511         res_create.last_level = 0;
 512         res_create.nr_samples = 0;
 513
 514         res_create.size = ALIGN(bo->meta.total_size, PAGE_SIZE); // PAGE_SIZE = 0x1000
 515         ret = drmIoctl(bo->drv->fd, DRM_IOCTL_VIRTGPU_RESOURCE_CREATE, &res_create);
 516         if (ret) {
 517                 drv_log("DRM_IOCTL_VIRTGPU_RESOURCE_CREATE failed with %s\n", strerror(errno));
 518                 return ret;
 519         }
 520
 521         for (uint32_t plane = 0; plane < bo->meta.num_planes; plane++)
 522                 bo->handles[plane].u32 = res_create.bo_handle;
 523
 524         return 0;
 525 }
 526
 527 static void *virtio_virgl_bo_map(struct bo *bo, struct vma *vma, size_t plane, uint32_t map_flags)
 528 {
 529         int ret;
 530         struct drm_virtgpu_map gem_map;
 531
 532         memset(&gem_map, 0, sizeof(gem_map));
 533         gem_map.handle = bo->handles[0].u32;
 534
 535         ret = drmIoctl(bo->drv->fd, DRM_IOCTL_VIRTGPU_MAP, &gem_map);
 536         if (ret) {
 537                 drv_log("DRM_IOCTL_VIRTGPU_MAP failed with %s\n", strerror(errno));
 538                 return MAP_FAILED;
 539         }
 540
 541         vma->length = bo->meta.total_size;
 542         return mmap(0, bo->meta.total_size, drv_get_prot(map_flags), MAP_SHARED, bo->drv->fd,
 543                     gem_map.offset);
 544 }
 545
 546 static int virtio_gpu_get_caps(struct driver *drv, union virgl_caps *caps, int *caps_is_v2)
 547 {
 548         int ret;
 549         struct drm_virtgpu_get_caps cap_args;
 550
 551         *caps_is_v2 = 0;
 552         memset(&cap_args, 0, sizeof(cap_args));
 553         cap_args.addr = (unsigned long long)caps;
 554         if (features[feat_capset_fix].enabled) {
 555                 *caps_is_v2 = 1;
 556                 cap_args.cap_set_id = 2;
 557                 cap_args.size = sizeof(union virgl_caps);
 558         } else {
 559                 cap_args.cap_set_id = 1;
 560                 cap_args.size = sizeof(struct virgl_caps_v1);
 561         }
 562
 563         ret = drmIoctl(drv->fd, DRM_IOCTL_VIRTGPU_GET_CAPS, &cap_args);
 564         if (ret) {
 565                 drv_log("DRM_IOCTL_VIRTGPU_GET_CAPS failed with %s\n", strerror(errno));
 566                 *caps_is_v2 = 0;
 567
 568                 // Fallback to v1
 569                 cap_args.cap_set_id = 1;
 570                 cap_args.size = sizeof(struct virgl_caps_v1);
 571
 572                 ret = drmIoctl(drv->fd, DRM_IOCTL_VIRTGPU_GET_CAPS, &cap_args);
 573                 if (ret) {
 574                         drv_log("DRM_IOCTL_VIRTGPU_GET_CAPS failed with %s\n", strerror(errno));
 575                 }
 576         }
 577
 578         return ret;
 579 }
 580
 581 static void virtio_gpu_init_features_and_caps(struct driver *drv)
 582 {
 583         struct virtio_gpu_priv *priv = (struct virtio_gpu_priv *)drv->priv;
 584
 585         for (uint32_t i = 0; i < ARRAY_SIZE(features); i++) {
 586                 struct drm_virtgpu_getparam params = { 0 };
 587
 588                 params.param = features[i].feature;
 589                 params.value = (uint64_t)(uintptr_t)&features[i].enabled;
 590                 int ret = drmIoctl(drv->fd, DRM_IOCTL_VIRTGPU_GETPARAM, &params);
 591                 if (ret)
 592                         drv_log("DRM_IOCTL_VIRTGPU_GET_PARAM failed with %s\n", strerror(errno));
 593         }
 594
 595         if (features[feat_3d].enabled) {
 596                 virtio_gpu_get_caps(drv, &priv->caps, &priv->caps_is_v2);
 597         }
 598
 599         // Multi-planar formats are currently only supported in virglrenderer through gbm.
 600         priv->host_gbm_enabled =
 601             virtio_gpu_supports_combination_natively(drv, DRM_FORMAT_NV12, BO_USE_TEXTURE);
 602 }
 603
 604 static int virtio_gpu_init(struct driver *drv)
 605 {
 606         struct virtio_gpu_priv *priv;
 607
 608         priv = calloc(1, sizeof(*priv));
 609         drv->priv = priv;
 610
 611         virtio_gpu_init_features_and_caps(drv);
 612
 613         if (features[feat_3d].enabled) {
 614                 /* This doesn't mean host can scanout everything, it just means host
 615                  * hypervisor can show it. */
 616                 virtio_gpu_add_combinations(drv, render_target_formats,
 617                                             ARRAY_SIZE(render_target_formats), &LINEAR_METADATA,
 618                                             BO_USE_RENDER_MASK | BO_USE_SCANOUT);
 619                 virtio_gpu_add_combinations(drv, texture_source_formats,
 620                                             ARRAY_SIZE(texture_source_formats), &LINEAR_METADATA,
 621                                             BO_USE_TEXTURE_MASK);
 622         } else {
 623                 /* Virtio primary plane only allows this format. */
 624                 virtio_gpu_add_combination(drv, DRM_FORMAT_XRGB8888, &LINEAR_METADATA,
 625                                            BO_USE_RENDER_MASK | BO_USE_SCANOUT);
 626                 /* Virtio cursor plane only allows this format and Chrome cannot live without
 627                  * ARGB888 renderable format. */
 628                 virtio_gpu_add_combination(drv, DRM_FORMAT_ARGB8888, &LINEAR_METADATA,
 629                                            BO_USE_RENDER_MASK | BO_USE_CURSOR);
 630                 /* Android needs more, but they cannot be bound as scanouts anymore after
 631                  * "drm/virtio: fix DRM_FORMAT_* handling" */
 632                 virtio_gpu_add_combinations(drv, render_target_formats,
 633                                             ARRAY_SIZE(render_target_formats), &LINEAR_METADATA,
 634                                             BO_USE_RENDER_MASK);
 635                 virtio_gpu_add_combinations(drv, dumb_texture_source_formats,
 636                                             ARRAY_SIZE(dumb_texture_source_formats),
 637                                             &LINEAR_METADATA, BO_USE_TEXTURE_MASK);
 638                 virtio_gpu_add_combination(drv, DRM_FORMAT_NV12, &LINEAR_METADATA,
 639                                            BO_USE_SW_MASK | BO_USE_LINEAR);
 640                 virtio_gpu_add_combination(drv, DRM_FORMAT_NV21, &LINEAR_METADATA,
 641                                            BO_USE_SW_MASK | BO_USE_LINEAR);
 642         }
 643
 644         /* Android CTS tests require this. */
 645         virtio_gpu_add_combination(drv, DRM_FORMAT_RGB888, &LINEAR_METADATA, BO_USE_SW_MASK);
 646         virtio_gpu_add_combination(drv, DRM_FORMAT_BGR888, &LINEAR_METADATA, BO_USE_SW_MASK);
 647         virtio_gpu_add_combination(drv, DRM_FORMAT_ABGR16161616F, &LINEAR_METADATA,
 648                                    BO_USE_SW_MASK | BO_USE_TEXTURE_MASK);
 649
 650         drv_modify_combination(drv, DRM_FORMAT_ABGR8888, &LINEAR_METADATA,
 651                                BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE | BO_USE_HW_VIDEO_DECODER |
 652                                    BO_USE_HW_VIDEO_ENCODER);
 653         drv_modify_combination(drv, DRM_FORMAT_XBGR8888, &LINEAR_METADATA,
 654                                BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE | BO_USE_HW_VIDEO_DECODER |
 655                                    BO_USE_HW_VIDEO_ENCODER);
 656         drv_modify_combination(drv, DRM_FORMAT_NV12, &LINEAR_METADATA,
 657                                BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE | BO_USE_HW_VIDEO_DECODER |
 658                                    BO_USE_HW_VIDEO_ENCODER);
 659         drv_modify_combination(drv, DRM_FORMAT_NV21, &LINEAR_METADATA,
 660                                BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE | BO_USE_HW_VIDEO_DECODER |
 661                                    BO_USE_HW_VIDEO_ENCODER);
 662         drv_modify_combination(drv, DRM_FORMAT_R16, &LINEAR_METADATA,
 663                                BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE | BO_USE_HW_VIDEO_DECODER);
 664         drv_modify_combination(drv, DRM_FORMAT_R8, &LINEAR_METADATA,
 665                                BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE | BO_USE_HW_VIDEO_DECODER |
 666                                    BO_USE_HW_VIDEO_ENCODER);
 667         drv_modify_combination(drv, DRM_FORMAT_YVU420, &LINEAR_METADATA,
 668                                BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE | BO_USE_HW_VIDEO_DECODER |
 669                                    BO_USE_HW_VIDEO_ENCODER);
 670         drv_modify_combination(drv, DRM_FORMAT_YVU420_ANDROID, &LINEAR_METADATA,
 671                                BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE | BO_USE_HW_VIDEO_DECODER |
 672                                    BO_USE_HW_VIDEO_ENCODER);
 673
 674         return drv_modify_linear_combinations(drv);
 675 }
 676
 677 static void virtio_gpu_close(struct driver *drv)
 678 {
 679         free(drv->priv);
 680         drv->priv = NULL;
 681 }
 682
 683 static int virtio_gpu_bo_create_blob(struct driver *drv, struct bo *bo)
 684 {
 685         int ret;
 686         uint32_t stride;
 687         uint32_t cmd[VIRGL_PIPE_RES_CREATE_SIZE + 1] = { 0 };
 688         struct drm_virtgpu_resource_create_blob drm_rc_blob = { 0 };
 689
 690         uint32_t blob_flags = VIRTGPU_BLOB_FLAG_USE_MAPPABLE | VIRTGPU_BLOB_FLAG_USE_SHAREABLE;
 691         if (bo->meta.use_flags & BO_USE_NON_GPU_HW) {
 692                 blob_flags |= VIRTGPU_BLOB_FLAG_USE_CROSS_DEVICE;
 693         }
 694
 695         stride = drv_stride_from_format(bo->meta.format, bo->meta.width, 0);
 696         drv_bo_from_format(bo, stride, bo->meta.height, bo->meta.format);
 697         bo->meta.total_size = ALIGN(bo->meta.total_size, PAGE_SIZE);
 698         bo->meta.tiling = blob_flags;
 699
 700         cmd[0] = VIRGL_CMD0(VIRGL_CCMD_PIPE_RESOURCE_CREATE, 0, VIRGL_PIPE_RES_CREATE_SIZE);
 701         cmd[VIRGL_PIPE_RES_CREATE_TARGET] = PIPE_TEXTURE_2D;
 702         cmd[VIRGL_PIPE_RES_CREATE_WIDTH] = bo->meta.width;
 703         cmd[VIRGL_PIPE_RES_CREATE_HEIGHT] = bo->meta.height;
 704         cmd[VIRGL_PIPE_RES_CREATE_FORMAT] = translate_format(bo->meta.format);
 705         cmd[VIRGL_PIPE_RES_CREATE_BIND] = use_flags_to_bind(bo->meta.use_flags);
 706         cmd[VIRGL_PIPE_RES_CREATE_DEPTH] = 1;
 707
 708         drm_rc_blob.cmd = (uint64_t)&cmd;
 709         drm_rc_blob.cmd_size = 4 * (VIRGL_PIPE_RES_CREATE_SIZE + 1);
 710         drm_rc_blob.size = bo->meta.total_size;
 711         drm_rc_blob.blob_mem = VIRTGPU_BLOB_MEM_HOST3D;
 712         drm_rc_blob.blob_flags = blob_flags;
 713
 714         ret = drmIoctl(drv->fd, DRM_IOCTL_VIRTGPU_RESOURCE_CREATE_BLOB, &drm_rc_blob);
 715         if (ret < 0) {
 716                 drv_log("DRM_VIRTGPU_RESOURCE_CREATE_BLOB failed with %s\n", strerror(errno));
 717                 return -errno;
 718         }
 719
 720         for (uint32_t plane = 0; plane < bo->meta.num_planes; plane++)
 721                 bo->handles[plane].u32 = drm_rc_blob.bo_handle;
 722
 723         return 0;
 724 }
 725
 726 static bool should_use_blob(struct driver *drv, uint32_t format, uint64_t use_flags)
 727 {
 728         struct virtio_gpu_priv *priv = (struct virtio_gpu_priv *)drv->priv;
 729
 730         // TODO(gurchetansingh): remove once all minigbm users are blob-safe
 731 #ifndef VIRTIO_GPU_NEXT
 732         return false;
 733 #endif
 734
 735         // Only use blob when host gbm is available
 736         if (!priv->host_gbm_enabled)
 737                 return false;
 738
 739         // Focus on non-GPU apps for now
 740         if (use_flags & (BO_USE_RENDERING | BO_USE_TEXTURE))
 741                 return false;
 742
 743         // Simple, strictly defined formats for now
 744         if (format != DRM_FORMAT_YVU420_ANDROID && format != DRM_FORMAT_R8)
 745                 return false;
 746
 747         if (use_flags &
 748             (BO_USE_SW_READ_OFTEN | BO_USE_SW_WRITE_OFTEN | BO_USE_LINEAR | BO_USE_NON_GPU_HW))
 749                 return true;
 750
 751         return false;
 752 }
 753
 754 static int virtio_gpu_bo_create(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
 755                                 uint64_t use_flags)
 756 {
 757         if (features[feat_resource_blob].enabled && features[feat_host_visible].enabled &&
 758             should_use_blob(bo->drv, format, use_flags))
 759                 return virtio_gpu_bo_create_blob(bo->drv, bo);
 760
 761         if (features[feat_3d].enabled)
 762                 return virtio_virgl_bo_create(bo, width, height, format, use_flags);
 763         else
 764                 return virtio_dumb_bo_create(bo, width, height, format, use_flags);
 765 }
 766
 767 static int virtio_gpu_bo_destroy(struct bo *bo)
 768 {
 769         if (features[feat_3d].enabled)
 770                 return drv_gem_bo_destroy(bo);
 771         else
 772                 return drv_dumb_bo_destroy(bo);
 773 }
 774
 775 static void *virtio_gpu_bo_map(struct bo *bo, struct vma *vma, size_t plane, uint32_t map_flags)
 776 {
 777         if (features[feat_3d].enabled)
 778                 return virtio_virgl_bo_map(bo, vma, plane, map_flags);
 779         else
 780                 return drv_dumb_bo_map(bo, vma, plane, map_flags);
 781 }
 782
 783 static int virtio_gpu_bo_invalidate(struct bo *bo, struct mapping *mapping)
 784 {
 785         int ret;
 786         size_t i;
 787         struct drm_virtgpu_3d_transfer_from_host xfer;
 788         struct drm_virtgpu_3d_wait waitcmd;
 789         struct virtio_transfers_params xfer_params;
 790         struct virtio_gpu_priv *priv = (struct virtio_gpu_priv *)bo->drv->priv;
 791
 792         if (!features[feat_3d].enabled)
 793                 return 0;
 794
 795         // Invalidate is only necessary if the host writes to the buffer.
 796         if ((bo->meta.use_flags & (BO_USE_RENDERING | BO_USE_CAMERA_WRITE |
 797                                    BO_USE_HW_VIDEO_ENCODER | BO_USE_HW_VIDEO_DECODER)) == 0)
 798                 return 0;
 799
 800         if (features[feat_resource_blob].enabled &&
 801             (bo->meta.tiling & VIRTGPU_BLOB_FLAG_USE_MAPPABLE))
 802                 return 0;
 803
 804         memset(&xfer, 0, sizeof(xfer));
 805         xfer.bo_handle = mapping->vma->handle;
 806
 807         if (mapping->rect.x || mapping->rect.y) {
 808                 /*
 809                  * virglrenderer uses the box parameters and assumes that offset == 0 for planar
 810                  * images
 811                  */
 812                 if (bo->meta.num_planes == 1) {
 813                         xfer.offset =
 814                             (bo->meta.strides[0] * mapping->rect.y) +
 815                             drv_bytes_per_pixel_from_format(bo->meta.format, 0) * mapping->rect.x;
 816                 }
 817         }
 818
 819         if ((bo->meta.use_flags & BO_USE_RENDERING) == 0) {
 820                 // Unfortunately, the kernel doesn't actually pass the guest layer_stride
 821                 // and guest stride to the host (compare virtio_gpu.h and virtgpu_drm.h).
 822                 // For gbm based resources, we can work around this by using the level field
 823                 // to pass the stride to virglrenderer's gbm transfer code. However, we need
 824                 // to avoid doing this for resources which don't rely on that transfer code,
 825                 // which is resources with the BO_USE_RENDERING flag set.
 826                 // TODO(b/145993887): Send also stride when the patches are landed
 827                 if (priv->host_gbm_enabled) {
 828                         xfer.level = bo->meta.strides[0];
 829                 }
 830         }
 831
 832         if (virtio_gpu_supports_combination_natively(bo->drv, bo->meta.format,
 833                                                      bo->meta.use_flags)) {
 834                 xfer_params.xfers_needed = 1;
 835                 xfer_params.xfer_boxes[0] = mapping->rect;
 836         } else {
 837                 assert(virtio_gpu_supports_combination_through_emulation(bo->drv, bo->meta.format,
 838                                                                          bo->meta.use_flags));
 839
 840                 virtio_gpu_get_emulated_transfers_params(bo, &mapping->rect, &xfer_params);
 841         }
 842
 843         for (i = 0; i < xfer_params.xfers_needed; i++) {
 844                 xfer.box.x = xfer_params.xfer_boxes[i].x;
 845                 xfer.box.y = xfer_params.xfer_boxes[i].y;
 846                 xfer.box.w = xfer_params.xfer_boxes[i].width;
 847                 xfer.box.h = xfer_params.xfer_boxes[i].height;
 848                 xfer.box.d = 1;
 849
 850                 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_VIRTGPU_TRANSFER_FROM_HOST, &xfer);
 851                 if (ret) {
 852                         drv_log("DRM_IOCTL_VIRTGPU_TRANSFER_FROM_HOST failed with %s\n",
 853                                 strerror(errno));
 854                         return -errno;
 855                 }
 856         }
 857
 858         // The transfer needs to complete before invalidate returns so that any host changes
 859         // are visible and to ensure the host doesn't overwrite subsequent guest changes.
 860         // TODO(b/136733358): Support returning fences from transfers
 861         memset(&waitcmd, 0, sizeof(waitcmd));
 862         waitcmd.handle = mapping->vma->handle;
 863         ret = drmIoctl(bo->drv->fd, DRM_IOCTL_VIRTGPU_WAIT, &waitcmd);
 864         if (ret) {
 865                 drv_log("DRM_IOCTL_VIRTGPU_WAIT failed with %s\n", strerror(errno));
 866                 return -errno;
 867         }
 868
 869         return 0;
 870 }
 871
 872 static int virtio_gpu_bo_flush(struct bo *bo, struct mapping *mapping)
 873 {
 874         int ret;
 875         size_t i;
 876         struct drm_virtgpu_3d_transfer_to_host xfer;
 877         struct drm_virtgpu_3d_wait waitcmd;
 878         struct virtio_transfers_params xfer_params;
 879         struct virtio_gpu_priv *priv = (struct virtio_gpu_priv *)bo->drv->priv;
 880
 881         if (!features[feat_3d].enabled)
 882                 return 0;
 883
 884         if (!(mapping->vma->map_flags & BO_MAP_WRITE))
 885                 return 0;
 886
 887         if (features[feat_resource_blob].enabled &&
 888             (bo->meta.tiling & VIRTGPU_BLOB_FLAG_USE_MAPPABLE))
 889                 return 0;
 890
 891         memset(&xfer, 0, sizeof(xfer));
 892         xfer.bo_handle = mapping->vma->handle;
 893
 894         if (mapping->rect.x || mapping->rect.y) {
 895                 /*
 896                  * virglrenderer uses the box parameters and assumes that offset == 0 for planar
 897                  * images
 898                  */
 899                 if (bo->meta.num_planes == 1) {
 900                         xfer.offset =
 901                             (bo->meta.strides[0] * mapping->rect.y) +
 902                             drv_bytes_per_pixel_from_format(bo->meta.format, 0) * mapping->rect.x;
 903                 }
 904         }
 905
 906         // Unfortunately, the kernel doesn't actually pass the guest layer_stride and
 907         // guest stride to the host (compare virtio_gpu.h and virtgpu_drm.h). We can use
 908         // the level to work around this.
 909         if (priv->host_gbm_enabled) {
 910                 xfer.level = bo->meta.strides[0];
 911         }
 912
 913         if (virtio_gpu_supports_combination_natively(bo->drv, bo->meta.format,
 914                                                      bo->meta.use_flags)) {
 915                 xfer_params.xfers_needed = 1;
 916                 xfer_params.xfer_boxes[0] = mapping->rect;
 917         } else {
 918                 assert(virtio_gpu_supports_combination_through_emulation(bo->drv, bo->meta.format,
 919                                                                          bo->meta.use_flags));
 920
 921                 virtio_gpu_get_emulated_transfers_params(bo, &mapping->rect, &xfer_params);
 922         }
 923
 924         for (i = 0; i < xfer_params.xfers_needed; i++) {
 925                 xfer.box.x = xfer_params.xfer_boxes[i].x;
 926                 xfer.box.y = xfer_params.xfer_boxes[i].y;
 927                 xfer.box.w = xfer_params.xfer_boxes[i].width;
 928                 xfer.box.h = xfer_params.xfer_boxes[i].height;
 929                 xfer.box.d = 1;
 930
 931                 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_VIRTGPU_TRANSFER_TO_HOST, &xfer);
 932                 if (ret) {
 933                         drv_log("DRM_IOCTL_VIRTGPU_TRANSFER_TO_HOST failed with %s\n",
 934                                 strerror(errno));
 935                         return -errno;
 936                 }
 937         }
 938
 939         // If the buffer is only accessed by the host GPU, then the flush is ordered
 940         // with subsequent commands. However, if other host hardware can access the
 941         // buffer, we need to wait for the transfer to complete for consistency.
 942         // TODO(b/136733358): Support returning fences from transfers
 943         if (bo->meta.use_flags & BO_USE_NON_GPU_HW) {
 944                 memset(&waitcmd, 0, sizeof(waitcmd));
 945                 waitcmd.handle = mapping->vma->handle;
 946
 947                 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_VIRTGPU_WAIT, &waitcmd);
 948                 if (ret) {
 949                         drv_log("DRM_IOCTL_VIRTGPU_WAIT failed with %s\n", strerror(errno));
 950                         return -errno;
 951                 }
 952         }
 953
 954         return 0;
 955 }
 956
 957 static uint32_t virtio_gpu_resolve_format(struct driver *drv, uint32_t format, uint64_t use_flags)
 958 {
 959         switch (format) {
 960         case DRM_FORMAT_FLEX_IMPLEMENTATION_DEFINED:
 961                 // TODO(b/157902551): Cuttlefish's current camera hal implementation
 962                 // requires that the flex format is RGBA. Revert this edit and use YUV
 963                 // format when Cuttlefish switches to the newer camera hal.
 964                 return DRM_FORMAT_XBGR8888;
 965         case DRM_FORMAT_FLEX_YCbCr_420_888:
 966                 /*
 967                  * All of our host drivers prefer NV12 as their flexible media format.
 968                  * If that changes, this will need to be modified.
 969                  */
 970                 if (features[feat_3d].enabled)
 971                         return DRM_FORMAT_NV12;
 972                 else
 973                         return DRM_FORMAT_YVU420_ANDROID;
 974         default:
 975                 return format;
 976         }
 977 }
 978
 979 static int virtio_gpu_resource_info(struct bo *bo, uint32_t strides[DRV_MAX_PLANES],
 980                                     uint32_t offsets[DRV_MAX_PLANES])
 981 {
 982         int ret;
 983         struct drm_virtgpu_resource_info res_info;
 984
 985         if (!features[feat_3d].enabled)
 986                 return 0;
 987
 988         memset(&res_info, 0, sizeof(res_info));
 989         res_info.bo_handle = bo->handles[0].u32;
 990         ret = drmIoctl(bo->drv->fd, DRM_IOCTL_VIRTGPU_RESOURCE_INFO, &res_info);
 991         if (ret) {
 992                 drv_log("DRM_IOCTL_VIRTGPU_RESOURCE_INFO failed with %s\n", strerror(errno));
 993                 return ret;
 994         }
 995
 996         for (uint32_t plane = 0; plane < bo->meta.num_planes; plane++) {
 997                 /*
 998                  * Currently, kernel v4.14 (Betty) doesn't have the extended resource info
 999                  * ioctl.
1000                  */
1001                 if (res_info.strides[plane]) {
1002                         strides[plane] = res_info.strides[plane];
1003                         offsets[plane] = res_info.offsets[plane];
1004                 }
1005         }
1006
1007         return 0;
1008 }
1009
1010 const struct backend backend_virtio_gpu = {
1011         .name = "virtio_gpu",
1012         .init = virtio_gpu_init,
1013         .close = virtio_gpu_close,
1014         .bo_create = virtio_gpu_bo_create,
1015         .bo_destroy = virtio_gpu_bo_destroy,
1016         .bo_import = drv_prime_bo_import,
1017         .bo_map = virtio_gpu_bo_map,
1018         .bo_unmap = drv_bo_munmap,
1019         .bo_invalidate = virtio_gpu_bo_invalidate,
1020         .bo_flush = virtio_gpu_bo_flush,
1021         .resolve_format = virtio_gpu_resolve_format,
1022         .resource_info = virtio_gpu_resource_info,
1023 };