virtio_gpu.c

   1 /*
   2  * Copyright 2017 The Chromium OS Authors. All rights reserved.
   3  * Use of this source code is governed by a BSD-style license that can be
   4  * found in the LICENSE file.
   5  */
   6
   7 #include <assert.h>
   8 #include <errno.h>
   9 #include <stdint.h>
  10 #include <stdio.h>
  11 #include <string.h>
  12 #include <sys/mman.h>
  13 #include <xf86drm.h>
  14
  15 #include "drv_priv.h"
  16 #include "helpers.h"
  17 #include "util.h"
  18 #include "virgl_hw.h"
  19 #include "virtgpu_drm.h"
  20
  21 #ifndef PAGE_SIZE
  22 #define PAGE_SIZE 0x1000
  23 #endif
  24 #define PIPE_TEXTURE_2D 2
  25
  26 #define MESA_LLVMPIPE_TILE_ORDER 6
  27 #define MESA_LLVMPIPE_TILE_SIZE (1 << MESA_LLVMPIPE_TILE_ORDER)
  28
  29 struct feature {
  30         uint64_t feature;
  31         const char *name;
  32         uint32_t enabled;
  33 };
  34
  35 enum feature_id {
  36         feat_3d,
  37         feat_capset_fix,
  38         feat_max,
  39 };
  40
  41 #define FEATURE(x)                                                                                 \
  42         (struct feature)                                                                           \
  43         {                                                                                          \
  44                 x, #x, 0                                                                           \
  45         }
  46
  47 static struct feature features[] = { FEATURE(VIRTGPU_PARAM_3D_FEATURES),
  48                                      FEATURE(VIRTGPU_PARAM_CAPSET_QUERY_FIX) };
  49
  50 static const uint32_t render_target_formats[] = { DRM_FORMAT_ABGR8888, DRM_FORMAT_ARGB8888,
  51                                                   DRM_FORMAT_RGB565, DRM_FORMAT_XBGR8888,
  52                                                   DRM_FORMAT_XRGB8888 };
  53
  54 static const uint32_t dumb_texture_source_formats[] = {
  55         DRM_FORMAT_R8,   DRM_FORMAT_R16,  DRM_FORMAT_YVU420,
  56         DRM_FORMAT_NV12, DRM_FORMAT_NV21, DRM_FORMAT_YVU420_ANDROID
  57 };
  58
  59 static const uint32_t texture_source_formats[] = { DRM_FORMAT_NV12, DRM_FORMAT_NV21,
  60                                                    DRM_FORMAT_R8,   DRM_FORMAT_R16,
  61                                                    DRM_FORMAT_RG88, DRM_FORMAT_YVU420_ANDROID };
  62
  63 struct virtio_gpu_priv {
  64         int caps_is_v2;
  65         union virgl_caps caps;
  66         int host_gbm_enabled;
  67 };
  68
  69 static uint32_t translate_format(uint32_t drm_fourcc)
  70 {
  71         switch (drm_fourcc) {
  72         case DRM_FORMAT_BGR888:
  73         case DRM_FORMAT_RGB888:
  74                 return VIRGL_FORMAT_R8G8B8_UNORM;
  75         case DRM_FORMAT_XRGB8888:
  76                 return VIRGL_FORMAT_B8G8R8X8_UNORM;
  77         case DRM_FORMAT_ARGB8888:
  78                 return VIRGL_FORMAT_B8G8R8A8_UNORM;
  79         case DRM_FORMAT_XBGR8888:
  80                 return VIRGL_FORMAT_R8G8B8X8_UNORM;
  81         case DRM_FORMAT_ABGR8888:
  82                 return VIRGL_FORMAT_R8G8B8A8_UNORM;
  83         case DRM_FORMAT_ABGR16161616F:
  84                 return VIRGL_FORMAT_R16G16B16A16_UNORM;
  85         case DRM_FORMAT_RGB565:
  86                 return VIRGL_FORMAT_B5G6R5_UNORM;
  87         case DRM_FORMAT_R8:
  88                 return VIRGL_FORMAT_R8_UNORM;
  89         case DRM_FORMAT_RG88:
  90                 return VIRGL_FORMAT_R8G8_UNORM;
  91         case DRM_FORMAT_NV12:
  92                 return VIRGL_FORMAT_NV12;
  93         case DRM_FORMAT_NV21:
  94                 return VIRGL_FORMAT_NV21;
  95         case DRM_FORMAT_YVU420:
  96         case DRM_FORMAT_YVU420_ANDROID:
  97                 return VIRGL_FORMAT_YV12;
  98         default:
  99                 return 0;
 100         }
 101 }
 102
 103 static bool virtio_gpu_bitmask_supports_format(struct virgl_supported_format_mask *supported,
 104                                                uint32_t drm_format)
 105 {
 106         uint32_t virgl_format = translate_format(drm_format);
 107         if (!virgl_format) {
 108                 return false;
 109         }
 110
 111         uint32_t bitmask_index = virgl_format / 32;
 112         uint32_t bit_index = virgl_format % 32;
 113         return supported->bitmask[bitmask_index] & (1 << bit_index);
 114 }
 115
 116 // The metadata generated here for emulated buffers is slightly different than the metadata
 117 // generated by drv_bo_from_format. In order to simplify transfers in the flush and invalidate
 118 // functions below, the emulated buffers are oversized. For example, ignoring stride alignment
 119 // requirements to demonstrate, a 6x6 YUV420 image buffer might have the following layout from
 120 // drv_bo_from_format:
 121 //
 122 // | Y | Y | Y | Y | Y | Y |
 123 // | Y | Y | Y | Y | Y | Y |
 124 // | Y | Y | Y | Y | Y | Y |
 125 // | Y | Y | Y | Y | Y | Y |
 126 // | Y | Y | Y | Y | Y | Y |
 127 // | Y | Y | Y | Y | Y | Y |
 128 // | U | U | U | U | U | U |
 129 // | U | U | U | V | V | V |
 130 // | V | V | V | V | V | V |
 131 //
 132 // where each plane immediately follows the previous plane in memory. This layout makes it
 133 // difficult to compute the transfers needed for example when the middle 2x2 region of the
 134 // image is locked and needs to be flushed/invalidated.
 135 //
 136 // Emulated multi-plane buffers instead have a layout of:
 137 //
 138 // | Y | Y | Y | Y | Y | Y |
 139 // | Y | Y | Y | Y | Y | Y |
 140 // | Y | Y | Y | Y | Y | Y |
 141 // | Y | Y | Y | Y | Y | Y |
 142 // | Y | Y | Y | Y | Y | Y |
 143 // | Y | Y | Y | Y | Y | Y |
 144 // | U | U | U |   |   |   |
 145 // | U | U | U |   |   |   |
 146 // | U | U | U |   |   |   |
 147 // | V | V | V |   |   |   |
 148 // | V | V | V |   |   |   |
 149 // | V | V | V |   |   |   |
 150 //
 151 // where each plane is placed as a sub-image (albeit with a very large stride) in order to
 152 // simplify transfers into 3 sub-image transfers for the above example.
 153 //
 154 // Additional note: the V-plane is not placed to the right of the U-plane due to some
 155 // observed failures in media framework code which assumes the V-plane is not
 156 // "row-interlaced" with the U-plane.
 157 static void virtio_gpu_get_emulated_metadata(const struct bo *bo, struct bo_metadata *metadata)
 158 {
 159         uint32_t y_plane_height;
 160         uint32_t c_plane_height;
 161         uint32_t original_width = bo->meta.width;
 162         uint32_t original_height = bo->meta.height;
 163
 164         metadata->format = DRM_FORMAT_R8;
 165         switch (bo->meta.format) {
 166         case DRM_FORMAT_NV12:
 167         case DRM_FORMAT_NV21:
 168                 // Bi-planar
 169                 metadata->num_planes = 2;
 170
 171                 y_plane_height = original_height;
 172                 c_plane_height = DIV_ROUND_UP(original_height, 2);
 173
 174                 metadata->width = original_width;
 175                 metadata->height = y_plane_height + c_plane_height;
 176
 177                 // Y-plane (full resolution)
 178                 metadata->strides[0] = metadata->width;
 179                 metadata->offsets[0] = 0;
 180                 metadata->sizes[0] = metadata->width * y_plane_height;
 181
 182                 // CbCr-plane  (half resolution, interleaved, placed below Y-plane)
 183                 metadata->strides[1] = metadata->width;
 184                 metadata->offsets[1] = metadata->offsets[0] + metadata->sizes[0];
 185                 metadata->sizes[1] = metadata->width * c_plane_height;
 186
 187                 metadata->total_size = metadata->width * metadata->height;
 188                 break;
 189         case DRM_FORMAT_YVU420:
 190         case DRM_FORMAT_YVU420_ANDROID:
 191                 // Tri-planar
 192                 metadata->num_planes = 3;
 193
 194                 y_plane_height = original_height;
 195                 c_plane_height = DIV_ROUND_UP(original_height, 2);
 196
 197                 metadata->width = ALIGN(original_width, 32);
 198                 metadata->height = y_plane_height + (2 * c_plane_height);
 199
 200                 // Y-plane (full resolution)
 201                 metadata->strides[0] = metadata->width;
 202                 metadata->offsets[0] = 0;
 203                 metadata->sizes[0] = metadata->width * original_height;
 204
 205                 // Cb-plane (half resolution, placed below Y-plane)
 206                 metadata->strides[1] = metadata->width;
 207                 metadata->offsets[1] = metadata->offsets[0] + metadata->sizes[0];
 208                 metadata->sizes[1] = metadata->width * c_plane_height;
 209
 210                 // Cr-plane (half resolution, placed below Cb-plane)
 211                 metadata->strides[2] = metadata->width;
 212                 metadata->offsets[2] = metadata->offsets[1] + metadata->sizes[1];
 213                 metadata->sizes[2] = metadata->width * c_plane_height;
 214
 215                 metadata->total_size = metadata->width * metadata->height;
 216                 break;
 217         default:
 218                 break;
 219         }
 220 }
 221
 222 struct virtio_transfers_params {
 223         size_t xfers_needed;
 224         struct rectangle xfer_boxes[DRV_MAX_PLANES];
 225 };
 226
 227 static void virtio_gpu_get_emulated_transfers_params(const struct bo *bo,
 228                                                      const struct rectangle *transfer_box,
 229                                                      struct virtio_transfers_params *xfer_params)
 230 {
 231         uint32_t y_plane_height;
 232         uint32_t c_plane_height;
 233         struct bo_metadata emulated_metadata;
 234
 235         if (transfer_box->x == 0 && transfer_box->y == 0 && transfer_box->width == bo->meta.width &&
 236             transfer_box->height == bo->meta.height) {
 237                 virtio_gpu_get_emulated_metadata(bo, &emulated_metadata);
 238
 239                 xfer_params->xfers_needed = 1;
 240                 xfer_params->xfer_boxes[0].x = 0;
 241                 xfer_params->xfer_boxes[0].y = 0;
 242                 xfer_params->xfer_boxes[0].width = emulated_metadata.width;
 243                 xfer_params->xfer_boxes[0].height = emulated_metadata.height;
 244
 245                 return;
 246         }
 247
 248         switch (bo->meta.format) {
 249         case DRM_FORMAT_NV12:
 250         case DRM_FORMAT_NV21:
 251                 // Bi-planar
 252                 xfer_params->xfers_needed = 2;
 253
 254                 y_plane_height = bo->meta.height;
 255                 c_plane_height = DIV_ROUND_UP(bo->meta.height, 2);
 256
 257                 // Y-plane (full resolution)
 258                 xfer_params->xfer_boxes[0].x = transfer_box->x;
 259                 xfer_params->xfer_boxes[0].y = transfer_box->y;
 260                 xfer_params->xfer_boxes[0].width = transfer_box->width;
 261                 xfer_params->xfer_boxes[0].height = transfer_box->height;
 262
 263                 // CbCr-plane (half resolution, interleaved, placed below Y-plane)
 264                 xfer_params->xfer_boxes[1].x = transfer_box->x;
 265                 xfer_params->xfer_boxes[1].y = transfer_box->y + y_plane_height;
 266                 xfer_params->xfer_boxes[1].width = transfer_box->width;
 267                 xfer_params->xfer_boxes[1].height = DIV_ROUND_UP(transfer_box->height, 2);
 268
 269                 break;
 270         case DRM_FORMAT_YVU420:
 271         case DRM_FORMAT_YVU420_ANDROID:
 272                 // Tri-planar
 273                 xfer_params->xfers_needed = 3;
 274
 275                 y_plane_height = bo->meta.height;
 276                 c_plane_height = DIV_ROUND_UP(bo->meta.height, 2);
 277
 278                 // Y-plane (full resolution)
 279                 xfer_params->xfer_boxes[0].x = transfer_box->x;
 280                 xfer_params->xfer_boxes[0].y = transfer_box->y;
 281                 xfer_params->xfer_boxes[0].width = transfer_box->width;
 282                 xfer_params->xfer_boxes[0].height = transfer_box->height;
 283
 284                 // Cb-plane (half resolution, placed below Y-plane)
 285                 xfer_params->xfer_boxes[1].x = transfer_box->x;
 286                 xfer_params->xfer_boxes[1].y = transfer_box->y + y_plane_height;
 287                 xfer_params->xfer_boxes[1].width = DIV_ROUND_UP(transfer_box->width, 2);
 288                 xfer_params->xfer_boxes[1].height = DIV_ROUND_UP(transfer_box->height, 2);
 289
 290                 // Cr-plane (half resolution, placed below Cb-plane)
 291                 xfer_params->xfer_boxes[2].x = transfer_box->x;
 292                 xfer_params->xfer_boxes[2].y = transfer_box->y + y_plane_height + c_plane_height;
 293                 xfer_params->xfer_boxes[2].width = DIV_ROUND_UP(transfer_box->width, 2);
 294                 xfer_params->xfer_boxes[2].height = DIV_ROUND_UP(transfer_box->height, 2);
 295
 296                 break;
 297         }
 298 }
 299
 300 static bool virtio_gpu_supports_combination_natively(struct driver *drv, uint32_t drm_format,
 301                                                      uint64_t use_flags)
 302 {
 303         struct virtio_gpu_priv *priv = (struct virtio_gpu_priv *)drv->priv;
 304
 305         if (priv->caps.max_version == 0) {
 306                 return true;
 307         }
 308
 309         if ((use_flags & BO_USE_RENDERING) &&
 310             !virtio_gpu_bitmask_supports_format(&priv->caps.v1.render, drm_format)) {
 311                 return false;
 312         }
 313
 314         if ((use_flags & BO_USE_TEXTURE) &&
 315             !virtio_gpu_bitmask_supports_format(&priv->caps.v1.sampler, drm_format)) {
 316                 return false;
 317         }
 318
 319         if ((use_flags & BO_USE_SCANOUT) && priv->caps_is_v2 &&
 320             !virtio_gpu_bitmask_supports_format(&priv->caps.v2.scanout, drm_format)) {
 321                 return false;
 322         }
 323
 324         return true;
 325 }
 326
 327 // For virtio backends that do not support formats natively (e.g. multi-planar formats are not
 328 // supported in virglrenderer when gbm is unavailable on the host machine), whether or not the
 329 // format and usage combination can be handled as a blob (byte buffer).
 330 static bool virtio_gpu_supports_combination_through_emulation(struct driver *drv,
 331                                                               uint32_t drm_format,
 332                                                               uint64_t use_flags)
 333 {
 334         struct virtio_gpu_priv *priv = (struct virtio_gpu_priv *)drv->priv;
 335
 336         // Only enable emulation on non-gbm virtio backends.
 337         if (priv->host_gbm_enabled) {
 338                 return false;
 339         }
 340
 341         if (use_flags & (BO_USE_RENDERING | BO_USE_SCANOUT)) {
 342                 return false;
 343         }
 344
 345         if (!virtio_gpu_supports_combination_natively(drv, DRM_FORMAT_R8, use_flags)) {
 346                 return false;
 347         }
 348
 349         return drm_format == DRM_FORMAT_NV12 || drm_format == DRM_FORMAT_NV21 ||
 350                drm_format == DRM_FORMAT_YVU420 || drm_format == DRM_FORMAT_YVU420_ANDROID;
 351 }
 352
 353 // Adds the given buffer combination to the list of supported buffer combinations if the
 354 // combination is supported by the virtio backend.
 355 static void virtio_gpu_add_combination(struct driver *drv, uint32_t drm_format,
 356                                        struct format_metadata *metadata, uint64_t use_flags)
 357 {
 358         struct virtio_gpu_priv *priv = (struct virtio_gpu_priv *)drv->priv;
 359
 360         if (features[feat_3d].enabled && priv->caps.max_version >= 1) {
 361                 if ((use_flags & BO_USE_SCANOUT) && priv->caps_is_v2 &&
 362                     !virtio_gpu_supports_combination_natively(drv, drm_format, use_flags)) {
 363                         drv_log("Scanout format: %d\n", drm_format);
 364                         use_flags &= ~BO_USE_SCANOUT;
 365                 }
 366
 367                 if (!virtio_gpu_supports_combination_natively(drv, drm_format, use_flags) &&
 368                     !virtio_gpu_supports_combination_through_emulation(drv, drm_format,
 369                                                                        use_flags)) {
 370                         drv_log("Skipping unsupported combination format:%d\n", drm_format);
 371                         return;
 372                 }
 373         }
 374
 375         drv_add_combination(drv, drm_format, metadata, use_flags);
 376 }
 377
 378 // Adds each given buffer combination to the list of supported buffer combinations if the
 379 // combination supported by the virtio backend.
 380 static void virtio_gpu_add_combinations(struct driver *drv, const uint32_t *drm_formats,
 381                                         uint32_t num_formats, struct format_metadata *metadata,
 382                                         uint64_t use_flags)
 383 {
 384         uint32_t i;
 385
 386         for (i = 0; i < num_formats; i++) {
 387                 virtio_gpu_add_combination(drv, drm_formats[i], metadata, use_flags);
 388         }
 389 }
 390
 391 static int virtio_dumb_bo_create(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
 392                                  uint64_t use_flags)
 393 {
 394         if (bo->meta.format != DRM_FORMAT_R8) {
 395                 width = ALIGN(width, MESA_LLVMPIPE_TILE_SIZE);
 396                 height = ALIGN(height, MESA_LLVMPIPE_TILE_SIZE);
 397         }
 398
 399         return drv_dumb_bo_create_ex(bo, width, height, format, use_flags, BO_QUIRK_DUMB32BPP);
 400 }
 401
 402 static inline void handle_flag(uint64_t *flag, uint64_t check_flag, uint32_t *bind,
 403                                uint32_t virgl_bind)
 404 {
 405         if ((*flag) & check_flag) {
 406                 (*flag) &= ~check_flag;
 407                 (*bind) |= virgl_bind;
 408         }
 409 }
 410
 411 static uint32_t use_flags_to_bind(uint64_t use_flags)
 412 {
 413         /* In crosvm, VIRGL_BIND_SHARED means minigbm will allocate, not virglrenderer. */
 414         uint32_t bind = VIRGL_BIND_SHARED;
 415
 416         handle_flag(&use_flags, BO_USE_TEXTURE, &bind, VIRGL_BIND_SAMPLER_VIEW);
 417         handle_flag(&use_flags, BO_USE_RENDERING, &bind, VIRGL_BIND_RENDER_TARGET);
 418         handle_flag(&use_flags, BO_USE_SCANOUT, &bind, VIRGL_BIND_SCANOUT);
 419         handle_flag(&use_flags, BO_USE_CURSOR, &bind, VIRGL_BIND_CURSOR);
 420         handle_flag(&use_flags, BO_USE_LINEAR, &bind, VIRGL_BIND_LINEAR);
 421
 422         if (use_flags & BO_USE_PROTECTED) {
 423                 handle_flag(&use_flags, BO_USE_PROTECTED, &bind, VIRGL_BIND_MINIGBM_PROTECTED);
 424         } else {
 425                 // Make sure we don't set both flags, since that could be mistaken for
 426                 // protected. Give OFTEN priority over RARELY.
 427                 if (use_flags & BO_USE_SW_READ_OFTEN) {
 428                         handle_flag(&use_flags, BO_USE_SW_READ_OFTEN, &bind,
 429                                     VIRGL_BIND_MINIGBM_SW_READ_OFTEN);
 430                 } else {
 431                         handle_flag(&use_flags, BO_USE_SW_READ_RARELY, &bind,
 432                                     VIRGL_BIND_MINIGBM_SW_READ_RARELY);
 433                 }
 434                 if (use_flags & BO_USE_SW_WRITE_OFTEN) {
 435                         handle_flag(&use_flags, BO_USE_SW_WRITE_OFTEN, &bind,
 436                                     VIRGL_BIND_MINIGBM_SW_WRITE_OFTEN);
 437                 } else {
 438                         handle_flag(&use_flags, BO_USE_SW_WRITE_RARELY, &bind,
 439                                     VIRGL_BIND_MINIGBM_SW_WRITE_RARELY);
 440                 }
 441         }
 442
 443         handle_flag(&use_flags, BO_USE_CAMERA_WRITE, &bind, VIRGL_BIND_MINIGBM_CAMERA_WRITE);
 444         handle_flag(&use_flags, BO_USE_CAMERA_READ, &bind, VIRGL_BIND_MINIGBM_CAMERA_READ);
 445         handle_flag(&use_flags, BO_USE_HW_VIDEO_DECODER, &bind,
 446                     VIRGL_BIND_MINIGBM_HW_VIDEO_DECODER);
 447         handle_flag(&use_flags, BO_USE_HW_VIDEO_ENCODER, &bind,
 448                     VIRGL_BIND_MINIGBM_HW_VIDEO_ENCODER);
 449
 450         if (use_flags) {
 451                 drv_log("Unhandled bo use flag: %llx\n", (unsigned long long)use_flags);
 452         }
 453
 454         return bind;
 455 }
 456
 457 static int virtio_virgl_bo_create(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
 458                                   uint64_t use_flags)
 459 {
 460         int ret;
 461         size_t i;
 462         uint32_t stride;
 463         struct drm_virtgpu_resource_create res_create;
 464         struct bo_metadata emulated_metadata;
 465
 466         if (virtio_gpu_supports_combination_natively(bo->drv, format, use_flags)) {
 467                 stride = drv_stride_from_format(format, width, 0);
 468                 drv_bo_from_format(bo, stride, height, format);
 469         } else {
 470                 assert(
 471                     virtio_gpu_supports_combination_through_emulation(bo->drv, format, use_flags));
 472
 473                 virtio_gpu_get_emulated_metadata(bo, &emulated_metadata);
 474
 475                 format = emulated_metadata.format;
 476                 width = emulated_metadata.width;
 477                 height = emulated_metadata.height;
 478                 for (i = 0; i < emulated_metadata.num_planes; i++) {
 479                         bo->meta.strides[i] = emulated_metadata.strides[i];
 480                         bo->meta.offsets[i] = emulated_metadata.offsets[i];
 481                         bo->meta.sizes[i] = emulated_metadata.sizes[i];
 482                 }
 483                 bo->meta.total_size = emulated_metadata.total_size;
 484         }
 485
 486         /*
 487          * Setting the target is intended to ensure this resource gets bound as a 2D
 488          * texture in the host renderer's GL state. All of these resource properties are
 489          * sent unchanged by the kernel to the host, which in turn sends them unchanged to
 490          * virglrenderer. When virglrenderer makes a resource, it will convert the target
 491          * enum to the equivalent one in GL and then bind the resource to that target.
 492          */
 493         memset(&res_create, 0, sizeof(res_create));
 494
 495         res_create.target = PIPE_TEXTURE_2D;
 496         res_create.format = translate_format(format);
 497         res_create.bind = use_flags_to_bind(use_flags);
 498         res_create.width = width;
 499         res_create.height = height;
 500
 501         /* For virgl 3D */
 502         res_create.depth = 1;
 503         res_create.array_size = 1;
 504         res_create.last_level = 0;
 505         res_create.nr_samples = 0;
 506
 507         res_create.size = ALIGN(bo->meta.total_size, PAGE_SIZE); // PAGE_SIZE = 0x1000
 508         ret = drmIoctl(bo->drv->fd, DRM_IOCTL_VIRTGPU_RESOURCE_CREATE, &res_create);
 509         if (ret) {
 510                 drv_log("DRM_IOCTL_VIRTGPU_RESOURCE_CREATE failed with %s\n", strerror(errno));
 511                 return ret;
 512         }
 513
 514         for (uint32_t plane = 0; plane < bo->meta.num_planes; plane++)
 515                 bo->handles[plane].u32 = res_create.bo_handle;
 516
 517         return 0;
 518 }
 519
 520 static void *virtio_virgl_bo_map(struct bo *bo, struct vma *vma, size_t plane, uint32_t map_flags)
 521 {
 522         int ret;
 523         struct drm_virtgpu_map gem_map;
 524
 525         memset(&gem_map, 0, sizeof(gem_map));
 526         gem_map.handle = bo->handles[0].u32;
 527
 528         ret = drmIoctl(bo->drv->fd, DRM_IOCTL_VIRTGPU_MAP, &gem_map);
 529         if (ret) {
 530                 drv_log("DRM_IOCTL_VIRTGPU_MAP failed with %s\n", strerror(errno));
 531                 return MAP_FAILED;
 532         }
 533
 534         vma->length = bo->meta.total_size;
 535         return mmap(0, bo->meta.total_size, drv_get_prot(map_flags), MAP_SHARED, bo->drv->fd,
 536                     gem_map.offset);
 537 }
 538
 539 static int virtio_gpu_get_caps(struct driver *drv, union virgl_caps *caps, int *caps_is_v2)
 540 {
 541         int ret;
 542         struct drm_virtgpu_get_caps cap_args;
 543
 544         *caps_is_v2 = 0;
 545         memset(&cap_args, 0, sizeof(cap_args));
 546         cap_args.addr = (unsigned long long)caps;
 547         if (features[feat_capset_fix].enabled) {
 548                 *caps_is_v2 = 1;
 549                 cap_args.cap_set_id = 2;
 550                 cap_args.size = sizeof(union virgl_caps);
 551         } else {
 552                 cap_args.cap_set_id = 1;
 553                 cap_args.size = sizeof(struct virgl_caps_v1);
 554         }
 555
 556         ret = drmIoctl(drv->fd, DRM_IOCTL_VIRTGPU_GET_CAPS, &cap_args);
 557         if (ret) {
 558                 drv_log("DRM_IOCTL_VIRTGPU_GET_CAPS failed with %s\n", strerror(errno));
 559                 *caps_is_v2 = 0;
 560
 561                 // Fallback to v1
 562                 cap_args.cap_set_id = 1;
 563                 cap_args.size = sizeof(struct virgl_caps_v1);
 564
 565                 ret = drmIoctl(drv->fd, DRM_IOCTL_VIRTGPU_GET_CAPS, &cap_args);
 566                 if (ret) {
 567                         drv_log("DRM_IOCTL_VIRTGPU_GET_CAPS failed with %s\n", strerror(errno));
 568                 }
 569         }
 570
 571         return ret;
 572 }
 573
 574 static void virtio_gpu_init_features_and_caps(struct driver *drv)
 575 {
 576         struct virtio_gpu_priv *priv = (struct virtio_gpu_priv *)drv->priv;
 577
 578         for (uint32_t i = 0; i < ARRAY_SIZE(features); i++) {
 579                 struct drm_virtgpu_getparam params = { 0 };
 580
 581                 params.param = features[i].feature;
 582                 params.value = (uint64_t)(uintptr_t)&features[i].enabled;
 583                 int ret = drmIoctl(drv->fd, DRM_IOCTL_VIRTGPU_GETPARAM, &params);
 584                 if (ret)
 585                         drv_log("DRM_IOCTL_VIRTGPU_GET_PARAM failed with %s\n", strerror(errno));
 586         }
 587
 588         if (features[feat_3d].enabled) {
 589                 virtio_gpu_get_caps(drv, &priv->caps, &priv->caps_is_v2);
 590         }
 591
 592         // Multi-planar formats are currently only supported in virglrenderer through gbm.
 593         priv->host_gbm_enabled =
 594             virtio_gpu_supports_combination_natively(drv, DRM_FORMAT_NV12, BO_USE_TEXTURE);
 595 }
 596
 597 static int virtio_gpu_init(struct driver *drv)
 598 {
 599         struct virtio_gpu_priv *priv;
 600
 601         priv = calloc(1, sizeof(*priv));
 602         drv->priv = priv;
 603
 604         virtio_gpu_init_features_and_caps(drv);
 605
 606         if (features[feat_3d].enabled) {
 607                 /* This doesn't mean host can scanout everything, it just means host
 608                  * hypervisor can show it. */
 609                 virtio_gpu_add_combinations(drv, render_target_formats,
 610                                             ARRAY_SIZE(render_target_formats), &LINEAR_METADATA,
 611                                             BO_USE_RENDER_MASK | BO_USE_SCANOUT);
 612                 virtio_gpu_add_combinations(drv, texture_source_formats,
 613                                             ARRAY_SIZE(texture_source_formats), &LINEAR_METADATA,
 614                                             BO_USE_TEXTURE_MASK);
 615         } else {
 616                 /* Virtio primary plane only allows this format. */
 617                 virtio_gpu_add_combination(drv, DRM_FORMAT_XRGB8888, &LINEAR_METADATA,
 618                                            BO_USE_RENDER_MASK | BO_USE_SCANOUT);
 619                 /* Virtio cursor plane only allows this format and Chrome cannot live without
 620                  * ARGB888 renderable format. */
 621                 virtio_gpu_add_combination(drv, DRM_FORMAT_ARGB8888, &LINEAR_METADATA,
 622                                            BO_USE_RENDER_MASK | BO_USE_CURSOR);
 623                 /* Android needs more, but they cannot be bound as scanouts anymore after
 624                  * "drm/virtio: fix DRM_FORMAT_* handling" */
 625                 virtio_gpu_add_combinations(drv, render_target_formats,
 626                                             ARRAY_SIZE(render_target_formats), &LINEAR_METADATA,
 627                                             BO_USE_RENDER_MASK);
 628                 virtio_gpu_add_combinations(drv, dumb_texture_source_formats,
 629                                             ARRAY_SIZE(dumb_texture_source_formats),
 630                                             &LINEAR_METADATA, BO_USE_TEXTURE_MASK);
 631                 virtio_gpu_add_combination(drv, DRM_FORMAT_NV12, &LINEAR_METADATA,
 632                                            BO_USE_SW_MASK | BO_USE_LINEAR);
 633                 virtio_gpu_add_combination(drv, DRM_FORMAT_NV21, &LINEAR_METADATA,
 634                                            BO_USE_SW_MASK | BO_USE_LINEAR);
 635         }
 636
 637         /* Android CTS tests require this. */
 638         virtio_gpu_add_combination(drv, DRM_FORMAT_RGB888, &LINEAR_METADATA, BO_USE_SW_MASK);
 639         virtio_gpu_add_combination(drv, DRM_FORMAT_BGR888, &LINEAR_METADATA, BO_USE_SW_MASK);
 640         virtio_gpu_add_combination(drv, DRM_FORMAT_ABGR16161616F, &LINEAR_METADATA,
 641                                    BO_USE_SW_MASK | BO_USE_TEXTURE_MASK);
 642
 643         drv_modify_combination(drv, DRM_FORMAT_ABGR8888, &LINEAR_METADATA,
 644                                BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE | BO_USE_HW_VIDEO_DECODER |
 645                                    BO_USE_HW_VIDEO_ENCODER);
 646         drv_modify_combination(drv, DRM_FORMAT_XBGR8888, &LINEAR_METADATA,
 647                                BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE | BO_USE_HW_VIDEO_DECODER |
 648                                    BO_USE_HW_VIDEO_ENCODER);
 649         drv_modify_combination(drv, DRM_FORMAT_NV12, &LINEAR_METADATA,
 650                                BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE | BO_USE_HW_VIDEO_DECODER |
 651                                    BO_USE_HW_VIDEO_ENCODER);
 652         drv_modify_combination(drv, DRM_FORMAT_NV21, &LINEAR_METADATA,
 653                                BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE | BO_USE_HW_VIDEO_DECODER |
 654                                    BO_USE_HW_VIDEO_ENCODER);
 655         drv_modify_combination(drv, DRM_FORMAT_R16, &LINEAR_METADATA,
 656                                BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE | BO_USE_HW_VIDEO_DECODER);
 657         drv_modify_combination(drv, DRM_FORMAT_R8, &LINEAR_METADATA,
 658                                BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE | BO_USE_HW_VIDEO_DECODER |
 659                                    BO_USE_HW_VIDEO_ENCODER);
 660         drv_modify_combination(drv, DRM_FORMAT_YVU420, &LINEAR_METADATA,
 661                                BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE | BO_USE_HW_VIDEO_DECODER |
 662                                    BO_USE_HW_VIDEO_ENCODER);
 663         drv_modify_combination(drv, DRM_FORMAT_YVU420_ANDROID, &LINEAR_METADATA,
 664                                BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE | BO_USE_HW_VIDEO_DECODER |
 665                                    BO_USE_HW_VIDEO_ENCODER);
 666
 667         return drv_modify_linear_combinations(drv);
 668 }
 669
 670 static void virtio_gpu_close(struct driver *drv)
 671 {
 672         free(drv->priv);
 673         drv->priv = NULL;
 674 }
 675
 676 static int virtio_gpu_bo_create(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
 677                                 uint64_t use_flags)
 678 {
 679         if (features[feat_3d].enabled)
 680                 return virtio_virgl_bo_create(bo, width, height, format, use_flags);
 681         else
 682                 return virtio_dumb_bo_create(bo, width, height, format, use_flags);
 683 }
 684
 685 static int virtio_gpu_bo_destroy(struct bo *bo)
 686 {
 687         if (features[feat_3d].enabled)
 688                 return drv_gem_bo_destroy(bo);
 689         else
 690                 return drv_dumb_bo_destroy(bo);
 691 }
 692
 693 static void *virtio_gpu_bo_map(struct bo *bo, struct vma *vma, size_t plane, uint32_t map_flags)
 694 {
 695         if (features[feat_3d].enabled)
 696                 return virtio_virgl_bo_map(bo, vma, plane, map_flags);
 697         else
 698                 return drv_dumb_bo_map(bo, vma, plane, map_flags);
 699 }
 700
 701 static int virtio_gpu_bo_invalidate(struct bo *bo, struct mapping *mapping)
 702 {
 703         int ret;
 704         size_t i;
 705         struct drm_virtgpu_3d_transfer_from_host xfer;
 706         struct drm_virtgpu_3d_wait waitcmd;
 707         struct virtio_transfers_params xfer_params;
 708         struct virtio_gpu_priv *priv = (struct virtio_gpu_priv *)bo->drv->priv;
 709
 710         if (!features[feat_3d].enabled)
 711                 return 0;
 712
 713         // Invalidate is only necessary if the host writes to the buffer.
 714         if ((bo->meta.use_flags & (BO_USE_RENDERING | BO_USE_CAMERA_WRITE |
 715                                    BO_USE_HW_VIDEO_ENCODER | BO_USE_HW_VIDEO_DECODER)) == 0)
 716                 return 0;
 717
 718         memset(&xfer, 0, sizeof(xfer));
 719         xfer.bo_handle = mapping->vma->handle;
 720
 721         if (mapping->rect.x || mapping->rect.y) {
 722                 /*
 723                  * virglrenderer uses the box parameters and assumes that offset == 0 for planar
 724                  * images
 725                  */
 726                 if (bo->meta.num_planes == 1) {
 727                         xfer.offset =
 728                             (bo->meta.strides[0] * mapping->rect.y) +
 729                             drv_bytes_per_pixel_from_format(bo->meta.format, 0) * mapping->rect.x;
 730                 }
 731         }
 732
 733         if ((bo->meta.use_flags & BO_USE_RENDERING) == 0) {
 734                 // Unfortunately, the kernel doesn't actually pass the guest layer_stride
 735                 // and guest stride to the host (compare virtio_gpu.h and virtgpu_drm.h).
 736                 // For gbm based resources, we can work around this by using the level field
 737                 // to pass the stride to virglrenderer's gbm transfer code. However, we need
 738                 // to avoid doing this for resources which don't rely on that transfer code,
 739                 // which is resources with the BO_USE_RENDERING flag set.
 740                 // TODO(b/145993887): Send also stride when the patches are landed
 741                 if (priv->host_gbm_enabled) {
 742                         xfer.level = bo->meta.strides[0];
 743                 }
 744         }
 745
 746         if (virtio_gpu_supports_combination_natively(bo->drv, bo->meta.format,
 747                                                      bo->meta.use_flags)) {
 748                 xfer_params.xfers_needed = 1;
 749                 xfer_params.xfer_boxes[0] = mapping->rect;
 750         } else {
 751                 assert(virtio_gpu_supports_combination_through_emulation(bo->drv, bo->meta.format,
 752                                                                          bo->meta.use_flags));
 753
 754                 virtio_gpu_get_emulated_transfers_params(bo, &mapping->rect, &xfer_params);
 755         }
 756
 757         for (i = 0; i < xfer_params.xfers_needed; i++) {
 758                 xfer.box.x = xfer_params.xfer_boxes[i].x;
 759                 xfer.box.y = xfer_params.xfer_boxes[i].y;
 760                 xfer.box.w = xfer_params.xfer_boxes[i].width;
 761                 xfer.box.h = xfer_params.xfer_boxes[i].height;
 762                 xfer.box.d = 1;
 763
 764                 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_VIRTGPU_TRANSFER_FROM_HOST, &xfer);
 765                 if (ret) {
 766                         drv_log("DRM_IOCTL_VIRTGPU_TRANSFER_FROM_HOST failed with %s\n",
 767                                 strerror(errno));
 768                         return -errno;
 769                 }
 770         }
 771
 772         // The transfer needs to complete before invalidate returns so that any host changes
 773         // are visible and to ensure the host doesn't overwrite subsequent guest changes.
 774         // TODO(b/136733358): Support returning fences from transfers
 775         memset(&waitcmd, 0, sizeof(waitcmd));
 776         waitcmd.handle = mapping->vma->handle;
 777         ret = drmIoctl(bo->drv->fd, DRM_IOCTL_VIRTGPU_WAIT, &waitcmd);
 778         if (ret) {
 779                 drv_log("DRM_IOCTL_VIRTGPU_WAIT failed with %s\n", strerror(errno));
 780                 return -errno;
 781         }
 782
 783         return 0;
 784 }
 785
 786 static int virtio_gpu_bo_flush(struct bo *bo, struct mapping *mapping)
 787 {
 788         int ret;
 789         size_t i;
 790         struct drm_virtgpu_3d_transfer_to_host xfer;
 791         struct drm_virtgpu_3d_wait waitcmd;
 792         struct virtio_transfers_params xfer_params;
 793         struct virtio_gpu_priv *priv = (struct virtio_gpu_priv *)bo->drv->priv;
 794
 795         if (!features[feat_3d].enabled)
 796                 return 0;
 797
 798         if (!(mapping->vma->map_flags & BO_MAP_WRITE))
 799                 return 0;
 800
 801         memset(&xfer, 0, sizeof(xfer));
 802         xfer.bo_handle = mapping->vma->handle;
 803
 804         if (mapping->rect.x || mapping->rect.y) {
 805                 /*
 806                  * virglrenderer uses the box parameters and assumes that offset == 0 for planar
 807                  * images
 808                  */
 809                 if (bo->meta.num_planes == 1) {
 810                         xfer.offset =
 811                             (bo->meta.strides[0] * mapping->rect.y) +
 812                             drv_bytes_per_pixel_from_format(bo->meta.format, 0) * mapping->rect.x;
 813                 }
 814         }
 815
 816         // Unfortunately, the kernel doesn't actually pass the guest layer_stride and
 817         // guest stride to the host (compare virtio_gpu.h and virtgpu_drm.h). We can use
 818         // the level to work around this.
 819         if (priv->host_gbm_enabled) {
 820                 xfer.level = bo->meta.strides[0];
 821         }
 822
 823         if (virtio_gpu_supports_combination_natively(bo->drv, bo->meta.format,
 824                                                      bo->meta.use_flags)) {
 825                 xfer_params.xfers_needed = 1;
 826                 xfer_params.xfer_boxes[0] = mapping->rect;
 827         } else {
 828                 assert(virtio_gpu_supports_combination_through_emulation(bo->drv, bo->meta.format,
 829                                                                          bo->meta.use_flags));
 830
 831                 virtio_gpu_get_emulated_transfers_params(bo, &mapping->rect, &xfer_params);
 832         }
 833
 834         for (i = 0; i < xfer_params.xfers_needed; i++) {
 835                 xfer.box.x = xfer_params.xfer_boxes[i].x;
 836                 xfer.box.y = xfer_params.xfer_boxes[i].y;
 837                 xfer.box.w = xfer_params.xfer_boxes[i].width;
 838                 xfer.box.h = xfer_params.xfer_boxes[i].height;
 839                 xfer.box.d = 1;
 840
 841                 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_VIRTGPU_TRANSFER_TO_HOST, &xfer);
 842                 if (ret) {
 843                         drv_log("DRM_IOCTL_VIRTGPU_TRANSFER_TO_HOST failed with %s\n",
 844                                 strerror(errno));
 845                         return -errno;
 846                 }
 847         }
 848
 849         // If the buffer is only accessed by the host GPU, then the flush is ordered
 850         // with subsequent commands. However, if other host hardware can access the
 851         // buffer, we need to wait for the transfer to complete for consistency.
 852         // TODO(b/136733358): Support returning fences from transfers
 853         if (bo->meta.use_flags & BO_USE_NON_GPU_HW) {
 854                 memset(&waitcmd, 0, sizeof(waitcmd));
 855                 waitcmd.handle = mapping->vma->handle;
 856
 857                 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_VIRTGPU_WAIT, &waitcmd);
 858                 if (ret) {
 859                         drv_log("DRM_IOCTL_VIRTGPU_WAIT failed with %s\n", strerror(errno));
 860                         return -errno;
 861                 }
 862         }
 863
 864         return 0;
 865 }
 866
 867 static uint32_t virtio_gpu_resolve_format(struct driver *drv, uint32_t format, uint64_t use_flags)
 868 {
 869         switch (format) {
 870         case DRM_FORMAT_FLEX_IMPLEMENTATION_DEFINED:
 871                 // TODO(b/157902551): Cuttlefish's current camera hal implementation
 872                 // requires that the flex format is RGBA. Revert this edit and use YUV
 873                 // format when Cuttlefish switches to the newer camera hal.
 874                 return DRM_FORMAT_XBGR8888;
 875         case DRM_FORMAT_FLEX_YCbCr_420_888:
 876                 /*
 877                  * All of our host drivers prefer NV12 as their flexible media format.
 878                  * If that changes, this will need to be modified.
 879                  */
 880                 if (features[feat_3d].enabled)
 881                         return DRM_FORMAT_NV12;
 882                 else
 883                         return DRM_FORMAT_YVU420_ANDROID;
 884         default:
 885                 return format;
 886         }
 887 }
 888
 889 static int virtio_gpu_resource_info(struct bo *bo, uint32_t strides[DRV_MAX_PLANES],
 890                                     uint32_t offsets[DRV_MAX_PLANES])
 891 {
 892         int ret;
 893         struct drm_virtgpu_resource_info res_info;
 894
 895         if (!features[feat_3d].enabled)
 896                 return 0;
 897
 898         memset(&res_info, 0, sizeof(res_info));
 899         res_info.bo_handle = bo->handles[0].u32;
 900         ret = drmIoctl(bo->drv->fd, DRM_IOCTL_VIRTGPU_RESOURCE_INFO, &res_info);
 901         if (ret) {
 902                 drv_log("DRM_IOCTL_VIRTGPU_RESOURCE_INFO failed with %s\n", strerror(errno));
 903                 return ret;
 904         }
 905
 906         for (uint32_t plane = 0; plane < bo->meta.num_planes; plane++) {
 907                 /*
 908                  * Currently, kernel v4.14 (Betty) doesn't have the extended resource info
 909                  * ioctl.
 910                  */
 911                 if (res_info.strides[plane]) {
 912                         strides[plane] = res_info.strides[plane];
 913                         offsets[plane] = res_info.offsets[plane];
 914                 }
 915         }
 916
 917         return 0;
 918 }
 919
 920 const struct backend backend_virtio_gpu = {
 921         .name = "virtio_gpu",
 922         .init = virtio_gpu_init,
 923         .close = virtio_gpu_close,
 924         .bo_create = virtio_gpu_bo_create,
 925         .bo_destroy = virtio_gpu_bo_destroy,
 926         .bo_import = drv_prime_bo_import,
 927         .bo_map = virtio_gpu_bo_map,
 928         .bo_unmap = drv_bo_munmap,
 929         .bo_invalidate = virtio_gpu_bo_invalidate,
 930         .bo_flush = virtio_gpu_bo_flush,
 931         .resolve_format = virtio_gpu_resolve_format,
 932         .resource_info = virtio_gpu_resource_info,
 933 };