hal/odm.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  *
  19  ******************************************************************************/
  20
  21 //============================================================
  22 // include files
  23 //============================================================
  24
  25 #include "odm_precomp.h"
  26
  27
  28
  29 const u2Byte dB_Invert_Table[8][12] = {
  30         {       1,              1,              1,              2,              2,              2,              2,              3,              3,              3,              4,              4},
  31         {       4,              5,              6,              6,              7,              8,              9,              10,             11,             13,             14,             16},
  32         {       18,             20,             22,             25,             28,             32,             35,             40,             45,             50,             56,             63},
  33         {       71,             79,             89,             100,    112,    126,    141,    158,    178,    200,    224,    251},
  34         {       282,    316,    355,    398,    447,    501,    562,    631,    708,    794,    891,    1000},
  35         {       1122,   1259,   1413,   1585,   1778,   1995,   2239,   2512,   2818,   3162,   3548,   3981},
  36         {       4467,   5012,   5623,   6310,   7079,   7943,   8913,   10000,  11220,  12589,  14125,  15849},
  37         {       17783,  19953,  22387,  25119,  28184,  31623,  35481,  39811,  44668,  50119,  56234,  65535}};
  38
  39 // 20100515 Joseph: Add global variable to keep temporary scan list for antenna switching test.
  40 //u8                    tmpNumBssDesc;
  41 //RT_WLAN_BSS   tmpbssDesc[MAX_BSS_DESC];
  42
  43
  44 //avoid to warn in FreeBSD ==> To DO modify
  45 u4Byte EDCAParam[HT_IOT_PEER_MAX][3] =
  46 {          // UL                        DL
  47         {0x5ea42b, 0x5ea42b, 0x5ea42b}, //0:unknown AP
  48         {0xa44f, 0x5ea44f, 0x5e431c}, // 1:realtek AP
  49         {0x5ea42b, 0x5ea42b, 0x5ea42b}, // 2:unknown AP => realtek_92SE
  50         {0x5ea32b, 0x5ea42b, 0x5e4322}, // 3:broadcom AP
  51         {0x5ea422, 0x00a44f, 0x00a44f}, // 4:ralink AP
  52         {0x5ea322, 0x00a630, 0x00a44f}, // 5:atheros AP
  53         //{0x5ea42b, 0x5ea42b, 0x5ea42b},// 6:cisco AP
  54         {0x5e4322, 0x5e4322, 0x5e4322},// 6:cisco AP
  55         //{0x3ea430, 0x00a630, 0x3ea44f}, // 7:cisco AP
  56         {0x5ea44f, 0x00a44f, 0x5ea42b}, // 8:marvell AP
  57         //{0x5ea44f, 0x5ea44f, 0x5ea44f}, // 9realtek AP
  58         {0x5ea42b, 0x5ea42b, 0x5ea42b}, // 10:unknown AP=> 92U AP
  59         {0x5ea42b, 0xa630, 0x5e431c}, // 11:airgocap AP
  60 //      {0x5e4322, 0x00a44f, 0x5ea44f}, // 12:unknown AP
  61 };
  62 //============================================================
  63 // EDCA Paramter for AP/ADSL   by Mingzhi 2011-11-22
  64 //============================================================
  65
  66 //============================================================
  67 // Global var
  68 //============================================================
  69 u4Byte OFDMSwingTable[OFDM_TABLE_SIZE_92D] = {
  70         0x7f8001fe, // 0, +6.0dB
  71         0x788001e2, // 1, +5.5dB
  72         0x71c001c7, // 2, +5.0dB
  73         0x6b8001ae, // 3, +4.5dB
  74         0x65400195, // 4, +4.0dB
  75         0x5fc0017f, // 5, +3.5dB
  76         0x5a400169, // 6, +3.0dB
  77         0x55400155, // 7, +2.5dB
  78         0x50800142, // 8, +2.0dB
  79         0x4c000130, // 9, +1.5dB
  80         0x47c0011f, // 10, +1.0dB
  81         0x43c0010f, // 11, +0.5dB
  82         0x40000100, // 12, +0dB
  83         0x3c8000f2, // 13, -0.5dB
  84         0x390000e4, // 14, -1.0dB
  85         0x35c000d7, // 15, -1.5dB
  86         0x32c000cb, // 16, -2.0dB
  87         0x300000c0, // 17, -2.5dB
  88         0x2d4000b5, // 18, -3.0dB
  89         0x2ac000ab, // 19, -3.5dB
  90         0x288000a2, // 20, -4.0dB
  91         0x26000098, // 21, -4.5dB
  92         0x24000090, // 22, -5.0dB
  93         0x22000088, // 23, -5.5dB
  94         0x20000080, // 24, -6.0dB
  95         0x1e400079, // 25, -6.5dB
  96         0x1c800072, // 26, -7.0dB
  97         0x1b00006c, // 27. -7.5dB
  98         0x19800066, // 28, -8.0dB
  99         0x18000060, // 29, -8.5dB
 100         0x16c0005b, // 30, -9.0dB
 101         0x15800056, // 31, -9.5dB
 102         0x14400051, // 32, -10.0dB
 103         0x1300004c, // 33, -10.5dB
 104         0x12000048, // 34, -11.0dB
 105         0x11000044, // 35, -11.5dB
 106         0x10000040, // 36, -12.0dB
 107         0x0f00003c,// 37, -12.5dB
 108         0x0e400039,// 38, -13.0dB
 109         0x0d800036,// 39, -13.5dB
 110         0x0cc00033,// 40, -14.0dB
 111         0x0c000030,// 41, -14.5dB
 112         0x0b40002d,// 42, -15.0dB
 113 };
 114
 115
 116 u8 CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8] = {
 117         {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04},       // 0, +0dB
 118         {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04},       // 1, -0.5dB
 119         {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03},       // 2, -1.0dB
 120         {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03},       // 3, -1.5dB
 121         {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03},       // 4, -2.0dB
 122         {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03},       // 5, -2.5dB
 123         {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03},       // 6, -3.0dB
 124         {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03},       // 7, -3.5dB
 125         {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02},       // 8, -4.0dB
 126         {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02},       // 9, -4.5dB
 127         {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02},       // 10, -5.0dB
 128         {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02},       // 11, -5.5dB
 129         {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02},       // 12, -6.0dB
 130         {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02},       // 13, -6.5dB
 131         {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02},       // 14, -7.0dB
 132         {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02},       // 15, -7.5dB
 133         {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01},       // 16, -8.0dB
 134         {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02},       // 17, -8.5dB
 135         {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01},       // 18, -9.0dB
 136         {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},       // 19, -9.5dB
 137         {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},       // 20, -10.0dB
 138         {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01},       // 21, -10.5dB
 139         {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01},       // 22, -11.0dB
 140         {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01},       // 23, -11.5dB
 141         {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01},       // 24, -12.0dB
 142         {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01},       // 25, -12.5dB
 143         {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01},       // 26, -13.0dB
 144         {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01},       // 27, -13.5dB
 145         {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},       // 28, -14.0dB
 146         {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},       // 29, -14.5dB
 147         {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01},       // 30, -15.0dB
 148         {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},       // 31, -15.5dB
 149         {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}        // 32, -16.0dB
 150 };
 151
 152
 153 u8 CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8]= {
 154         {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00},       // 0, +0dB
 155         {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00},       // 1, -0.5dB
 156         {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00},       // 2, -1.0dB
 157         {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00},       // 3, -1.5dB
 158         {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00},       // 4, -2.0dB
 159         {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00},       // 5, -2.5dB
 160         {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00},       // 6, -3.0dB
 161         {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00},       // 7, -3.5dB
 162         {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00},       // 8, -4.0dB
 163         {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00},       // 9, -4.5dB
 164         {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00},       // 10, -5.0dB
 165         {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},       // 11, -5.5dB
 166         {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00},       // 12, -6.0dB
 167         {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00},       // 13, -6.5dB
 168         {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00},       // 14, -7.0dB
 169         {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00},       // 15, -7.5dB
 170         {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00},       // 16, -8.0dB
 171         {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00},       // 17, -8.5dB
 172         {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00},       // 18, -9.0dB
 173         {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},       // 19, -9.5dB
 174         {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},       // 20, -10.0dB
 175         {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00},       // 21, -10.5dB
 176         {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00},       // 22, -11.0dB
 177         {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},       // 23, -11.5dB
 178         {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},       // 24, -12.0dB
 179         {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00},       // 25, -12.5dB
 180         {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},       // 26, -13.0dB
 181         {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},       // 27, -13.5dB
 182         {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},       // 28, -14.0dB
 183         {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},       // 29, -14.5dB
 184         {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},       // 30, -15.0dB
 185         {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},       // 31, -15.5dB
 186         {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}        // 32, -16.0dB
 187 };
 188
 189
 190 #ifdef AP_BUILD_WORKAROUND
 191
 192 unsigned int TxPwrTrk_OFDM_SwingTbl[TxPwrTrk_OFDM_SwingTbl_Len] = {
 193         /*  +6.0dB */ 0x7f8001fe,
 194         /*  +5.5dB */ 0x788001e2,
 195         /*  +5.0dB */ 0x71c001c7,
 196         /*  +4.5dB */ 0x6b8001ae,
 197         /*  +4.0dB */ 0x65400195,
 198         /*  +3.5dB */ 0x5fc0017f,
 199         /*  +3.0dB */ 0x5a400169,
 200         /*  +2.5dB */ 0x55400155,
 201         /*  +2.0dB */ 0x50800142,
 202         /*  +1.5dB */ 0x4c000130,
 203         /*  +1.0dB */ 0x47c0011f,
 204         /*  +0.5dB */ 0x43c0010f,
 205         /*   0.0dB */ 0x40000100,
 206         /*  -0.5dB */ 0x3c8000f2,
 207         /*  -1.0dB */ 0x390000e4,
 208         /*  -1.5dB */ 0x35c000d7,
 209         /*  -2.0dB */ 0x32c000cb,
 210         /*  -2.5dB */ 0x300000c0,
 211         /*  -3.0dB */ 0x2d4000b5,
 212         /*  -3.5dB */ 0x2ac000ab,
 213         /*  -4.0dB */ 0x288000a2,
 214         /*  -4.5dB */ 0x26000098,
 215         /*  -5.0dB */ 0x24000090,
 216         /*  -5.5dB */ 0x22000088,
 217         /*  -6.0dB */ 0x20000080,
 218         /*  -6.5dB */ 0x1a00006c,
 219         /*  -7.0dB */ 0x1c800072,
 220         /*  -7.5dB */ 0x18000060,
 221         /*  -8.0dB */ 0x19800066,
 222         /*  -8.5dB */ 0x15800056,
 223         /*  -9.0dB */ 0x26c0005b,
 224         /*  -9.5dB */ 0x14400051,
 225         /* -10.0dB */ 0x24400051,
 226         /* -10.5dB */ 0x1300004c,
 227         /* -11.0dB */ 0x12000048,
 228         /* -11.5dB */ 0x11000044,
 229         /* -12.0dB */ 0x10000040
 230 };
 231 #endif
 232
 233 //============================================================
 234 // Local Function predefine.
 235 //============================================================
 236
 237 //START------------COMMON INFO RELATED---------------//
 238 void
 239 odm_CommonInfoSelfInit(
 240                 PDM_ODM_T               pDM_Odm
 241         );
 242
 243 void
 244 odm_CommonInfoSelfUpdate(
 245                 PDM_ODM_T               pDM_Odm
 246         );
 247
 248 void
 249 odm_CmnInfoInit_Debug(
 250                 PDM_ODM_T               pDM_Odm
 251         );
 252
 253 void
 254 odm_CmnInfoHook_Debug(
 255                 PDM_ODM_T               pDM_Odm
 256         );
 257
 258 void
 259 odm_CmnInfoUpdate_Debug(
 260                 PDM_ODM_T               pDM_Odm
 261         );
 262 /*
 263 void
 264 odm_FindMinimumRSSI(
 265                 PDM_ODM_T               pDM_Odm
 266         );
 267
 268 void
 269 odm_IsLinked(
 270                 PDM_ODM_T               pDM_Odm
 271         );
 272 */
 273 //END------------COMMON INFO RELATED---------------//
 274
 275 //START---------------DIG---------------------------//
 276 void
 277 odm_FalseAlarmCounterStatistics(
 278                 PDM_ODM_T               pDM_Odm
 279         );
 280
 281 void
 282 odm_DIGInit(
 283                 PDM_ODM_T               pDM_Odm
 284         );
 285
 286 void
 287 odm_DIG(
 288                 PDM_ODM_T               pDM_Odm
 289         );
 290
 291 void
 292 odm_CCKPacketDetectionThresh(
 293                 PDM_ODM_T               pDM_Odm
 294         );
 295 //END---------------DIG---------------------------//
 296
 297 //START-------BB POWER SAVE-----------------------//
 298 void
 299 odm_DynamicBBPowerSavingInit(
 300                 PDM_ODM_T               pDM_Odm
 301         );
 302
 303 void
 304 odm_DynamicBBPowerSaving(
 305                 PDM_ODM_T               pDM_Odm
 306         );
 307
 308 void
 309 odm_1R_CCA(
 310                 PDM_ODM_T               pDM_Odm
 311         );
 312 //END---------BB POWER SAVE-----------------------//
 313
 314
 315 void
 316 odm_RefreshRateAdaptiveMaskMP(
 317                 PDM_ODM_T               pDM_Odm
 318         );
 319
 320 void
 321 odm_RefreshRateAdaptiveMaskCE(
 322                 PDM_ODM_T               pDM_Odm
 323         );
 324
 325 void
 326 odm_RefreshRateAdaptiveMaskAPADSL(
 327                 PDM_ODM_T               pDM_Odm
 328         );
 329
 330 void
 331 odm_DynamicTxPowerInit(
 332                 PDM_ODM_T               pDM_Odm
 333         );
 334
 335 void
 336 odm_DynamicTxPowerRestorePowerIndex(
 337         PDM_ODM_T       pDM_Odm
 338         );
 339
 340 void
 341 odm_DynamicTxPowerNIC(
 342         PDM_ODM_T       pDM_Odm
 343         );
 344
 345 void
 346 odm_DynamicTxPowerSavePowerIndex(
 347                 PDM_ODM_T               pDM_Odm
 348         );
 349
 350 void
 351 odm_DynamicTxPowerWritePowerIndex(
 352         PDM_ODM_T       pDM_Odm,
 353         u8              Value);
 354
 355 void
 356 odm_DynamicTxPower_92C(
 357         PDM_ODM_T       pDM_Odm
 358         );
 359
 360 void
 361 odm_DynamicTxPower_92D(
 362         PDM_ODM_T       pDM_Odm
 363         );
 364
 365 void
 366 odm_RSSIMonitorInit(
 367         PDM_ODM_T       pDM_Odm
 368         );
 369
 370 void
 371 odm_RSSIMonitorCheckMP(
 372         PDM_ODM_T       pDM_Odm
 373         );
 374
 375 void
 376 odm_RSSIMonitorCheckCE(
 377                 PDM_ODM_T               pDM_Odm
 378         );
 379 void
 380 odm_RSSIMonitorCheckAP(
 381                 PDM_ODM_T               pDM_Odm
 382         );
 383
 384
 385
 386 void
 387 odm_RSSIMonitorCheck(
 388                 PDM_ODM_T               pDM_Odm
 389         );
 390 void
 391 odm_DynamicTxPower(
 392                 PDM_ODM_T               pDM_Odm
 393         );
 394
 395 void
 396 odm_DynamicTxPowerAP(
 397                 PDM_ODM_T               pDM_Odm
 398         );
 399
 400
 401 void
 402 odm_SwAntDivInit(
 403                 PDM_ODM_T               pDM_Odm
 404         );
 405
 406 void
 407 odm_SwAntDivInit_NIC(
 408                 PDM_ODM_T               pDM_Odm
 409         );
 410
 411 void
 412 odm_SwAntDivChkAntSwitch(
 413                 PDM_ODM_T               pDM_Odm,
 414                 u8                      Step
 415         );
 416
 417 void
 418 odm_SwAntDivChkAntSwitchNIC(
 419                 PDM_ODM_T               pDM_Odm,
 420                 u8              Step
 421         );
 422
 423
 424 void odm_SwAntDivChkAntSwitchCallback(void *FunctionContext);
 425
 426 void
 427 odm_GlobalAdapterCheck(
 428                 void
 429         );
 430
 431 void
 432 odm_RefreshRateAdaptiveMask(
 433                 PDM_ODM_T               pDM_Odm
 434         );
 435
 436 void
 437 ODM_TXPowerTrackingCheck(
 438                 PDM_ODM_T               pDM_Odm
 439         );
 440
 441 void
 442 odm_TXPowerTrackingCheckAP(
 443                 PDM_ODM_T               pDM_Odm
 444         );
 445
 446
 447
 448
 449
 450
 451
 452 void
 453 odm_RateAdaptiveMaskInit(
 454         PDM_ODM_T       pDM_Odm
 455         );
 456
 457 void
 458 odm_TXPowerTrackingThermalMeterInit(
 459         PDM_ODM_T       pDM_Odm
 460         );
 461
 462
 463 void
 464 odm_TXPowerTrackingInit(
 465         PDM_ODM_T       pDM_Odm
 466         );
 467
 468 void
 469 odm_TXPowerTrackingCheckMP(
 470         PDM_ODM_T       pDM_Odm
 471         );
 472
 473
 474 void
 475 odm_TXPowerTrackingCheckCE(
 476         PDM_ODM_T       pDM_Odm
 477         );
 478
 479 void
 480 odm_EdcaTurboCheck(
 481                 PDM_ODM_T               pDM_Odm
 482         );
 483 void
 484 ODM_EdcaTurboInit(
 485         PDM_ODM_T               pDM_Odm
 486 );
 487
 488 void
 489 odm_EdcaTurboCheckCE(
 490                 PDM_ODM_T               pDM_Odm
 491         );
 492
 493 #define         RxDefaultAnt1           0x65a9
 494 #define RxDefaultAnt2           0x569a
 495
 496 void
 497 odm_InitHybridAntDiv(
 498  PDM_ODM_T      pDM_Odm
 499         );
 500
 501 bool
 502 odm_StaDefAntSel(
 503  PDM_ODM_T      pDM_Odm,
 504  u4Byte         OFDM_Ant1_Cnt,
 505  u4Byte         OFDM_Ant2_Cnt,
 506  u4Byte         CCK_Ant1_Cnt,
 507  u4Byte         CCK_Ant2_Cnt,
 508  u8             *pDefAnt
 509         );
 510
 511 void
 512 odm_SetRxIdleAnt(
 513         PDM_ODM_T       pDM_Odm,
 514         u8      Ant,
 515    bool   bDualPath
 516 );
 517
 518
 519
 520 void
 521 odm_HwAntDiv(
 522         PDM_ODM_T       pDM_Odm
 523 );
 524
 525
 526 //============================================================
 527 //3 Export Interface
 528 //============================================================
 529
 530 //
 531 // 2011/09/21 MH Add to describe different team necessary resource allocate??
 532 //
 533 void
 534 ODM_DMInit(
 535                 PDM_ODM_T               pDM_Odm
 536         )
 537 {
 538
 539 #if (FPGA_TWO_MAC_VERIFICATION == 1)
 540         odm_RateAdaptiveMaskInit(pDM_Odm);
 541         return;
 542 #endif
 543
 544         //2012.05.03 Luke: For all IC series
 545         odm_CommonInfoSelfInit(pDM_Odm);
 546         odm_CmnInfoInit_Debug(pDM_Odm);
 547         odm_DIGInit(pDM_Odm);
 548         odm_RateAdaptiveMaskInit(pDM_Odm);
 549
 550         if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
 551         {
 552
 553         }
 554         else if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
 555         {
 556                 #if (RTL8188E_SUPPORT == 1)
 557                 odm_PrimaryCCA_Init(pDM_Odm);    // Gary
 558                 #endif
 559                 odm_DynamicBBPowerSavingInit(pDM_Odm);
 560                 odm_DynamicTxPowerInit(pDM_Odm);
 561                 odm_TXPowerTrackingInit(pDM_Odm);
 562                 ODM_EdcaTurboInit(pDM_Odm);
 563                 #if (RTL8188E_SUPPORT == 1)
 564                 ODM_RAInfo_Init_all(pDM_Odm);
 565                 #endif
 566                 if(( pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV )  ||
 567                         ( pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV )    ||
 568                         ( pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV ))
 569                 {
 570                         odm_InitHybridAntDiv(pDM_Odm);
 571                 }
 572                 else if( pDM_Odm->AntDivType == CGCS_RX_SW_ANTDIV)
 573                 {
 574                         odm_SwAntDivInit(pDM_Odm);
 575                 }
 576         }
 577 }
 578
 579 //
 580 // 2011/09/20 MH This is the entry pointer for all team to execute HW out source DM.
 581 // You can not add any dummy function here, be care, you can only use DM structure
 582 // to perform any new ODM_DM.
 583 //
 584 void
 585 ODM_DMWatchdog(
 586                 PDM_ODM_T               pDM_Odm
 587         )
 588 {
 589         //2012.05.03 Luke: For all IC series
 590         odm_GlobalAdapterCheck();
 591         odm_CmnInfoHook_Debug(pDM_Odm);
 592         odm_CmnInfoUpdate_Debug(pDM_Odm);
 593         odm_CommonInfoSelfUpdate(pDM_Odm);
 594         odm_FalseAlarmCounterStatistics(pDM_Odm);
 595         odm_RSSIMonitorCheck(pDM_Odm);
 596
 597         //For CE Platform(SPRD or Tablet)
 598         //8723A or 8189ES platform
 599         //NeilChen--2012--08--24--
 600         //Fix Leave LPS issue
 601         if((pDM_Odm->Adapter->pwrctrlpriv.pwr_mode != PS_MODE_ACTIVE) &&// in LPS mode
 602                 (
 603                         (pDM_Odm->SupportICType & (ODM_RTL8723A ) )||
 604                         (pDM_Odm->SupportICType & (ODM_RTL8188E) &&((pDM_Odm->SupportInterface  == ODM_ITRF_SDIO)) )
 605
 606                 //&&((pDM_Odm->SupportInterface  == ODM_ITRF_SDIO))
 607                 )
 608         )
 609         {
 610                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("----Step1: odm_DIG is in LPS mode\n"));
 611                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("---Step2: 8723AS is in LPS mode\n"));
 612                         odm_DIGbyRSSI_LPS(pDM_Odm);
 613         }
 614         else
 615         {
 616                 odm_DIG(pDM_Odm);
 617         }
 618
 619
 620         odm_CCKPacketDetectionThresh(pDM_Odm);
 621
 622         if(*(pDM_Odm->pbPowerSaving)==TRUE)
 623                 return;
 624
 625         odm_RefreshRateAdaptiveMask(pDM_Odm);
 626
 627         #if (RTL8192D_SUPPORT == 1)
 628         ODM_DynamicEarlyMode(pDM_Odm);
 629         #endif
 630         odm_DynamicBBPowerSaving(pDM_Odm);
 631         #if (RTL8188E_SUPPORT == 1)
 632         odm_DynamicPrimaryCCA(pDM_Odm);
 633         #endif
 634         if(( pDM_Odm->AntDivType ==  CG_TRX_HW_ANTDIV ) ||
 635                 ( pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV )    ||
 636                 ( pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV ))
 637         {
 638                 odm_HwAntDiv(pDM_Odm);
 639         }
 640         else if( pDM_Odm->AntDivType == CGCS_RX_SW_ANTDIV)
 641         {
 642                 odm_SwAntDivChkAntSwitch(pDM_Odm, SWAW_STEP_PEAK);
 643         }
 644
 645         if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
 646         {
 647
 648         }
 649         else if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
 650         {
 651                 ODM_TXPowerTrackingCheck(pDM_Odm);
 652               odm_EdcaTurboCheck(pDM_Odm);
 653                 odm_DynamicTxPower(pDM_Odm);
 654         }
 655
 656         odm_dtc(pDM_Odm);
 657 }
 658
 659
 660 //
 661 // Init /.. Fixed HW value. Only init time.
 662 //
 663 void
 664 ODM_CmnInfoInit(
 665                 PDM_ODM_T               pDM_Odm,
 666                 ODM_CMNINFO_E   CmnInfo,
 667                 u4Byte                  Value
 668         )
 669 {
 670         //ODM_RT_TRACE(pDM_Odm,);
 671
 672         //
 673         // This section is used for init value
 674         //
 675         switch  (CmnInfo)
 676         {
 677                 //
 678                 // Fixed ODM value.
 679                 //
 680                 case    ODM_CMNINFO_ABILITY:
 681                         pDM_Odm->SupportAbility = (u4Byte)Value;
 682                         break;
 683                 case    ODM_CMNINFO_PLATFORM:
 684                         pDM_Odm->SupportPlatform = (u8)Value;
 685                         break;
 686
 687                 case    ODM_CMNINFO_INTERFACE:
 688                         pDM_Odm->SupportInterface = (u8)Value;
 689                         break;
 690
 691                 case    ODM_CMNINFO_MP_TEST_CHIP:
 692                         pDM_Odm->bIsMPChip= (u8)Value;
 693                         break;
 694
 695                 case    ODM_CMNINFO_IC_TYPE:
 696                         pDM_Odm->SupportICType = Value;
 697                         break;
 698
 699                 case    ODM_CMNINFO_CUT_VER:
 700                         pDM_Odm->CutVersion = (u8)Value;
 701                         break;
 702
 703                 case    ODM_CMNINFO_FAB_VER:
 704                         pDM_Odm->FabVersion = (u8)Value;
 705                         break;
 706
 707                 case    ODM_CMNINFO_RF_TYPE:
 708                         pDM_Odm->RFType = (u8)Value;
 709                         break;
 710
 711                 case    ODM_CMNINFO_RF_ANTENNA_TYPE:
 712                         pDM_Odm->AntDivType= (u8)Value;
 713                         break;
 714
 715                 case    ODM_CMNINFO_BOARD_TYPE:
 716                         pDM_Odm->BoardType = (u8)Value;
 717                         break;
 718
 719                 case    ODM_CMNINFO_EXT_LNA:
 720                         pDM_Odm->ExtLNA = (u8)Value;
 721                         break;
 722
 723                 case    ODM_CMNINFO_EXT_PA:
 724                         pDM_Odm->ExtPA = (u8)Value;
 725                         break;
 726
 727                 case    ODM_CMNINFO_EXT_TRSW:
 728                         pDM_Odm->ExtTRSW = (u8)Value;
 729                         break;
 730                 case    ODM_CMNINFO_PATCH_ID:
 731                         pDM_Odm->PatchID = (u8)Value;
 732                         break;
 733                 case    ODM_CMNINFO_BINHCT_TEST:
 734                         pDM_Odm->bInHctTest = (bool)Value;
 735                         break;
 736                 case    ODM_CMNINFO_BWIFI_TEST:
 737                         pDM_Odm->bWIFITest = (bool)Value;
 738                         break;
 739
 740                 case    ODM_CMNINFO_SMART_CONCURRENT:
 741                         pDM_Odm->bDualMacSmartConcurrent = (bool )Value;
 742                         break;
 743
 744                 //To remove the compiler warning, must add an empty default statement to handle the other values.
 745                 default:
 746                         //do nothing
 747                         break;
 748
 749         }
 750
 751         //
 752         // Tx power tracking BB swing table.
 753         // The base index = 12. +((12-n)/2)dB 13~?? = decrease tx pwr by -((n-12)/2)dB
 754         //
 755         pDM_Odm->BbSwingIdxOfdm                 = 12; // Set defalut value as index 12.
 756         pDM_Odm->BbSwingIdxOfdmCurrent  = 12;
 757         pDM_Odm->BbSwingFlagOfdm                = FALSE;
 758
 759 }
 760
 761
 762 void
 763 ODM_CmnInfoHook(
 764                 PDM_ODM_T               pDM_Odm,
 765                 ODM_CMNINFO_E   CmnInfo,
 766                 void *                  pValue
 767         )
 768 {
 769         //
 770         // Hook call by reference pointer.
 771         //
 772         switch  (CmnInfo)
 773         {
 774                 //
 775                 // Dynamic call by reference pointer.
 776                 //
 777                 case    ODM_CMNINFO_MAC_PHY_MODE:
 778                         pDM_Odm->pMacPhyMode = (u8 *)pValue;
 779                         break;
 780
 781                 case    ODM_CMNINFO_TX_UNI:
 782                         pDM_Odm->pNumTxBytesUnicast = (u8Byte *)pValue;
 783                         break;
 784
 785                 case    ODM_CMNINFO_RX_UNI:
 786                         pDM_Odm->pNumRxBytesUnicast = (u8Byte *)pValue;
 787                         break;
 788
 789                 case    ODM_CMNINFO_WM_MODE:
 790                         pDM_Odm->pWirelessMode = (u8 *)pValue;
 791                         break;
 792
 793                 case    ODM_CMNINFO_BAND:
 794                         pDM_Odm->pBandType = (u8 *)pValue;
 795                         break;
 796
 797                 case    ODM_CMNINFO_SEC_CHNL_OFFSET:
 798                         pDM_Odm->pSecChOffset = (u8 *)pValue;
 799                         break;
 800
 801                 case    ODM_CMNINFO_SEC_MODE:
 802                         pDM_Odm->pSecurity = (u8 *)pValue;
 803                         break;
 804
 805                 case    ODM_CMNINFO_BW:
 806                         pDM_Odm->pBandWidth = (u8 *)pValue;
 807                         break;
 808
 809                 case    ODM_CMNINFO_CHNL:
 810                         pDM_Odm->pChannel = (u8 *)pValue;
 811                         break;
 812
 813                 case    ODM_CMNINFO_DMSP_GET_VALUE:
 814                         pDM_Odm->pbGetValueFromOtherMac = (bool *)pValue;
 815                         break;
 816
 817                 case    ODM_CMNINFO_BUDDY_ADAPTOR:
 818                         pDM_Odm->pBuddyAdapter = (PADAPTER *)pValue;
 819                         break;
 820
 821                 case    ODM_CMNINFO_DMSP_IS_MASTER:
 822                         pDM_Odm->pbMasterOfDMSP = (bool *)pValue;
 823                         break;
 824
 825                 case    ODM_CMNINFO_SCAN:
 826                         pDM_Odm->pbScanInProcess = (bool *)pValue;
 827                         break;
 828
 829                 case    ODM_CMNINFO_POWER_SAVING:
 830                         pDM_Odm->pbPowerSaving = (bool *)pValue;
 831                         break;
 832
 833                 case    ODM_CMNINFO_ONE_PATH_CCA:
 834                         pDM_Odm->pOnePathCCA = (u8 *)pValue;
 835                         break;
 836
 837                 case    ODM_CMNINFO_DRV_STOP:
 838                         pDM_Odm->pbDriverStopped =  (bool *)pValue;
 839                         break;
 840
 841                 case    ODM_CMNINFO_PNP_IN:
 842                         pDM_Odm->pbDriverIsGoingToPnpSetPowerSleep =  (bool *)pValue;
 843                         break;
 844
 845                 case    ODM_CMNINFO_INIT_ON:
 846                         pDM_Odm->pinit_adpt_in_progress =  (bool *)pValue;
 847                         break;
 848
 849                 case    ODM_CMNINFO_ANT_TEST:
 850                         pDM_Odm->pAntennaTest =  (u8 *)pValue;
 851                         break;
 852
 853                 case    ODM_CMNINFO_NET_CLOSED:
 854                         pDM_Odm->pbNet_closed = (bool *)pValue;
 855                         break;
 856
 857                 //case  ODM_CMNINFO_BT_COEXIST:
 858                 //      pDM_Odm->BTCoexist = (bool *)pValue;
 859
 860                 //case  ODM_CMNINFO_STA_STATUS:
 861                         //pDM_Odm->pODM_StaInfo[] = (PSTA_INFO_T)pValue;
 862                         //break;
 863
 864                 //case  ODM_CMNINFO_PHY_STATUS:
 865                 //      pDM_Odm->pPhyInfo = (ODM_PHY_INFO *)pValue;
 866                 //      break;
 867
 868                 //case  ODM_CMNINFO_MAC_STATUS:
 869                 //      pDM_Odm->pMacInfo = (ODM_MAC_INFO *)pValue;
 870                 //      break;
 871                 //To remove the compiler warning, must add an empty default statement to handle the other values.
 872                 default:
 873                         //do nothing
 874                         break;
 875
 876         }
 877
 878 }
 879
 880
 881 void
 882 ODM_CmnInfoPtrArrayHook(
 883                 PDM_ODM_T               pDM_Odm,
 884                 ODM_CMNINFO_E   CmnInfo,
 885                 u2Byte                  Index,
 886                 void *                  pValue
 887         )
 888 {
 889         //
 890         // Hook call by reference pointer.
 891         //
 892         switch  (CmnInfo)
 893         {
 894                 //
 895                 // Dynamic call by reference pointer.
 896                 //
 897                 case    ODM_CMNINFO_STA_STATUS:
 898                         pDM_Odm->pODM_StaInfo[Index] = (PSTA_INFO_T)pValue;
 899                         break;
 900                 //To remove the compiler warning, must add an empty default statement to handle the other values.
 901                 default:
 902                         //do nothing
 903                         break;
 904         }
 905
 906 }
 907
 908
 909 //
 910 // Update Band/CHannel/.. The values are dynamic but non-per-packet.
 911 //
 912 void
 913 ODM_CmnInfoUpdate(
 914                 PDM_ODM_T               pDM_Odm,
 915                 u4Byte                  CmnInfo,
 916                 u8Byte                  Value
 917         )
 918 {
 919         //
 920         // This init variable may be changed in run time.
 921         //
 922         switch  (CmnInfo)
 923         {
 924                 case    ODM_CMNINFO_ABILITY:
 925                         pDM_Odm->SupportAbility = (u4Byte)Value;
 926                         break;
 927
 928                 case    ODM_CMNINFO_RF_TYPE:
 929                         pDM_Odm->RFType = (u8)Value;
 930                         break;
 931
 932                 case    ODM_CMNINFO_WIFI_DIRECT:
 933                         pDM_Odm->bWIFI_Direct = (bool)Value;
 934                         break;
 935
 936                 case    ODM_CMNINFO_WIFI_DISPLAY:
 937                         pDM_Odm->bWIFI_Display = (bool)Value;
 938                         break;
 939
 940                 case    ODM_CMNINFO_LINK:
 941                         pDM_Odm->bLinked = (bool)Value;
 942                         break;
 943
 944                 case    ODM_CMNINFO_RSSI_MIN:
 945                         pDM_Odm->RSSI_Min= (u8)Value;
 946                         break;
 947
 948                 case    ODM_CMNINFO_DBG_COMP:
 949                         pDM_Odm->DebugComponents = Value;
 950                         break;
 951
 952                 case    ODM_CMNINFO_DBG_LEVEL:
 953                         pDM_Odm->DebugLevel = (u4Byte)Value;
 954                         break;
 955                 case    ODM_CMNINFO_RA_THRESHOLD_HIGH:
 956                         pDM_Odm->RateAdaptive.HighRSSIThresh = (u8)Value;
 957                         break;
 958
 959                 case    ODM_CMNINFO_RA_THRESHOLD_LOW:
 960                         pDM_Odm->RateAdaptive.LowRSSIThresh = (u8)Value;
 961                         break;
 962 #if(BT_30_SUPPORT == 1)
 963                 // The following is for BT HS mode and BT coexist mechanism.
 964                 case ODM_CMNINFO_BT_DISABLED:
 965                         pDM_Odm->bBtDisabled = (bool)Value;
 966                         break;
 967
 968                 case    ODM_CMNINFO_BT_OPERATION:
 969                         pDM_Odm->bBtHsOperation = (bool)Value;
 970                         break;
 971
 972                 case ODM_CMNINFO_BT_DIG:
 973                         pDM_Odm->btHsDigVal = (u8)Value;
 974                         break;
 975
 976                 case    ODM_CMNINFO_BT_BUSY:
 977                         pDM_Odm->bBtBusy = (bool)Value;
 978                         break;
 979
 980                 case    ODM_CMNINFO_BT_DISABLE_EDCA:
 981                         pDM_Odm->bBtDisableEdcaTurbo = (bool)Value;
 982                         break;
 983 #endif
 984
 985         }
 986
 987
 988 }
 989
 990 void
 991 odm_CommonInfoSelfInit(
 992                 PDM_ODM_T               pDM_Odm
 993         )
 994 {
 995         pDM_Odm->bCckHighPower = (bool) ODM_GetBBReg(pDM_Odm, 0x824, BIT9);
 996         pDM_Odm->RFPathRxEnable = (u8) ODM_GetBBReg(pDM_Odm, 0xc04, 0x0F);
 997         if(pDM_Odm->SupportICType & (ODM_RTL8192C|ODM_RTL8192D))
 998         {
 999 #if(defined(CONFIG_HW_ANTENNA_DIVERSITY))
1000                 pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV;
1001 #elif (defined(CONFIG_SW_ANTENNA_DIVERSITY))
1002                 pDM_Odm->AntDivType = CGCS_RX_SW_ANTDIV;
1003 #endif
1004         }
1005         if(pDM_Odm->SupportICType & (ODM_RTL8723A))
1006                 pDM_Odm->AntDivType = CGCS_RX_SW_ANTDIV;
1007
1008         ODM_InitDebugSetting(pDM_Odm);
1009 }
1010
1011 void
1012 odm_CommonInfoSelfUpdate(
1013                 PDM_ODM_T               pDM_Odm
1014         )
1015 {
1016         u8      EntryCnt=0;
1017         u8      i;
1018         PSTA_INFO_T     pEntry;
1019
1020         if(*(pDM_Odm->pBandWidth) == ODM_BW40M)
1021         {
1022                 if(*(pDM_Odm->pSecChOffset) == 1)
1023                         pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) -2;
1024                 else if(*(pDM_Odm->pSecChOffset) == 2)
1025                         pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) +2;
1026         }
1027         else
1028                 pDM_Odm->ControlChannel = *(pDM_Odm->pChannel);
1029
1030         for (i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++)
1031         {
1032                 pEntry = pDM_Odm->pODM_StaInfo[i];
1033                 if(IS_STA_VALID(pEntry))
1034                         EntryCnt++;
1035         }
1036         if(EntryCnt == 1)
1037                 pDM_Odm->bOneEntryOnly = TRUE;
1038         else
1039                 pDM_Odm->bOneEntryOnly = FALSE;
1040 }
1041
1042 void
1043 odm_CmnInfoInit_Debug(
1044                 PDM_ODM_T               pDM_Odm
1045         )
1046 {
1047         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoInit_Debug==>\n"));
1048         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportPlatform=%d\n",pDM_Odm->SupportPlatform) );
1049         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportAbility=0x%x\n",pDM_Odm->SupportAbility) );
1050         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportInterface=%d\n",pDM_Odm->SupportInterface) );
1051         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportICType=0x%x\n",pDM_Odm->SupportICType) );
1052         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("CutVersion=%d\n",pDM_Odm->CutVersion) );
1053         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("FabVersion=%d\n",pDM_Odm->FabVersion) );
1054         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("RFType=%d\n",pDM_Odm->RFType) );
1055         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("BoardType=%d\n",pDM_Odm->BoardType) );
1056         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtLNA=%d\n",pDM_Odm->ExtLNA) );
1057         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtPA=%d\n",pDM_Odm->ExtPA) );
1058         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtTRSW=%d\n",pDM_Odm->ExtTRSW) );
1059         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("PatchID=%d\n",pDM_Odm->PatchID) );
1060         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("bInHctTest=%d\n",pDM_Odm->bInHctTest) );
1061         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFITest=%d\n",pDM_Odm->bWIFITest) );
1062         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("bDualMacSmartConcurrent=%d\n",pDM_Odm->bDualMacSmartConcurrent) );
1063
1064 }
1065
1066 void
1067 odm_CmnInfoHook_Debug(
1068                 PDM_ODM_T               pDM_Odm
1069         )
1070 {
1071         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoHook_Debug==>\n"));
1072         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pNumTxBytesUnicast=%llu\n",*(pDM_Odm->pNumTxBytesUnicast)) );
1073         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pNumRxBytesUnicast=%llu\n",*(pDM_Odm->pNumRxBytesUnicast)) );
1074         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pWirelessMode=0x%x\n",*(pDM_Odm->pWirelessMode)) );
1075         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pSecChOffset=%d\n",*(pDM_Odm->pSecChOffset)) );
1076         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pSecurity=%d\n",*(pDM_Odm->pSecurity)) );
1077         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pBandWidth=%d\n",*(pDM_Odm->pBandWidth)) );
1078         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pChannel=%d\n",*(pDM_Odm->pChannel)) );
1079
1080 #if (RTL8192D_SUPPORT==1)
1081         if(pDM_Odm->pBandType)
1082             ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pBandType=%d\n",*(pDM_Odm->pBandType)) );
1083         if(pDM_Odm->pMacPhyMode)
1084             ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pMacPhyMode=%d\n",*(pDM_Odm->pMacPhyMode)) );
1085         if(pDM_Odm->pBuddyAdapter)
1086             ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pbGetValueFromOtherMac=%d\n",*(pDM_Odm->pbGetValueFromOtherMac)) );
1087         if(pDM_Odm->pBuddyAdapter)
1088             ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pBuddyAdapter=%p\n",*(pDM_Odm->pBuddyAdapter)) );
1089         if(pDM_Odm->pbMasterOfDMSP)
1090             ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pbMasterOfDMSP=%d\n",*(pDM_Odm->pbMasterOfDMSP)) );
1091 #endif
1092         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pbScanInProcess=%d\n",*(pDM_Odm->pbScanInProcess)) );
1093         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pbPowerSaving=%d\n",*(pDM_Odm->pbPowerSaving)) );
1094
1095         if(pDM_Odm->SupportPlatform & (ODM_AP|ODM_ADSL))
1096                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pOnePathCCA=%d\n",*(pDM_Odm->pOnePathCCA)) );
1097 }
1098
1099 void
1100 odm_CmnInfoUpdate_Debug(
1101                 PDM_ODM_T               pDM_Odm
1102         )
1103 {
1104         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoUpdate_Debug==>\n"));
1105         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFI_Direct=%d\n",pDM_Odm->bWIFI_Direct) );
1106         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFI_Display=%d\n",pDM_Odm->bWIFI_Display) );
1107         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("bLinked=%d\n",pDM_Odm->bLinked) );
1108         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("RSSI_Min=%d\n",pDM_Odm->RSSI_Min) );
1109 }
1110
1111
1112 /*
1113 void
1114 odm_FindMinimumRSSI(
1115                 PDM_ODM_T               pDM_Odm
1116         )
1117 {
1118         u4Byte  i;
1119         u8      RSSI_Min = 0xFF;
1120
1121         for(i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++)
1122         {
1123 //              if(pDM_Odm->pODM_StaInfo[i] != NULL)
1124                 if(IS_STA_VALID(pDM_Odm->pODM_StaInfo[i]) )
1125                 {
1126                         if(pDM_Odm->pODM_StaInfo[i]->RSSI_Ave < RSSI_Min)
1127                         {
1128                                 RSSI_Min = pDM_Odm->pODM_StaInfo[i]->RSSI_Ave;
1129                         }
1130                 }
1131         }
1132
1133         pDM_Odm->RSSI_Min = RSSI_Min;
1134
1135 }
1136
1137 void
1138 odm_IsLinked(
1139                 PDM_ODM_T               pDM_Odm
1140         )
1141 {
1142         u4Byte i;
1143         bool Linked = FALSE;
1144
1145         for(i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++)
1146         {
1147                         if(IS_STA_VALID(pDM_Odm->pODM_StaInfo[i]) )
1148                         {
1149                                 Linked = TRUE;
1150                                 break;
1151                         }
1152
1153         }
1154
1155         pDM_Odm->bLinked = Linked;
1156 }
1157 */
1158
1159
1160 //3============================================================
1161 //3 DIG
1162 //3============================================================
1163 /*-----------------------------------------------------------------------------
1164  * Function:    odm_DIGInit()
1165  *
1166  * Overview:    Set DIG scheme init value.
1167  *
1168  * Input:               NONE
1169  *
1170  * Output:              NONE
1171  *
1172  * Return:              NONE
1173  *
1174  * Revised History:
1175  *      When            Who             Remark
1176  *
1177  *---------------------------------------------------------------------------*/
1178 void
1179 ODM_ChangeDynamicInitGainThresh(
1180         PDM_ODM_T       pDM_Odm,
1181         u4Byte          DM_Type,
1182         u4Byte          DM_Value
1183         )
1184 {
1185         pDIG_T  pDM_DigTable = &pDM_Odm->DM_DigTable;
1186
1187         if (DM_Type == DIG_TYPE_THRESH_HIGH)
1188         {
1189                 pDM_DigTable->RssiHighThresh = DM_Value;
1190         }
1191         else if (DM_Type == DIG_TYPE_THRESH_LOW)
1192         {
1193                 pDM_DigTable->RssiLowThresh = DM_Value;
1194         }
1195         else if (DM_Type == DIG_TYPE_ENABLE)
1196         {
1197                 pDM_DigTable->Dig_Enable_Flag   = TRUE;
1198         }
1199         else if (DM_Type == DIG_TYPE_DISABLE)
1200         {
1201                 pDM_DigTable->Dig_Enable_Flag = FALSE;
1202         }
1203         else if (DM_Type == DIG_TYPE_BACKOFF)
1204         {
1205                 if(DM_Value > 30)
1206                         DM_Value = 30;
1207                 pDM_DigTable->BackoffVal = (u8)DM_Value;
1208         }
1209         else if(DM_Type == DIG_TYPE_RX_GAIN_MIN)
1210         {
1211                 if(DM_Value == 0)
1212                         DM_Value = 0x1;
1213                 pDM_DigTable->rx_gain_range_min = (u8)DM_Value;
1214         }
1215         else if(DM_Type == DIG_TYPE_RX_GAIN_MAX)
1216         {
1217                 if(DM_Value > 0x50)
1218                         DM_Value = 0x50;
1219                 pDM_DigTable->rx_gain_range_max = (u8)DM_Value;
1220         }
1221 }       /* DM_ChangeDynamicInitGainThresh */
1222
1223 int getIGIForDiff(int value_IGI)
1224 {
1225         #define ONERCCA_LOW_TH          0x30
1226         #define ONERCCA_LOW_DIFF        8
1227
1228         if (value_IGI < ONERCCA_LOW_TH) {
1229                 if ((ONERCCA_LOW_TH - value_IGI) < ONERCCA_LOW_DIFF)
1230                         return ONERCCA_LOW_TH;
1231                 else
1232                         return value_IGI + ONERCCA_LOW_DIFF;
1233         } else {
1234                 return value_IGI;
1235         }
1236 }
1237
1238
1239 void
1240 ODM_Write_DIG(
1241         PDM_ODM_T               pDM_Odm,
1242         u8                      CurrentIGI
1243         )
1244 {
1245         pDIG_T  pDM_DigTable = &pDM_Odm->DM_DigTable;
1246
1247         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("ODM_REG(IGI_A,pDM_Odm)=0x%x, ODM_BIT(IGI,pDM_Odm)=0x%x \n",
1248                 ODM_REG(IGI_A,pDM_Odm),ODM_BIT(IGI,pDM_Odm)));
1249
1250         if(pDM_DigTable->CurIGValue != CurrentIGI)//if(pDM_DigTable->PreIGValue != CurrentIGI)
1251         {
1252                 if(pDM_Odm->SupportPlatform & (ODM_CE|ODM_MP))
1253                 {
1254                         ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI);
1255                                 if(pDM_Odm->SupportICType != ODM_RTL8188E)
1256                                 ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI);
1257                 }
1258                 else if(pDM_Odm->SupportPlatform & (ODM_AP|ODM_ADSL))
1259                 {
1260                         switch(*(pDM_Odm->pOnePathCCA))
1261                         {
1262                         case ODM_CCA_2R:
1263                                 ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI);
1264                                         if(pDM_Odm->SupportICType != ODM_RTL8188E)
1265                                         ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI);
1266                                 break;
1267                         case ODM_CCA_1R_A:
1268                                 ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI);
1269                                         if(pDM_Odm->SupportICType != ODM_RTL8188E)
1270                                         ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B,pDM_Odm), ODM_BIT(IGI,pDM_Odm), getIGIForDiff(CurrentIGI));
1271                                 break;
1272                         case ODM_CCA_1R_B:
1273                                 ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm), getIGIForDiff(CurrentIGI));
1274                                         if(pDM_Odm->SupportICType != ODM_RTL8188E)
1275                                         ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI);
1276                                         break;
1277                                 }
1278                 }
1279                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("CurrentIGI(0x%02x). \n",CurrentIGI));
1280                 //pDM_DigTable->PreIGValue = pDM_DigTable->CurIGValue;
1281                 pDM_DigTable->CurIGValue = CurrentIGI;
1282         }
1283         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("ODM_Write_DIG():CurrentIGI=0x%x \n",CurrentIGI));
1284 }
1285
1286
1287 //Need LPS mode for CE platform --2012--08--24---
1288 //8723AS/8189ES
1289 void
1290 odm_DIGbyRSSI_LPS(
1291                 PDM_ODM_T               pDM_Odm
1292         )
1293 {
1294         PADAPTER                                        pAdapter =pDM_Odm->Adapter;
1295         pDIG_T                                          pDM_DigTable = &pDM_Odm->DM_DigTable;
1296         PFALSE_ALARM_STATISTICS         pFalseAlmCnt = &pDM_Odm->FalseAlmCnt;
1297         u8      RSSI_Lower=DM_DIG_MIN_NIC;   //0x1E or 0x1C
1298         u8      bFwCurrentInPSMode = FALSE;
1299         u8      CurrentIGI=pDM_Odm->RSSI_Min;
1300
1301         if(! (pDM_Odm->SupportICType & (ODM_RTL8723A |ODM_RTL8188E)))
1302                 return;
1303
1304         //if((pDM_Odm->SupportInterface==ODM_ITRF_PCIE)||(pDM_Odm->SupportInterface ==ODM_ITRF_USB))
1305         //      return;
1306
1307         CurrentIGI=CurrentIGI+RSSI_OFFSET_DIG;
1308 #ifdef CONFIG_LPS
1309         bFwCurrentInPSMode = pAdapter->pwrctrlpriv.bFwCurrentInPSMode;
1310 #endif
1311
1312         //ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG_LPS, ODM_DBG_LOUD, ("odm_DIG()==>\n"));
1313
1314         // Using FW PS mode to make IGI
1315         if(bFwCurrentInPSMode)
1316         {
1317                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("---Neil---odm_DIG is in LPS mode\n"));
1318                 //Adjust by  FA in LPS MODE
1319                 if(pFalseAlmCnt->Cnt_all> DM_DIG_FA_TH2_LPS)
1320                         CurrentIGI = CurrentIGI+2;
1321                 else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1_LPS)
1322                         CurrentIGI = CurrentIGI+1;
1323                 else if(pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0_LPS)
1324                         CurrentIGI = CurrentIGI-1;
1325         }
1326         else
1327         {
1328                 CurrentIGI = RSSI_Lower;
1329         }
1330
1331         //Lower bound checking
1332
1333         //RSSI Lower bound check
1334         if((pDM_Odm->RSSI_Min-10) > DM_DIG_MIN_NIC)
1335                 RSSI_Lower =(pDM_Odm->RSSI_Min-10);
1336         else
1337                 RSSI_Lower =DM_DIG_MIN_NIC;
1338
1339         //Upper and Lower Bound checking
1340          if(CurrentIGI > DM_DIG_MAX_NIC)
1341                 CurrentIGI=DM_DIG_MAX_NIC;
1342          else if(CurrentIGI < RSSI_Lower)
1343                 CurrentIGI =RSSI_Lower;
1344
1345         ODM_Write_DIG(pDM_Odm, CurrentIGI);//ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue);
1346
1347 }
1348
1349
1350 void
1351 odm_DIGInit(
1352                 PDM_ODM_T               pDM_Odm
1353         )
1354 {
1355         pDIG_T  pDM_DigTable = &pDM_Odm->DM_DigTable;
1356
1357         //pDM_DigTable->Dig_Enable_Flag = TRUE;
1358         //pDM_DigTable->Dig_Ext_Port_Stage = DIG_EXT_PORT_STAGE_MAX;
1359         pDM_DigTable->CurIGValue = (u8) ODM_GetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm));
1360         //pDM_DigTable->PreIGValue = 0x0;
1361         //pDM_DigTable->CurSTAConnectState = pDM_DigTable->PreSTAConnectState = DIG_STA_DISCONNECT;
1362         //pDM_DigTable->CurMultiSTAConnectState = DIG_MultiSTA_DISCONNECT;
1363         pDM_DigTable->RssiLowThresh     = DM_DIG_THRESH_LOW;
1364         pDM_DigTable->RssiHighThresh    = DM_DIG_THRESH_HIGH;
1365         pDM_DigTable->FALowThresh       = DM_FALSEALARM_THRESH_LOW;
1366         pDM_DigTable->FAHighThresh      = DM_FALSEALARM_THRESH_HIGH;
1367         if(pDM_Odm->BoardType == ODM_BOARD_HIGHPWR)
1368         {
1369                 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC;
1370                 pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC;
1371         }
1372         else
1373         {
1374                 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC;
1375                 pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC;
1376         }
1377         pDM_DigTable->BackoffVal = DM_DIG_BACKOFF_DEFAULT;
1378         pDM_DigTable->BackoffVal_range_max = DM_DIG_BACKOFF_MAX;
1379         pDM_DigTable->BackoffVal_range_min = DM_DIG_BACKOFF_MIN;
1380         pDM_DigTable->PreCCK_CCAThres = 0xFF;
1381         pDM_DigTable->CurCCK_CCAThres = 0x83;
1382         pDM_DigTable->ForbiddenIGI = DM_DIG_MIN_NIC;
1383         pDM_DigTable->LargeFAHit = 0;
1384         pDM_DigTable->Recover_cnt = 0;
1385         pDM_DigTable->DIG_Dynamic_MIN_0 =DM_DIG_MIN_NIC;
1386         pDM_DigTable->DIG_Dynamic_MIN_1 = DM_DIG_MIN_NIC;
1387         pDM_DigTable->bMediaConnect_0 = FALSE;
1388         pDM_DigTable->bMediaConnect_1 = FALSE;
1389
1390         //To Initialize pDM_Odm->bDMInitialGainEnable == FALSE to avoid DIG error
1391         pDM_Odm->bDMInitialGainEnable = TRUE;
1392
1393 }
1394
1395
1396 void
1397 odm_DIG(
1398                 PDM_ODM_T               pDM_Odm
1399         )
1400 {
1401
1402         pDIG_T                                          pDM_DigTable = &pDM_Odm->DM_DigTable;
1403         PFALSE_ALARM_STATISTICS         pFalseAlmCnt = &pDM_Odm->FalseAlmCnt;
1404         pRXHP_T                                         pRX_HP_Table  = &pDM_Odm->DM_RXHP_Table;
1405         u8                                              DIG_Dynamic_MIN;
1406         u8                                              DIG_MaxOfMin;
1407         bool                                            FirstConnect, FirstDisConnect;
1408         u8                                              dm_dig_max, dm_dig_min;
1409         u8                                              CurrentIGI = pDM_DigTable->CurIGValue;
1410
1411
1412         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG()==>\n"));
1413         //if(!(pDM_Odm->SupportAbility & (ODM_BB_DIG|ODM_BB_FA_CNT)))
1414         if((!(pDM_Odm->SupportAbility&ODM_BB_DIG)) ||(!(pDM_Odm->SupportAbility&ODM_BB_FA_CNT)))
1415         {
1416                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: SupportAbility ODM_BB_DIG or ODM_BB_FA_CNT is disabled\n"));
1417                 return;
1418         }
1419
1420         if(*(pDM_Odm->pbScanInProcess))
1421         {
1422                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: In Scan Progress \n"));
1423                 return;
1424         }
1425
1426         //add by Neil Chen to avoid PSD is processing
1427         if(pDM_Odm->bDMInitialGainEnable == FALSE)
1428         {
1429                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: PSD is Processing \n"));
1430                 return;
1431         }
1432
1433         if(pDM_Odm->SupportICType == ODM_RTL8192D)
1434         {
1435                 if(*(pDM_Odm->pMacPhyMode) == ODM_DMSP)
1436                 {
1437                         if(*(pDM_Odm->pbMasterOfDMSP))
1438                         {
1439                                 DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0;
1440                                 FirstConnect = (pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == FALSE);
1441                                 FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == TRUE);
1442                         }
1443                         else
1444                         {
1445                                 DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_1;
1446                                 FirstConnect = (pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_1 == FALSE);
1447                                 FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_1 == TRUE);
1448                         }
1449                 }
1450                 else
1451                 {
1452                         if(*(pDM_Odm->pBandType) == ODM_BAND_5G)
1453                         {
1454                                 DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0;
1455                                 FirstConnect = (pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == FALSE);
1456                                 FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == TRUE);
1457                         }
1458                         else
1459                         {
1460                                 DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_1;
1461                                 FirstConnect = (pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_1 == FALSE);
1462                                 FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_1 == TRUE);
1463                         }
1464                 }
1465         }
1466         else
1467         {
1468                 DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0;
1469                 FirstConnect = (pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == FALSE);
1470                 FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == TRUE);
1471         }
1472
1473         //1 Boundary Decision
1474         if((pDM_Odm->SupportICType & (ODM_RTL8192C|ODM_RTL8723A)) &&
1475                 ((pDM_Odm->BoardType == ODM_BOARD_HIGHPWR) || pDM_Odm->ExtLNA))
1476         {
1477                 if(pDM_Odm->SupportPlatform & (ODM_AP|ODM_ADSL))
1478                 {
1479
1480                         dm_dig_max = DM_DIG_MAX_AP_HP;
1481                         dm_dig_min = DM_DIG_MIN_AP_HP;
1482                 }
1483                 else
1484                 {
1485                         dm_dig_max = DM_DIG_MAX_NIC_HP;
1486                         dm_dig_min = DM_DIG_MIN_NIC_HP;
1487                 }
1488                 DIG_MaxOfMin = DM_DIG_MAX_AP_HP;
1489         }
1490         else
1491         {
1492                 if(pDM_Odm->SupportPlatform & (ODM_AP|ODM_ADSL))
1493                 {
1494                         dm_dig_max = DM_DIG_MAX_AP;
1495                         dm_dig_min = DM_DIG_MIN_AP;
1496                         DIG_MaxOfMin = dm_dig_max;
1497                 }
1498                 else
1499                 {
1500                         dm_dig_max = DM_DIG_MAX_NIC;
1501                         dm_dig_min = DM_DIG_MIN_NIC;
1502                         DIG_MaxOfMin = DM_DIG_MAX_AP;
1503                 }
1504         }
1505
1506
1507         if(pDM_Odm->bLinked)
1508         {
1509               //2 8723A Series, offset need to be 10 //neil
1510                 if(pDM_Odm->SupportICType==(ODM_RTL8723A))
1511                 {
1512                         //2 Upper Bound
1513                         if(( pDM_Odm->RSSI_Min + 10) > DM_DIG_MAX_NIC )
1514                                 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC;
1515                         else if(( pDM_Odm->RSSI_Min + 10) < DM_DIG_MIN_NIC )
1516                                 pDM_DigTable->rx_gain_range_max = DM_DIG_MIN_NIC;
1517                         else
1518                                 pDM_DigTable->rx_gain_range_max = pDM_Odm->RSSI_Min + 10;
1519
1520                         //2 If BT is Concurrent, need to set Lower Bound
1521
1522 #if(BT_30_SUPPORT == 1)
1523                         if(pDM_Odm->bBtBusy)
1524                         {
1525                                 if(pDM_Odm->RSSI_Min>10)
1526                                 {
1527                                 if((pDM_Odm->RSSI_Min - 10) > DM_DIG_MAX_NIC)
1528                                                 DIG_Dynamic_MIN = DM_DIG_MAX_NIC;
1529                                 else if((pDM_Odm->RSSI_Min - 10) < DM_DIG_MIN_NIC)
1530                                                 DIG_Dynamic_MIN = DM_DIG_MIN_NIC;
1531                                         else
1532                                                 DIG_Dynamic_MIN = pDM_Odm->RSSI_Min - 10;
1533                                 }
1534                                 else
1535                                         DIG_Dynamic_MIN=DM_DIG_MIN_NIC;
1536                         }
1537                         else
1538 #endif
1539                         {
1540                                 DIG_Dynamic_MIN=DM_DIG_MIN_NIC;
1541                         }
1542                 }
1543                 else
1544                 {
1545                 //2 Modify DIG upper bound
1546                         if((pDM_Odm->RSSI_Min + 20) > dm_dig_max )
1547                                 pDM_DigTable->rx_gain_range_max = dm_dig_max;
1548                         else if((pDM_Odm->RSSI_Min + 20) < dm_dig_min )
1549                                 pDM_DigTable->rx_gain_range_max = dm_dig_min;
1550                         else
1551                                 pDM_DigTable->rx_gain_range_max = pDM_Odm->RSSI_Min + 20;
1552
1553
1554                 //2 Modify DIG lower bound
1555         /*
1556                 if((pFalseAlmCnt->Cnt_all > 500)&&(DIG_Dynamic_MIN < 0x25))
1557                         DIG_Dynamic_MIN++;
1558                 else if(((pFalseAlmCnt->Cnt_all < 500)||(pDM_Odm->RSSI_Min < 8))&&(DIG_Dynamic_MIN > dm_dig_min))
1559                         DIG_Dynamic_MIN--;
1560         */
1561                         if(pDM_Odm->bOneEntryOnly)
1562                         {
1563                                 if(pDM_Odm->RSSI_Min < dm_dig_min)
1564                                         DIG_Dynamic_MIN = dm_dig_min;
1565                                 else if (pDM_Odm->RSSI_Min > DIG_MaxOfMin)
1566                                         DIG_Dynamic_MIN = DIG_MaxOfMin;
1567                                 else
1568                                         DIG_Dynamic_MIN = pDM_Odm->RSSI_Min;
1569                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() : bOneEntryOnly=TRUE,  DIG_Dynamic_MIN=0x%x\n",DIG_Dynamic_MIN));
1570                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() : pDM_Odm->RSSI_Min=%d\n",pDM_Odm->RSSI_Min));
1571                         }
1572                         //1 Lower Bound for 88E AntDiv
1573 #if (RTL8188E_SUPPORT == 1)
1574                         else if((pDM_Odm->SupportICType == ODM_RTL8188E)&&(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV))
1575                         {
1576                                 if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)
1577                                 {
1578                                         DIG_Dynamic_MIN = (u8) pDM_DigTable->AntDiv_RSSI_max;
1579                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_DIG(): pDM_DigTable->AntDiv_RSSI_max=%d \n",pDM_DigTable->AntDiv_RSSI_max));
1580                                 }
1581                         }
1582 #endif
1583                         else
1584                         {
1585                                 DIG_Dynamic_MIN=dm_dig_min;
1586                         }
1587                 }
1588         }
1589         else
1590         {
1591                 pDM_DigTable->rx_gain_range_max = dm_dig_max;
1592                 DIG_Dynamic_MIN = dm_dig_min;
1593                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() : No Link\n"));
1594         }
1595
1596         //1 Modify DIG lower bound, deal with abnormally large false alarm
1597         if(pFalseAlmCnt->Cnt_all > 10000)
1598         {
1599                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("dm_DIG(): Abnornally false alarm case. \n"));
1600
1601                 if(pDM_DigTable->LargeFAHit != 3)
1602                 pDM_DigTable->LargeFAHit++;
1603                 if(pDM_DigTable->ForbiddenIGI < CurrentIGI)//if(pDM_DigTable->ForbiddenIGI < pDM_DigTable->CurIGValue)
1604                 {
1605                         pDM_DigTable->ForbiddenIGI = CurrentIGI;//pDM_DigTable->ForbiddenIGI = pDM_DigTable->CurIGValue;
1606                         pDM_DigTable->LargeFAHit = 1;
1607                 }
1608
1609                 if(pDM_DigTable->LargeFAHit >= 3)
1610                 {
1611                         if((pDM_DigTable->ForbiddenIGI+1) >pDM_DigTable->rx_gain_range_max)
1612                                 pDM_DigTable->rx_gain_range_min = pDM_DigTable->rx_gain_range_max;
1613                         else
1614                                 pDM_DigTable->rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 1);
1615                         pDM_DigTable->Recover_cnt = 3600; //3600=2hr
1616                 }
1617
1618         }
1619         else
1620         {
1621                 //Recovery mechanism for IGI lower bound
1622                 if(pDM_DigTable->Recover_cnt != 0)
1623                         pDM_DigTable->Recover_cnt --;
1624                 else
1625                 {
1626                         if(pDM_DigTable->LargeFAHit < 3)
1627                         {
1628                                 if((pDM_DigTable->ForbiddenIGI -1) < DIG_Dynamic_MIN) //DM_DIG_MIN)
1629                                 {
1630                                         pDM_DigTable->ForbiddenIGI = DIG_Dynamic_MIN; //DM_DIG_MIN;
1631                                         pDM_DigTable->rx_gain_range_min = DIG_Dynamic_MIN; //DM_DIG_MIN;
1632                                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Normal Case: At Lower Bound\n"));
1633                                 }
1634                                 else
1635                                 {
1636                                         pDM_DigTable->ForbiddenIGI --;
1637                                         pDM_DigTable->rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 1);
1638                                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Normal Case: Approach Lower Bound\n"));
1639                                 }
1640                         }
1641                         else
1642                         {
1643                                 pDM_DigTable->LargeFAHit = 0;
1644                         }
1645                 }
1646         }
1647         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): pDM_DigTable->LargeFAHit=%d\n",pDM_DigTable->LargeFAHit));
1648
1649         //1 Adjust initial gain by false alarm
1650         if(pDM_Odm->bLinked)
1651         {
1652                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DIG AfterLink\n"));
1653                 if(FirstConnect)
1654                 {
1655                         CurrentIGI = pDM_Odm->RSSI_Min;
1656                         ODM_RT_TRACE(pDM_Odm,   ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: First Connect\n"));
1657                 }
1658                 else
1659                 {
1660                         if(pDM_Odm->SupportICType == ODM_RTL8192D)
1661                         {
1662                                 if(pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2_92D)
1663                                         CurrentIGI = CurrentIGI + 2;//pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2;
1664                                 else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1_92D)
1665                                         CurrentIGI = CurrentIGI + 1; //pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1;
1666                                 else if(pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0_92D)
1667                                         CurrentIGI = CurrentIGI - 1;//pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1;
1668                         }
1669                         else
1670                         {
1671 #if(BT_30_SUPPORT == 1)
1672                                 if(pDM_Odm->bBtBusy)
1673                                 {
1674                                         if(pFalseAlmCnt->Cnt_all > 0x300)
1675                                                 CurrentIGI = CurrentIGI + 2;
1676                                         else if (pFalseAlmCnt->Cnt_all > 0x250)
1677                                                 CurrentIGI = CurrentIGI + 1;
1678                                         else if(pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0)
1679                                                 CurrentIGI = CurrentIGI -1;
1680                                 }
1681                                 else
1682 #endif
1683                                 {
1684                                 if(pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2)
1685                                                 CurrentIGI = CurrentIGI + 4;//pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2;
1686                                 else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1)
1687                                                 CurrentIGI = CurrentIGI + 2;//pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1;
1688                                 else if(pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0)
1689                                                 CurrentIGI = CurrentIGI - 2;//pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1;
1690
1691
1692                         }
1693                 }
1694         }
1695         }
1696         else
1697         {
1698                 //CurrentIGI = pDM_DigTable->rx_gain_range_min;//pDM_DigTable->CurIGValue = pDM_DigTable->rx_gain_range_min
1699                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DIG BeforeLink\n"));
1700                 if(FirstDisConnect)
1701                 {
1702                         CurrentIGI = pDM_DigTable->rx_gain_range_min;
1703                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): First DisConnect \n"));
1704                 }
1705                 else
1706                 {
1707                 //2012.03.30 LukeLee: enable DIG before link but with very high thresholds
1708              if(pFalseAlmCnt->Cnt_all > 10000)
1709                         CurrentIGI = CurrentIGI + 2;//pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2;
1710                 else if (pFalseAlmCnt->Cnt_all > 8000)
1711                         CurrentIGI = CurrentIGI + 1;//pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1;
1712                 else if(pFalseAlmCnt->Cnt_all < 500)
1713                         CurrentIGI = CurrentIGI - 1;//pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1;
1714                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): England DIG \n"));
1715                 }
1716         }
1717         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DIG End Adjust IGI\n"));
1718         //1 Check initial gain by upper/lower bound
1719 /*
1720         if(pDM_DigTable->CurIGValue > pDM_DigTable->rx_gain_range_max)
1721                 pDM_DigTable->CurIGValue = pDM_DigTable->rx_gain_range_max;
1722         if(pDM_DigTable->CurIGValue < pDM_DigTable->rx_gain_range_min)
1723                 pDM_DigTable->CurIGValue = pDM_DigTable->rx_gain_range_min;
1724 */
1725         if(CurrentIGI > pDM_DigTable->rx_gain_range_max)
1726                 CurrentIGI = pDM_DigTable->rx_gain_range_max;
1727         if(CurrentIGI < pDM_DigTable->rx_gain_range_min)
1728                 CurrentIGI = pDM_DigTable->rx_gain_range_min;
1729
1730         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): rx_gain_range_max=0x%x, rx_gain_range_min=0x%x\n",
1731                 pDM_DigTable->rx_gain_range_max, pDM_DigTable->rx_gain_range_min));
1732         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): TotalFA=%d\n", pFalseAlmCnt->Cnt_all));
1733         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): CurIGValue=0x%x\n", CurrentIGI));
1734
1735         //2 High power RSSI threshold
1736
1737 #if (RTL8192D_SUPPORT==1)
1738         if(pDM_Odm->SupportICType == ODM_RTL8192D)
1739         {
1740                 //sherry  delete DualMacSmartConncurrent 20110517
1741                 if(*(pDM_Odm->pMacPhyMode) == ODM_DMSP)
1742                 {
1743                         ODM_Write_DIG_DMSP(pDM_Odm, CurrentIGI);//ODM_Write_DIG_DMSP(pDM_Odm, pDM_DigTable->CurIGValue);
1744                         if(*(pDM_Odm->pbMasterOfDMSP))
1745                         {
1746                                 pDM_DigTable->bMediaConnect_0 = pDM_Odm->bLinked;
1747                                 pDM_DigTable->DIG_Dynamic_MIN_0 = DIG_Dynamic_MIN;
1748                         }
1749                         else
1750                         {
1751                                 pDM_DigTable->bMediaConnect_1 = pDM_Odm->bLinked;
1752                                 pDM_DigTable->DIG_Dynamic_MIN_1 = DIG_Dynamic_MIN;
1753                         }
1754                 }
1755                 else
1756                 {
1757                         ODM_Write_DIG(pDM_Odm, CurrentIGI);//ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue);
1758                         if(*(pDM_Odm->pBandType) == ODM_BAND_5G)
1759                         {
1760                                 pDM_DigTable->bMediaConnect_0 = pDM_Odm->bLinked;
1761                                 pDM_DigTable->DIG_Dynamic_MIN_0 = DIG_Dynamic_MIN;
1762                         }
1763                         else
1764                         {
1765                                 pDM_DigTable->bMediaConnect_1 = pDM_Odm->bLinked;
1766                                 pDM_DigTable->DIG_Dynamic_MIN_1 = DIG_Dynamic_MIN;
1767                         }
1768                 }
1769         }
1770         else
1771 #endif
1772         {
1773                 ODM_Write_DIG(pDM_Odm, CurrentIGI);//ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue);
1774                 pDM_DigTable->bMediaConnect_0 = pDM_Odm->bLinked;
1775                 pDM_DigTable->DIG_Dynamic_MIN_0 = DIG_Dynamic_MIN;
1776         }
1777
1778 }
1779
1780 //3============================================================
1781 //3 FASLE ALARM CHECK
1782 //3============================================================
1783
1784 void
1785 odm_FalseAlarmCounterStatistics(
1786                 PDM_ODM_T               pDM_Odm
1787         )
1788 {
1789         u4Byte ret_value;
1790         PFALSE_ALARM_STATISTICS FalseAlmCnt = &(pDM_Odm->FalseAlmCnt);
1791
1792         if(!(pDM_Odm->SupportAbility & ODM_BB_FA_CNT))
1793                 return;
1794
1795 //      if(pDM_Odm->SupportICType != ODM_RTL8812)
1796         if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
1797         {
1798
1799         //hold ofdm counter
1800                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_HOLDC_11N, BIT31, 1); //hold page C counter
1801                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT31, 1); //hold page D counter
1802
1803                 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE1_11N, bMaskDWord);
1804         FalseAlmCnt->Cnt_Fast_Fsync = (ret_value&0xffff);
1805         FalseAlmCnt->Cnt_SB_Search_fail = ((ret_value&0xffff0000)>>16);
1806                 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE2_11N, bMaskDWord);
1807         FalseAlmCnt->Cnt_OFDM_CCA = (ret_value&0xffff);
1808         FalseAlmCnt->Cnt_Parity_Fail = ((ret_value&0xffff0000)>>16);
1809                 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE3_11N, bMaskDWord);
1810         FalseAlmCnt->Cnt_Rate_Illegal = (ret_value&0xffff);
1811         FalseAlmCnt->Cnt_Crc8_fail = ((ret_value&0xffff0000)>>16);
1812                 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE4_11N, bMaskDWord);
1813         FalseAlmCnt->Cnt_Mcs_fail = (ret_value&0xffff);
1814
1815         FalseAlmCnt->Cnt_Ofdm_fail =    FalseAlmCnt->Cnt_Parity_Fail + FalseAlmCnt->Cnt_Rate_Illegal +
1816                                                                 FalseAlmCnt->Cnt_Crc8_fail + FalseAlmCnt->Cnt_Mcs_fail +
1817                                                                 FalseAlmCnt->Cnt_Fast_Fsync + FalseAlmCnt->Cnt_SB_Search_fail;
1818
1819 #if (RTL8188E_SUPPORT==1)
1820         if(pDM_Odm->SupportICType == ODM_RTL8188E)
1821         {
1822                         ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_SC_CNT_11N, bMaskDWord);
1823                 FalseAlmCnt->Cnt_BW_LSC = (ret_value&0xffff);
1824                 FalseAlmCnt->Cnt_BW_USC = ((ret_value&0xffff0000)>>16);
1825         }
1826 #endif
1827
1828 #if (RTL8192D_SUPPORT==1)
1829         if(pDM_Odm->SupportICType == ODM_RTL8192D)
1830         {
1831                 odm_GetCCKFalseAlarm_92D(pDM_Odm);
1832         }
1833         else
1834 #endif
1835         {
1836                 //hold cck counter
1837                         ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT12, 1);
1838                         ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT14, 1);
1839
1840                         ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_LSB_11N, bMaskByte0);
1841                 FalseAlmCnt->Cnt_Cck_fail = ret_value;
1842                         ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_MSB_11N, bMaskByte3);
1843                 FalseAlmCnt->Cnt_Cck_fail +=  (ret_value& 0xff)<<8;
1844
1845                         ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_CCA_CNT_11N, bMaskDWord);
1846                 FalseAlmCnt->Cnt_CCK_CCA = ((ret_value&0xFF)<<8) |((ret_value&0xFF00)>>8);
1847         }
1848
1849         FalseAlmCnt->Cnt_all = (FalseAlmCnt->Cnt_Fast_Fsync +
1850                                                 FalseAlmCnt->Cnt_SB_Search_fail +
1851                                                 FalseAlmCnt->Cnt_Parity_Fail +
1852                                                 FalseAlmCnt->Cnt_Rate_Illegal +
1853                                                 FalseAlmCnt->Cnt_Crc8_fail +
1854                                                 FalseAlmCnt->Cnt_Mcs_fail +
1855                                                 FalseAlmCnt->Cnt_Cck_fail);
1856
1857         FalseAlmCnt->Cnt_CCA_all = FalseAlmCnt->Cnt_OFDM_CCA + FalseAlmCnt->Cnt_CCK_CCA;
1858
1859 #if (RTL8192C_SUPPORT==1)
1860         if(pDM_Odm->SupportICType == ODM_RTL8192C)
1861                 odm_ResetFACounter_92C(pDM_Odm);
1862 #endif
1863
1864 #if (RTL8192D_SUPPORT==1)
1865         if(pDM_Odm->SupportICType == ODM_RTL8192D)
1866                 odm_ResetFACounter_92D(pDM_Odm);
1867 #endif
1868
1869         if(pDM_Odm->SupportICType >=ODM_RTL8723A)
1870         {
1871                 //reset false alarm counter registers
1872                         ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT31, 1);
1873                         ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT31, 0);
1874                         ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT27, 1);
1875                         ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT27, 0);
1876                 //update ofdm counter
1877                         ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_HOLDC_11N, BIT31, 0); //update page C counter
1878                         ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT31, 0); //update page D counter
1879
1880                 //reset CCK CCA counter
1881                         ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT13|BIT12, 0);
1882                         ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT13|BIT12, 2);
1883                 //reset CCK FA counter
1884                         ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT15|BIT14, 0);
1885                         ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT15|BIT14, 2);
1886         }
1887
1888         ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Enter odm_FalseAlarmCounterStatistics\n"));
1889         ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Fast_Fsync=%d, Cnt_SB_Search_fail=%d\n",
1890                 FalseAlmCnt->Cnt_Fast_Fsync, FalseAlmCnt->Cnt_SB_Search_fail));
1891         ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Parity_Fail=%d, Cnt_Rate_Illegal=%d\n",
1892                 FalseAlmCnt->Cnt_Parity_Fail, FalseAlmCnt->Cnt_Rate_Illegal));
1893         ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Crc8_fail=%d, Cnt_Mcs_fail=%d\n",
1894                 FalseAlmCnt->Cnt_Crc8_fail, FalseAlmCnt->Cnt_Mcs_fail));
1895         }
1896         else //FOR ODM_IC_11AC_SERIES
1897         {
1898                 //read OFDM FA counter
1899                 FalseAlmCnt->Cnt_Ofdm_fail = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_11AC, bMaskLWord);
1900                 FalseAlmCnt->Cnt_Cck_fail = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_11AC, bMaskLWord);
1901                 FalseAlmCnt->Cnt_all = FalseAlmCnt->Cnt_Ofdm_fail + FalseAlmCnt->Cnt_Cck_fail;
1902
1903                 // reset OFDM FA coutner
1904                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RST_11AC, BIT17, 1);
1905                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RST_11AC, BIT17, 0);
1906                 // reset CCK FA counter
1907                 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11AC, BIT15, 0);
1908                 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11AC, BIT15, 1);
1909         }
1910         ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Cck_fail=%d\n",       FalseAlmCnt->Cnt_Cck_fail));
1911         ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Ofdm_fail=%d\n",      FalseAlmCnt->Cnt_Ofdm_fail));
1912         ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Total False Alarm=%d\n",  FalseAlmCnt->Cnt_all));
1913 }
1914
1915 //3============================================================
1916 //3 CCK Packet Detect Threshold
1917 //3============================================================
1918
1919 void
1920 odm_CCKPacketDetectionThresh(
1921                 PDM_ODM_T               pDM_Odm
1922         )
1923 {
1924
1925         pDIG_T  pDM_DigTable = &pDM_Odm->DM_DigTable;
1926         u8      CurCCK_CCAThres;
1927         PFALSE_ALARM_STATISTICS FalseAlmCnt = &(pDM_Odm->FalseAlmCnt);
1928
1929         if(!(pDM_Odm->SupportAbility & (ODM_BB_CCK_PD|ODM_BB_FA_CNT)))
1930                 return;
1931
1932         if(pDM_Odm->ExtLNA)
1933                 return;
1934
1935         if(pDM_Odm->bLinked)
1936         {
1937                 if(pDM_Odm->RSSI_Min > 25)
1938                         CurCCK_CCAThres = 0xcd;
1939                 else if((pDM_Odm->RSSI_Min <= 25) && (pDM_Odm->RSSI_Min > 10))
1940                         CurCCK_CCAThres = 0x83;
1941                 else
1942                 {
1943                         if(FalseAlmCnt->Cnt_Cck_fail > 1000)
1944                                 CurCCK_CCAThres = 0x83;
1945                         else
1946                                 CurCCK_CCAThres = 0x40;
1947                 }
1948         }
1949         else
1950         {
1951                 if(FalseAlmCnt->Cnt_Cck_fail > 1000)
1952                         CurCCK_CCAThres = 0x83;
1953                 else
1954                         CurCCK_CCAThres = 0x40;
1955         }
1956
1957 #if (RTL8192D_SUPPORT==1)
1958         if(pDM_Odm->SupportICType == ODM_RTL8192D)
1959                 ODM_Write_CCK_CCA_Thres_92D(pDM_Odm, CurCCK_CCAThres);
1960         else
1961 #endif
1962                 ODM_Write_CCK_CCA_Thres(pDM_Odm, CurCCK_CCAThres);
1963 }
1964
1965 void
1966 ODM_Write_CCK_CCA_Thres(
1967         PDM_ODM_T               pDM_Odm,
1968         u8                      CurCCK_CCAThres
1969         )
1970 {
1971         pDIG_T  pDM_DigTable = &pDM_Odm->DM_DigTable;
1972
1973         if(pDM_DigTable->CurCCK_CCAThres!=CurCCK_CCAThres)              //modify by Guo.Mingzhi 2012-01-03
1974         {
1975                 ODM_Write1Byte(pDM_Odm, ODM_REG(CCK_CCA,pDM_Odm), CurCCK_CCAThres);
1976         }
1977         pDM_DigTable->PreCCK_CCAThres = pDM_DigTable->CurCCK_CCAThres;
1978         pDM_DigTable->CurCCK_CCAThres = CurCCK_CCAThres;
1979
1980 }
1981
1982 //3============================================================
1983 //3 BB Power Save
1984 //3============================================================
1985 void
1986 odm_DynamicBBPowerSavingInit(
1987                 PDM_ODM_T               pDM_Odm
1988         )
1989 {
1990         pPS_T   pDM_PSTable = &pDM_Odm->DM_PSTable;
1991
1992         pDM_PSTable->PreCCAState = CCA_MAX;
1993         pDM_PSTable->CurCCAState = CCA_MAX;
1994         pDM_PSTable->PreRFState = RF_MAX;
1995         pDM_PSTable->CurRFState = RF_MAX;
1996         pDM_PSTable->Rssi_val_min = 0;
1997         pDM_PSTable->initialize = 0;
1998 }
1999
2000
2001 void
2002 odm_DynamicBBPowerSaving(
2003                 PDM_ODM_T               pDM_Odm
2004         )
2005 {
2006         if ((pDM_Odm->SupportICType != ODM_RTL8192C) && (pDM_Odm->SupportICType != ODM_RTL8723A))
2007                 return;
2008         if(!(pDM_Odm->SupportAbility & ODM_BB_PWR_SAVE))
2009                 return;
2010         if(!(pDM_Odm->SupportPlatform & (ODM_MP|ODM_CE)))
2011                 return;
2012
2013         //1 2.Power Saving for 92C
2014         if((pDM_Odm->SupportICType == ODM_RTL8192C) &&(pDM_Odm->RFType == ODM_2T2R))
2015         {
2016                 odm_1R_CCA(pDM_Odm);
2017         }
2018
2019         // 20100628 Joseph: Turn off BB power save for 88CE because it makesthroughput unstable.
2020         // 20100831 Joseph: Turn ON BB power save again after modifying AGC delay from 900ns ot 600ns.
2021         //1 3.Power Saving for 88C
2022         else
2023         {
2024                 ODM_RF_Saving(pDM_Odm, FALSE);
2025         }
2026 }
2027
2028 void
2029 odm_1R_CCA(
2030         PDM_ODM_T       pDM_Odm
2031         )
2032 {
2033         pPS_T   pDM_PSTable = &pDM_Odm->DM_PSTable;
2034
2035         if(pDM_Odm->RSSI_Min!= 0xFF)
2036         {
2037
2038                 if(pDM_PSTable->PreCCAState == CCA_2R)
2039                 {
2040                         if(pDM_Odm->RSSI_Min >= 35)
2041                                 pDM_PSTable->CurCCAState = CCA_1R;
2042                         else
2043                                 pDM_PSTable->CurCCAState = CCA_2R;
2044
2045                 }
2046                 else{
2047                         if(pDM_Odm->RSSI_Min <= 30)
2048                                 pDM_PSTable->CurCCAState = CCA_2R;
2049                         else
2050                                 pDM_PSTable->CurCCAState = CCA_1R;
2051                 }
2052         }
2053         else{
2054                 pDM_PSTable->CurCCAState=CCA_MAX;
2055         }
2056
2057         if(pDM_PSTable->PreCCAState != pDM_PSTable->CurCCAState)
2058         {
2059                 if(pDM_PSTable->CurCCAState == CCA_1R)
2060                 {
2061                         if(  pDM_Odm->RFType ==ODM_2T2R )
2062                         {
2063                                 ODM_SetBBReg(pDM_Odm, 0xc04  , bMaskByte0, 0x13);
2064                                 //PHY_SetBBReg(pAdapter, 0xe70, bMaskByte3, 0x20);
2065                         }
2066                         else
2067                         {
2068                                 ODM_SetBBReg(pDM_Odm, 0xc04  , bMaskByte0, 0x23);
2069                                 //PHY_SetBBReg(pAdapter, 0xe70, 0x7fc00000, 0x10c); // Set RegE70[30:22] = 9b'100001100
2070                         }
2071                 }
2072                 else
2073                 {
2074                         ODM_SetBBReg(pDM_Odm, 0xc04  , bMaskByte0, 0x33);
2075                         //PHY_SetBBReg(pAdapter,0xe70, bMaskByte3, 0x63);
2076                 }
2077                 pDM_PSTable->PreCCAState = pDM_PSTable->CurCCAState;
2078         }
2079         //ODM_RT_TRACE(pDM_Odm, COMP_BB_POWERSAVING, DBG_LOUD, ("CCAStage = %s\n",(pDM_PSTable->CurCCAState==0)?"1RCCA":"2RCCA"));
2080 }
2081
2082 void
2083 ODM_RF_Saving(
2084         PDM_ODM_T       pDM_Odm,
2085         u8              bForceInNormal
2086         )
2087 {
2088         pPS_T   pDM_PSTable = &pDM_Odm->DM_PSTable;
2089         u8      Rssi_Up_bound = 30 ;
2090         u8      Rssi_Low_bound = 25;
2091         if(pDM_Odm->PatchID == 40 ) //RT_CID_819x_FUNAI_TV
2092         {
2093                 Rssi_Up_bound = 50 ;
2094                 Rssi_Low_bound = 45;
2095         }
2096         if(pDM_PSTable->initialize == 0){
2097
2098                 pDM_PSTable->Reg874 = (ODM_GetBBReg(pDM_Odm, 0x874, bMaskDWord)&0x1CC000)>>14;
2099                 pDM_PSTable->RegC70 = (ODM_GetBBReg(pDM_Odm, 0xc70, bMaskDWord)&BIT3)>>3;
2100                 pDM_PSTable->Reg85C = (ODM_GetBBReg(pDM_Odm, 0x85c, bMaskDWord)&0xFF000000)>>24;
2101                 pDM_PSTable->RegA74 = (ODM_GetBBReg(pDM_Odm, 0xa74, bMaskDWord)&0xF000)>>12;
2102                 //Reg818 = PHY_QueryBBReg(pAdapter, 0x818, bMaskDWord);
2103                 pDM_PSTable->initialize = 1;
2104         }
2105
2106         if(!bForceInNormal)
2107         {
2108                 if(pDM_Odm->RSSI_Min != 0xFF)
2109                 {
2110                         if(pDM_PSTable->PreRFState == RF_Normal)
2111                         {
2112                                 if(pDM_Odm->RSSI_Min >= Rssi_Up_bound)
2113                                         pDM_PSTable->CurRFState = RF_Save;
2114                                 else
2115                                         pDM_PSTable->CurRFState = RF_Normal;
2116                         }
2117                         else{
2118                                 if(pDM_Odm->RSSI_Min <= Rssi_Low_bound)
2119                                         pDM_PSTable->CurRFState = RF_Normal;
2120                                 else
2121                                         pDM_PSTable->CurRFState = RF_Save;
2122                         }
2123                 }
2124                 else
2125                         pDM_PSTable->CurRFState=RF_MAX;
2126         }
2127         else
2128         {
2129                 pDM_PSTable->CurRFState = RF_Normal;
2130         }
2131
2132         if(pDM_PSTable->PreRFState != pDM_PSTable->CurRFState)
2133         {
2134                 if(pDM_PSTable->CurRFState == RF_Save)
2135                 {
2136                         // <tynli_note> 8723 RSSI report will be wrong. Set 0x874[5]=1 when enter BB power saving mode.
2137                         // Suggested by SD3 Yu-Nan. 2011.01.20.
2138                         if(pDM_Odm->SupportICType == ODM_RTL8723A)
2139                         {
2140                                 ODM_SetBBReg(pDM_Odm, 0x874  , BIT5, 0x1); //Reg874[5]=1b'1
2141                         }
2142                         ODM_SetBBReg(pDM_Odm, 0x874  , 0x1C0000, 0x2); //Reg874[20:18]=3'b010
2143                         ODM_SetBBReg(pDM_Odm, 0xc70, BIT3, 0); //RegC70[3]=1'b0
2144                         ODM_SetBBReg(pDM_Odm, 0x85c, 0xFF000000, 0x63); //Reg85C[31:24]=0x63
2145                         ODM_SetBBReg(pDM_Odm, 0x874, 0xC000, 0x2); //Reg874[15:14]=2'b10
2146                         ODM_SetBBReg(pDM_Odm, 0xa74, 0xF000, 0x3); //RegA75[7:4]=0x3
2147                         ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 0x0); //Reg818[28]=1'b0
2148                         ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 0x1); //Reg818[28]=1'b1
2149                         //ODM_RT_TRACE(pDM_Odm, COMP_BB_POWERSAVING, DBG_LOUD, (" RF_Save"));
2150                 }
2151                 else
2152                 {
2153                         ODM_SetBBReg(pDM_Odm, 0x874  , 0x1CC000, pDM_PSTable->Reg874);
2154                         ODM_SetBBReg(pDM_Odm, 0xc70, BIT3, pDM_PSTable->RegC70);
2155                         ODM_SetBBReg(pDM_Odm, 0x85c, 0xFF000000, pDM_PSTable->Reg85C);
2156                         ODM_SetBBReg(pDM_Odm, 0xa74, 0xF000, pDM_PSTable->RegA74);
2157                         ODM_SetBBReg(pDM_Odm,0x818, BIT28, 0x0);
2158
2159                         if(pDM_Odm->SupportICType == ODM_RTL8723A)
2160                         {
2161                                 ODM_SetBBReg(pDM_Odm,0x874  , BIT5, 0x0); //Reg874[5]=1b'0
2162                         }
2163                         //ODM_RT_TRACE(pDM_Odm, COMP_BB_POWERSAVING, DBG_LOUD, (" RF_Normal"));
2164                 }
2165                 pDM_PSTable->PreRFState =pDM_PSTable->CurRFState;
2166         }
2167 }
2168
2169
2170 //3============================================================
2171 //3 RATR MASK
2172 //3============================================================
2173 //3============================================================
2174 //3 Rate Adaptive
2175 //3============================================================
2176
2177 void
2178 odm_RateAdaptiveMaskInit(
2179         PDM_ODM_T       pDM_Odm
2180         )
2181 {
2182         PODM_RATE_ADAPTIVE      pOdmRA = &pDM_Odm->RateAdaptive;
2183
2184         pOdmRA->Type = DM_Type_ByDriver;
2185         if (pOdmRA->Type == DM_Type_ByDriver)
2186                 pDM_Odm->bUseRAMask = _TRUE;
2187         else
2188                 pDM_Odm->bUseRAMask = _FALSE;
2189
2190         pOdmRA->RATRState = DM_RATR_STA_INIT;
2191         pOdmRA->HighRSSIThresh = 50;
2192         pOdmRA->LowRSSIThresh = 20;
2193 }
2194
2195 u4Byte ODM_Get_Rate_Bitmap(
2196         PDM_ODM_T       pDM_Odm,
2197         u4Byte          macid,
2198         u4Byte          ra_mask,
2199         u8              rssi_level)
2200 {
2201         PSTA_INFO_T     pEntry;
2202         u4Byte  rate_bitmap = 0x0fffffff;
2203         u8      WirelessMode;
2204         //u8    WirelessMode =*(pDM_Odm->pWirelessMode);
2205
2206
2207         pEntry = pDM_Odm->pODM_StaInfo[macid];
2208         if(!IS_STA_VALID(pEntry))
2209                 return ra_mask;
2210
2211         WirelessMode = pEntry->wireless_mode;
2212
2213         switch(WirelessMode)
2214         {
2215                 case ODM_WM_B:
2216                         if(ra_mask & 0x0000000c)                //11M or 5.5M enable
2217                                 rate_bitmap = 0x0000000d;
2218                         else
2219                                 rate_bitmap = 0x0000000f;
2220                         break;
2221
2222                 case (ODM_WM_A|ODM_WM_G):
2223                         if(rssi_level == DM_RATR_STA_HIGH)
2224                                 rate_bitmap = 0x00000f00;
2225                         else
2226                                 rate_bitmap = 0x00000ff0;
2227                         break;
2228
2229                 case (ODM_WM_B|ODM_WM_G):
2230                         if(rssi_level == DM_RATR_STA_HIGH)
2231                                 rate_bitmap = 0x00000f00;
2232                         else if(rssi_level == DM_RATR_STA_MIDDLE)
2233                                 rate_bitmap = 0x00000ff0;
2234                         else
2235                                 rate_bitmap = 0x00000ff5;
2236                         break;
2237
2238                 case (ODM_WM_B|ODM_WM_G|ODM_WM_N24G)    :
2239                 case (ODM_WM_A|ODM_WM_B|ODM_WM_G|ODM_WM_N24G)   :
2240                         {
2241                                 if (pDM_Odm->RFType == ODM_1T2R ||pDM_Odm->RFType == ODM_1T1R)
2242                                 {
2243                                         if(rssi_level == DM_RATR_STA_HIGH)
2244                                         {
2245                                                 rate_bitmap = 0x000f0000;
2246                                         }
2247                                         else if(rssi_level == DM_RATR_STA_MIDDLE)
2248                                         {
2249                                                 rate_bitmap = 0x000ff000;
2250                                         }
2251                                         else{
2252                                                 if (*(pDM_Odm->pBandWidth) == ODM_BW40M)
2253                                                         rate_bitmap = 0x000ff015;
2254                                                 else
2255                                                         rate_bitmap = 0x000ff005;
2256                                         }
2257                                 }
2258                                 else
2259                                 {
2260                                         if(rssi_level == DM_RATR_STA_HIGH)
2261                                         {
2262                                                 rate_bitmap = 0x0f8f0000;
2263                                         }
2264                                         else if(rssi_level == DM_RATR_STA_MIDDLE)
2265                                         {
2266                                                 rate_bitmap = 0x0f8ff000;
2267                                         }
2268                                         else
2269                                         {
2270                                                 if (*(pDM_Odm->pBandWidth) == ODM_BW40M)
2271                                                         rate_bitmap = 0x0f8ff015;
2272                                                 else
2273                                                         rate_bitmap = 0x0f8ff005;
2274                                         }
2275                                 }
2276                         }
2277                         break;
2278                 default:
2279                 //case WIRELESS_11_24N:
2280                 //case WIRELESS_11_5N:
2281                         if(pDM_Odm->RFType == RF_1T2R)
2282                                 rate_bitmap = 0x000fffff;
2283                         else
2284                                 rate_bitmap = 0x0fffffff;
2285                         break;
2286
2287         }
2288
2289         //printk("%s ==> rssi_level:0x%02x, WirelessMode:0x%02x, rate_bitmap:0x%08x \n",__FUNCTION__,rssi_level,WirelessMode,rate_bitmap);
2290         ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, (" ==> rssi_level:0x%02x, WirelessMode:0x%02x, rate_bitmap:0x%08x \n",rssi_level,WirelessMode,rate_bitmap));
2291
2292         return rate_bitmap;
2293
2294 }
2295
2296 /*-----------------------------------------------------------------------------
2297  * Function:    odm_RefreshRateAdaptiveMask()
2298  *
2299  * Overview:    Update rate table mask according to rssi
2300  *
2301  * Input:               NONE
2302  *
2303  * Output:              NONE
2304  *
2305  * Return:              NONE
2306  *
2307  * Revised History:
2308  *      When            Who             Remark
2309  *      05/27/2009      hpfan   Create Version 0.
2310  *
2311  *---------------------------------------------------------------------------*/
2312 void
2313 odm_RefreshRateAdaptiveMask(
2314                 PDM_ODM_T               pDM_Odm
2315         )
2316 {
2317         if (!(pDM_Odm->SupportAbility & ODM_BB_RA_MASK))
2318                 return;
2319         //
2320         // 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate
2321         // at the same time. In the stage2/3, we need to prive universal interface and merge all
2322         // HW dynamic mechanism.
2323         //
2324         switch  (pDM_Odm->SupportPlatform)
2325         {
2326                 case    ODM_MP:
2327                         odm_RefreshRateAdaptiveMaskMP(pDM_Odm);
2328                         break;
2329
2330                 case    ODM_CE:
2331                         odm_RefreshRateAdaptiveMaskCE(pDM_Odm);
2332                         break;
2333
2334                 case    ODM_AP:
2335                 case    ODM_ADSL:
2336                         odm_RefreshRateAdaptiveMaskAPADSL(pDM_Odm);
2337                         break;
2338         }
2339
2340 }
2341
2342 void
2343 odm_RefreshRateAdaptiveMaskMP(
2344                 PDM_ODM_T               pDM_Odm
2345         )
2346 {
2347 }
2348
2349
2350 void
2351 odm_RefreshRateAdaptiveMaskCE(
2352                 PDM_ODM_T               pDM_Odm
2353         )
2354 {
2355         u8      i;
2356         PADAPTER        pAdapter         =  pDM_Odm->Adapter;
2357
2358         if(pAdapter->bDriverStopped)
2359         {
2360                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_TRACE, ("<---- odm_RefreshRateAdaptiveMask(): driver is going to unload\n"));
2361                 return;
2362         }
2363
2364         if(!pDM_Odm->bUseRAMask)
2365         {
2366                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("<---- odm_RefreshRateAdaptiveMask(): driver does not control rate adaptive mask\n"));
2367                 return;
2368         }
2369
2370         //printk("==> %s \n",__FUNCTION__);
2371
2372         for(i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++){
2373                 PSTA_INFO_T pstat = pDM_Odm->pODM_StaInfo[i];
2374                 if(IS_STA_VALID(pstat) ) {
2375                         if( TRUE == ODM_RAStateCheck(pDM_Odm, pstat->rssi_stat.UndecoratedSmoothedPWDB, FALSE , &pstat->rssi_level) )
2376                         {
2377                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI:%d, RSSI_LEVEL:%d\n", pstat->rssi_stat.UndecoratedSmoothedPWDB, pstat->rssi_level));
2378                                 //printk("RSSI:%d, RSSI_LEVEL:%d\n", pstat->rssi_stat.UndecoratedSmoothedPWDB, pstat->rssi_level);
2379                                 rtw_hal_update_ra_mask(pstat, pstat->rssi_level);
2380                         }
2381
2382                 }
2383         }
2384
2385 }
2386
2387 void
2388 odm_RefreshRateAdaptiveMaskAPADSL(
2389                 PDM_ODM_T               pDM_Odm
2390         )
2391 {
2392 }
2393
2394 // Return Value: bool
2395 // - TRUE: RATRState is changed.
2396 bool
2397 ODM_RAStateCheck(
2398                 PDM_ODM_T               pDM_Odm,
2399                 s4Byte                  RSSI,
2400                 bool                    bForceUpdate,
2401                 u8 *                    pRATRState
2402         )
2403 {
2404         PODM_RATE_ADAPTIVE pRA = &pDM_Odm->RateAdaptive;
2405         const u8 GoUpGap = 5;
2406         u8 HighRSSIThreshForRA = pRA->HighRSSIThresh;
2407         u8 LowRSSIThreshForRA = pRA->LowRSSIThresh;
2408         u8 RATRState;
2409
2410         // Threshold Adjustment:
2411         // when RSSI state trends to go up one or two levels, make sure RSSI is high enough.
2412         // Here GoUpGap is added to solve the boundary's level alternation issue.
2413         switch (*pRATRState)
2414         {
2415                 case DM_RATR_STA_INIT:
2416                 case DM_RATR_STA_HIGH:
2417                         break;
2418
2419                 case DM_RATR_STA_MIDDLE:
2420                         HighRSSIThreshForRA += GoUpGap;
2421                         break;
2422
2423                 case DM_RATR_STA_LOW:
2424                         HighRSSIThreshForRA += GoUpGap;
2425                         LowRSSIThreshForRA += GoUpGap;
2426                         break;
2427
2428                 default:
2429                         ODM_RT_ASSERT(pDM_Odm, FALSE, ("wrong rssi level setting %d !", *pRATRState) );
2430                         break;
2431         }
2432
2433         // Decide RATRState by RSSI.
2434         if(RSSI > HighRSSIThreshForRA)
2435                 RATRState = DM_RATR_STA_HIGH;
2436         else if(RSSI > LowRSSIThreshForRA)
2437                 RATRState = DM_RATR_STA_MIDDLE;
2438         else
2439                 RATRState = DM_RATR_STA_LOW;
2440         //printk("==>%s,RATRState:0x%02x ,RSSI:%d \n",__FUNCTION__,RATRState,RSSI);
2441
2442         if( *pRATRState!=RATRState || bForceUpdate)
2443         {
2444                 ODM_RT_TRACE( pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI Level %d -> %d\n", *pRATRState, RATRState) );
2445                 *pRATRState = RATRState;
2446                 return TRUE;
2447         }
2448
2449         return FALSE;
2450 }
2451
2452
2453 //============================================================
2454
2455 //3============================================================
2456 //3 Dynamic Tx Power
2457 //3============================================================
2458
2459 void
2460 odm_DynamicTxPowerInit(
2461                 PDM_ODM_T               pDM_Odm
2462         )
2463 {
2464         PADAPTER        Adapter = pDM_Odm->Adapter;
2465         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
2466         struct dm_priv  *pdmpriv = &pHalData->dmpriv;
2467         pdmpriv->bDynamicTxPowerEnable = _FALSE;
2468
2469         #if (RTL8192C_SUPPORT==1)
2470
2471         #ifdef CONFIG_INTEL_PROXIM
2472         if((pHalData->BoardType == BOARD_USB_High_PA)||(Adapter->proximity.proxim_support==_TRUE))
2473         #else
2474         if(pHalData->BoardType == BOARD_USB_High_PA)
2475         #endif
2476
2477         {
2478                 //odm_SavePowerIndex(Adapter);
2479                 odm_DynamicTxPowerSavePowerIndex(pDM_Odm);
2480                 pdmpriv->bDynamicTxPowerEnable = _TRUE;
2481         }
2482         else
2483         #endif
2484
2485         pdmpriv->LastDTPLvl = TxHighPwrLevel_Normal;
2486         pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
2487 }
2488
2489 void
2490 odm_DynamicTxPowerSavePowerIndex(
2491                 PDM_ODM_T               pDM_Odm
2492         )
2493 {
2494         u8              index;
2495         u4Byte          Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a};
2496
2497         PADAPTER        Adapter = pDM_Odm->Adapter;
2498         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
2499         struct dm_priv  *pdmpriv = &pHalData->dmpriv;
2500         for(index = 0; index< 6; index++)
2501                 pdmpriv->PowerIndex_backup[index] = rtw_read8(Adapter, Power_Index_REG[index]);
2502 }
2503
2504 void
2505 odm_DynamicTxPowerRestorePowerIndex(
2506                 PDM_ODM_T               pDM_Odm
2507         )
2508 {
2509         u8                      index;
2510         PADAPTER                Adapter = pDM_Odm->Adapter;
2511
2512         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
2513         u4Byte                  Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a};
2514         struct dm_priv  *pdmpriv = &pHalData->dmpriv;
2515         for(index = 0; index< 6; index++)
2516                 rtw_write8(Adapter, Power_Index_REG[index], pdmpriv->PowerIndex_backup[index]);
2517 }
2518
2519 void
2520 odm_DynamicTxPowerWritePowerIndex(
2521         PDM_ODM_T       pDM_Odm,
2522         u8              Value)
2523 {
2524
2525         u8                      index;
2526         u4Byte                  Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a};
2527
2528         for(index = 0; index< 6; index++)
2529                 //PlatformEFIOWrite1Byte(Adapter, Power_Index_REG[index], Value);
2530                 ODM_Write1Byte(pDM_Odm, Power_Index_REG[index], Value);
2531
2532 }
2533
2534
2535 void
2536 odm_DynamicTxPower(
2537                 PDM_ODM_T               pDM_Odm
2538         )
2539 {
2540         //
2541         // For AP/ADSL use prtl8192cd_priv
2542         // For CE/NIC use PADAPTER
2543         //
2544         //PADAPTER              pAdapter = pDM_Odm->Adapter;
2545 //      prtl8192cd_priv priv            = pDM_Odm->priv;
2546
2547         if (!(pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_TXPWR))
2548                 return;
2549
2550         // 2012/01/12 MH According to Luke's suggestion, only high power will support the feature.
2551         if (pDM_Odm->ExtPA == FALSE)
2552                 return;
2553
2554
2555         //
2556         // 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate
2557         // at the same time. In the stage2/3, we need to prive universal interface and merge all
2558         // HW dynamic mechanism.
2559         //
2560         switch  (pDM_Odm->SupportPlatform)
2561         {
2562                 case    ODM_MP:
2563                 case    ODM_CE:
2564                         odm_DynamicTxPowerNIC(pDM_Odm);
2565                         break;
2566                 case    ODM_AP:
2567                         odm_DynamicTxPowerAP(pDM_Odm);
2568                         break;
2569
2570                 case    ODM_ADSL:
2571                         //odm_DIGAP(pDM_Odm);
2572                         break;
2573         }
2574
2575
2576 }
2577
2578
2579 void
2580 odm_DynamicTxPowerNIC(
2581                 PDM_ODM_T               pDM_Odm
2582         )
2583 {
2584         if (!(pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_TXPWR))
2585                 return;
2586
2587         if(pDM_Odm->SupportICType == ODM_RTL8192C)
2588         {
2589                 odm_DynamicTxPower_92C(pDM_Odm);
2590         }
2591         else if(pDM_Odm->SupportICType == ODM_RTL8192D)
2592         {
2593                 odm_DynamicTxPower_92D(pDM_Odm);
2594         }
2595         else if (pDM_Odm->SupportICType & ODM_RTL8188E)
2596         {
2597                 // Add Later.
2598         }
2599         else if (pDM_Odm->SupportICType == ODM_RTL8188E)
2600         {
2601                 // ???
2602                 // This part need to be redefined.
2603         }
2604 }
2605
2606 void
2607 odm_DynamicTxPowerAP(
2608                 PDM_ODM_T               pDM_Odm
2609
2610         )
2611 {
2612 }
2613
2614
2615 void
2616 odm_DynamicTxPower_92C(
2617         PDM_ODM_T       pDM_Odm
2618         )
2619 {
2620         #if (RTL8192C_SUPPORT==1)
2621         PADAPTER Adapter = pDM_Odm->Adapter;
2622         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
2623         struct dm_priv  *pdmpriv = &pHalData->dmpriv;
2624         struct mlme_priv        *pmlmepriv = &(Adapter->mlmepriv);
2625         struct mlme_ext_priv    *pmlmeext = &Adapter->mlmeextpriv;
2626         int     UndecoratedSmoothedPWDB;
2627
2628         if(!pdmpriv->bDynamicTxPowerEnable)
2629                 return;
2630
2631 #ifdef CONFIG_INTEL_PROXIM
2632         if(Adapter->proximity.proxim_on== _TRUE){
2633                 struct proximity_priv *prox_priv=Adapter->proximity.proximity_priv;
2634                 // Intel set fixed tx power
2635                 printk("\n %s  Adapter->proximity.proxim_on=%d prox_priv->proxim_modeinfo->power_output=%d \n",__FUNCTION__,Adapter->proximity.proxim_on,prox_priv->proxim_modeinfo->power_output);
2636                 if(prox_priv!=NULL){
2637                         if(prox_priv->proxim_modeinfo->power_output> 0)
2638                         {
2639                                 switch(prox_priv->proxim_modeinfo->power_output)
2640                                 {
2641                                         case 1:
2642                                                 pdmpriv->DynamicTxHighPowerLvl  = TxHighPwrLevel_100;
2643                                                 printk("TxHighPwrLevel_100\n");
2644                                                 break;
2645                                         case 2:
2646                                                 pdmpriv->DynamicTxHighPowerLvl  = TxHighPwrLevel_70;
2647                                                 printk("TxHighPwrLevel_70\n");
2648                                                 break;
2649                                         case 3:
2650                                                 pdmpriv->DynamicTxHighPowerLvl  = TxHighPwrLevel_50;
2651                                                 printk("TxHighPwrLevel_50\n");
2652                                                 break;
2653                                         case 4:
2654                                                 pdmpriv->DynamicTxHighPowerLvl  = TxHighPwrLevel_35;
2655                                                 printk("TxHighPwrLevel_35\n");
2656                                                 break;
2657                                         case 5:
2658                                                 pdmpriv->DynamicTxHighPowerLvl  = TxHighPwrLevel_15;
2659                                                 printk("TxHighPwrLevel_15\n");
2660                                                 break;
2661                                         default:
2662                                                 pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_100;
2663                                                 printk("TxHighPwrLevel_100\n");
2664                                                 break;
2665                                 }
2666                         }
2667                 }
2668         }
2669         else
2670 #endif
2671         {
2672                 // STA not connected and AP not connected
2673                 if((check_fwstate(pmlmepriv, _FW_LINKED) != _TRUE) &&
2674                         (pdmpriv->EntryMinUndecoratedSmoothedPWDB == 0))
2675                 {
2676                         //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("Not connected to any \n"));
2677                         pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
2678
2679                         //the LastDTPlvl should reset when disconnect,
2680                         //otherwise the tx power level wouldn't change when disconnect and connect again.
2681                         // Maddest 20091220.
2682                         pdmpriv->LastDTPLvl=TxHighPwrLevel_Normal;
2683                         return;
2684                 }
2685
2686                 if(check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)       // Default port
2687                 {
2688                         UndecoratedSmoothedPWDB = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
2689                 }
2690                 else // associated entry pwdb
2691                 {
2692                         UndecoratedSmoothedPWDB = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
2693                         //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("AP Ext Port PWDB = 0x%x \n", UndecoratedSmoothedPWDB));
2694                 }
2695
2696                 if(UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL2)
2697                 {
2698                         pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Level2;
2699                         //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x0)\n"));
2700                 }
2701                 else if((UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL2-3)) &&
2702                         (UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL1) )
2703                 {
2704                         pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Level1;
2705                         //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x10)\n"));
2706                 }
2707                 else if(UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL1-5))
2708                 {
2709                         pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
2710                         //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Normal\n"));
2711                 }
2712         }
2713         if( (pdmpriv->DynamicTxHighPowerLvl != pdmpriv->LastDTPLvl) )
2714         {
2715                 PHY_SetTxPowerLevel8192C(Adapter, pHalData->CurrentChannel);
2716                 if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Normal) // HP1 -> Normal  or HP2 -> Normal
2717                         odm_DynamicTxPowerRestorePowerIndex(pDM_Odm);
2718                 else if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1)
2719                         odm_DynamicTxPowerWritePowerIndex(pDM_Odm, 0x14);
2720                 else if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2)
2721                         odm_DynamicTxPowerWritePowerIndex(pDM_Odm, 0x10);
2722         }
2723         pdmpriv->LastDTPLvl = pdmpriv->DynamicTxHighPowerLvl;
2724         #endif
2725 }
2726
2727
2728 void
2729 odm_DynamicTxPower_92D(
2730         PDM_ODM_T       pDM_Odm
2731         )
2732 {
2733 #if (RTL8192D_SUPPORT==1)
2734         PADAPTER Adapter = pDM_Odm->Adapter;
2735         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
2736         struct mlme_priv        *pmlmepriv = &(Adapter->mlmepriv);
2737
2738         struct dm_priv  *pdmpriv = &pHalData->dmpriv;
2739         DM_ODM_T                *podmpriv = &pHalData->odmpriv;
2740         int     UndecoratedSmoothedPWDB;
2741         #if (RTL8192D_EASY_SMART_CONCURRENT == 1)
2742         PADAPTER        BuddyAdapter = Adapter->BuddyAdapter;
2743         bool            bGetValueFromBuddyAdapter = DualMacGetParameterFromBuddyAdapter(Adapter);
2744         u8              HighPowerLvlBackForMac0 = TxHighPwrLevel_Level1;
2745         #endif
2746
2747         // If dynamic high power is disabled.
2748         if( (pdmpriv->bDynamicTxPowerEnable != _TRUE) ||
2749                 (!(podmpriv->SupportAbility& ODM_BB_DYNAMIC_TXPWR)) )
2750         {
2751                 pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
2752                 return;
2753         }
2754
2755         // STA not connected and AP not connected
2756         if((check_fwstate(pmlmepriv, _FW_LINKED) != _TRUE) &&
2757                 (pdmpriv->EntryMinUndecoratedSmoothedPWDB == 0))
2758         {
2759                 //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("Not connected to any \n"));
2760                 pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
2761                 //the LastDTPlvl should reset when disconnect,
2762                 //otherwise the tx power level wouldn't change when disconnect and connect again.
2763                 // Maddest 20091220.
2764                 pdmpriv->LastDTPLvl=TxHighPwrLevel_Normal;
2765                 return;
2766         }
2767
2768         if(check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)       // Default port
2769         {
2770                 UndecoratedSmoothedPWDB = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
2771         }
2772         else // associated entry pwdb
2773         {
2774                 UndecoratedSmoothedPWDB = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
2775                 //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("AP Ext Port PWDB = 0x%x \n", UndecoratedSmoothedPWDB));
2776         }
2777 #if TX_POWER_FOR_5G_BAND == 1
2778         if(pHalData->CurrentBandType92D == BAND_ON_5G){
2779                 if(UndecoratedSmoothedPWDB >= 0x33)
2780                 {
2781                         pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Level2;
2782                         //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("5G:TxHighPwrLevel_Level2 (TxPwr=0x0)\n"));
2783                 }
2784                 else if((UndecoratedSmoothedPWDB <0x33) &&
2785                         (UndecoratedSmoothedPWDB >= 0x2b) )
2786                 {
2787                         pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Level1;
2788                         //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("5G:TxHighPwrLevel_Level1 (TxPwr=0x10)\n"));
2789                 }
2790                 else if(UndecoratedSmoothedPWDB < 0x2b)
2791                 {
2792                         pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
2793                         //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("5G:TxHighPwrLevel_Normal\n"));
2794                 }
2795         }
2796         else
2797 #endif
2798         {
2799                 if(UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL2)
2800                 {
2801                         pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Level2;
2802                         //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x0)\n"));
2803                 }
2804                 else if((UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL2-3)) &&
2805                         (UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL1) )
2806                 {
2807                         pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Level1;
2808                         //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x10)\n"));
2809                 }
2810                 else if(UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL1-5))
2811                 {
2812                         pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
2813                         //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Normal\n"));
2814                 }
2815         }
2816 #if (RTL8192D_EASY_SMART_CONCURRENT == 1)
2817         if(bGetValueFromBuddyAdapter)
2818         {
2819                 //ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() mac 0 for mac 1 \n"));
2820                 if(Adapter->DualMacDMSPControl.bChangeTxHighPowerLvlForAnotherMacOfDMSP)
2821                 {
2822                         //ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() change value \n"));
2823                         HighPowerLvlBackForMac0 = pHalData->DynamicTxHighPowerLvl;
2824                         pHalData->DynamicTxHighPowerLvl = Adapter->DualMacDMSPControl.CurTxHighLvlForAnotherMacOfDMSP;
2825                         PHY_SetTxPowerLevel8192D(Adapter, pHalData->CurrentChannel);
2826                         pHalData->DynamicTxHighPowerLvl = HighPowerLvlBackForMac0;
2827                         Adapter->DualMacDMSPControl.bChangeTxHighPowerLvlForAnotherMacOfDMSP = _FALSE;
2828                 }
2829         }
2830 #endif
2831
2832         if( (pdmpriv->DynamicTxHighPowerLvl != pdmpriv->LastDTPLvl) )
2833         {
2834                 //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("PHY_SetTxPowerLevel8192S() Channel = %d \n" , pHalData->CurrentChannel));
2835 #if (RTL8192D_EASY_SMART_CONCURRENT == 1)
2836                 if(BuddyAdapter == NULL)
2837                 {
2838                         //ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() BuddyAdapter == NULL case \n"));
2839                         if(!Adapter->bSlaveOfDMSP)
2840                         {
2841                                 PHY_SetTxPowerLevel8192D(Adapter, pHalData->CurrentChannel);
2842                         }
2843                 }
2844                 else
2845                 {
2846                         if(pHalData->MacPhyMode92D == DUALMAC_SINGLEPHY)
2847                         {
2848                                 //ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() BuddyAdapter DMSP \n"));
2849                                 if(Adapter->bSlaveOfDMSP)
2850                                 {
2851                                         //ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() bslave case  \n"));
2852                                         BuddyAdapter->DualMacDMSPControl.bChangeTxHighPowerLvlForAnotherMacOfDMSP = _TRUE;
2853                                         BuddyAdapter->DualMacDMSPControl.CurTxHighLvlForAnotherMacOfDMSP = pHalData->DynamicTxHighPowerLvl;
2854                                 }
2855                                 else
2856                                 {
2857                                         //ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() master case  \n"));
2858                                         if(!bGetValueFromBuddyAdapter)
2859                                         {
2860                                                 //ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() mac 0 for mac 0 \n"));
2861                                                 PHY_SetTxPowerLevel8192D(Adapter, pHalData->CurrentChannel);
2862                                         }
2863                                 }
2864                         }
2865                         else
2866                         {
2867                                 //ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() BuddyAdapter DMDP\n"));
2868                                 PHY_SetTxPowerLevel8192D(Adapter, pHalData->CurrentChannel);
2869                         }
2870                 }
2871 #else
2872                 PHY_SetTxPowerLevel8192D(Adapter, pHalData->CurrentChannel);
2873 #endif
2874         }
2875         pdmpriv->LastDTPLvl = pdmpriv->DynamicTxHighPowerLvl;
2876 #endif
2877 }
2878
2879
2880 //3============================================================
2881 //3 RSSI Monitor
2882 //3============================================================
2883
2884 void
2885 odm_RSSIMonitorInit(
2886         PDM_ODM_T       pDM_Odm
2887         )
2888 {
2889 }
2890
2891 void
2892 odm_RSSIMonitorCheck(
2893                 PDM_ODM_T               pDM_Odm
2894         )
2895 {
2896         //
2897         // For AP/ADSL use prtl8192cd_priv
2898         // For CE/NIC use PADAPTER
2899         //
2900         PADAPTER                pAdapter = pDM_Odm->Adapter;
2901         prtl8192cd_priv priv            = pDM_Odm->priv;
2902
2903         if (!(pDM_Odm->SupportAbility & ODM_BB_RSSI_MONITOR))
2904                 return;
2905
2906         //
2907         // 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate
2908         // at the same time. In the stage2/3, we need to prive universal interface and merge all
2909         // HW dynamic mechanism.
2910         //
2911         switch  (pDM_Odm->SupportPlatform)
2912         {
2913                 case    ODM_MP:
2914                         odm_RSSIMonitorCheckMP(pDM_Odm);
2915                         break;
2916
2917                 case    ODM_CE:
2918                         odm_RSSIMonitorCheckCE(pDM_Odm);
2919                         break;
2920
2921                 case    ODM_AP:
2922                         odm_RSSIMonitorCheckAP(pDM_Odm);
2923                         break;
2924
2925                 case    ODM_ADSL:
2926                         //odm_DIGAP(pDM_Odm);
2927                         break;
2928         }
2929
2930 }       // odm_RSSIMonitorCheck
2931
2932
2933 void
2934 odm_RSSIMonitorCheckMP(
2935         PDM_ODM_T       pDM_Odm
2936         )
2937 {
2938 }
2939
2940 //
2941 //sherry move from DUSC to here 20110517
2942 //
2943 static void
2944 FindMinimumRSSI_Dmsp(
2945         PADAPTER        pAdapter
2946 )
2947 {
2948 }
2949
2950 static void
2951 FindMinimumRSSI(
2952         PADAPTER        pAdapter
2953         )
2954 {
2955         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
2956         struct dm_priv  *pdmpriv = &pHalData->dmpriv;
2957         PDM_ODM_T               pDM_Odm = &(pHalData->odmpriv);
2958
2959         //1 1.Determine the minimum RSSI
2960
2961         if((pDM_Odm->bLinked != _TRUE) &&
2962                 (pdmpriv->EntryMinUndecoratedSmoothedPWDB == 0))
2963         {
2964                 pdmpriv->MinUndecoratedPWDBForDM = 0;
2965                 //ODM_RT_TRACE(pDM_Odm,COMP_BB_POWERSAVING, DBG_LOUD, ("Not connected to any \n"));
2966         }
2967         else
2968         {
2969                 pdmpriv->MinUndecoratedPWDBForDM = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
2970         }
2971
2972         //DBG_8723A("%s=>MinUndecoratedPWDBForDM(%d)\n",__FUNCTION__,pdmpriv->MinUndecoratedPWDBForDM);
2973         //ODM_RT_TRACE(pDM_Odm,COMP_DIG, DBG_LOUD, ("MinUndecoratedPWDBForDM =%d\n",pHalData->MinUndecoratedPWDBForDM));
2974 }
2975
2976 void
2977 odm_RSSIMonitorCheckCE(
2978                 PDM_ODM_T               pDM_Odm
2979         )
2980 {
2981         PADAPTER        Adapter = pDM_Odm->Adapter;
2982         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
2983         struct dm_priv  *pdmpriv = &pHalData->dmpriv;
2984         int     i;
2985         int     tmpEntryMaxPWDB=0, tmpEntryMinPWDB=0xff;
2986         u8      sta_cnt=0;
2987         u32 PWDB_rssi[NUM_STA]={0};//[0~15]:MACID, [16~31]:PWDB_rssi
2988
2989         if(pDM_Odm->bLinked != _TRUE)
2990                 return;
2991
2992         //if(check_fwstate(&Adapter->mlmepriv, WIFI_AP_STATE|WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE) == _TRUE)
2993         {
2994                 #if 1
2995                 struct sta_info *psta;
2996
2997                 for(i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++) {
2998                         if (IS_STA_VALID(psta = pDM_Odm->pODM_StaInfo[i]))
2999                         {
3000                                         if(psta->rssi_stat.UndecoratedSmoothedPWDB < tmpEntryMinPWDB)
3001                                                 tmpEntryMinPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB;
3002
3003                                         if(psta->rssi_stat.UndecoratedSmoothedPWDB > tmpEntryMaxPWDB)
3004                                                 tmpEntryMaxPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB;
3005
3006                                         if(psta->rssi_stat.UndecoratedSmoothedPWDB != (-1)) {
3007                                                 #if(RTL8192D_SUPPORT==1)
3008                                                 PWDB_rssi[sta_cnt++] = (psta->mac_id | (psta->rssi_stat.UndecoratedSmoothedPWDB<<16) | ((Adapter->stapriv.asoc_sta_count+1) << 8));
3009                                                 #else
3010                                                 PWDB_rssi[sta_cnt++] = (psta->mac_id | (psta->rssi_stat.UndecoratedSmoothedPWDB<<16) );
3011                                                 #endif
3012                                         }
3013                         }
3014                 }
3015                 #else
3016                 _irqL irqL;
3017                 _list   *plist, *phead;
3018                 struct sta_info *psta;
3019                 struct sta_priv *pstapriv = &Adapter->stapriv;
3020                 u8 bcast_addr[ETH_ALEN]= {0xff,0xff,0xff,0xff,0xff,0xff};
3021
3022                 _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
3023
3024                 for(i=0; i< NUM_STA; i++)
3025                 {
3026                         phead = &(pstapriv->sta_hash[i]);
3027                         plist = phead->next;
3028
3029                         while ((rtw_end_of_queue_search(phead, plist)) == _FALSE)
3030                         {
3031                                 psta = container_of(plist, struct sta_info, hash_list);
3032
3033                                 plist = plist->next;
3034
3035                                 if (!memcmp(psta->hwaddr, bcast_addr, ETH_ALEN) ||
3036                                     !memcmp(psta->hwaddr, myid(&Adapter->eeprompriv), ETH_ALEN))
3037                                         continue;
3038
3039                                 if(psta->state & WIFI_ASOC_STATE)
3040                                 {
3041
3042                                         if(psta->rssi_stat.UndecoratedSmoothedPWDB < tmpEntryMinPWDB)
3043                                                 tmpEntryMinPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB;
3044
3045                                         if(psta->rssi_stat.UndecoratedSmoothedPWDB > tmpEntryMaxPWDB)
3046                                                 tmpEntryMaxPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB;
3047
3048                                         if(psta->rssi_stat.UndecoratedSmoothedPWDB != (-1)){
3049                                                 //printk("%s==> mac_id(%d),rssi(%d)\n",__FUNCTION__,psta->mac_id,psta->rssi_stat.UndecoratedSmoothedPWDB);
3050                                                 #if(RTL8192D_SUPPORT==1)
3051                                                 PWDB_rssi[sta_cnt++] = (psta->mac_id | (psta->rssi_stat.UndecoratedSmoothedPWDB<<16) | ((Adapter->stapriv.asoc_sta_count+1) << 8));
3052                                                 #else
3053                                                 PWDB_rssi[sta_cnt++] = (psta->mac_id | (psta->rssi_stat.UndecoratedSmoothedPWDB<<16) );
3054                                                 #endif
3055                                         }
3056                                 }
3057
3058                         }
3059
3060                 }
3061
3062                 _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
3063                 #endif
3064
3065                 //printk("%s==> sta_cnt(%d)\n",__FUNCTION__,sta_cnt);
3066
3067                 for(i=0; i< sta_cnt; i++)
3068                 {
3069                         if(PWDB_rssi[i] != (0)){
3070                                 if(pHalData->fw_ractrl == _TRUE)// Report every sta's RSSI to FW
3071                                 {
3072                                         #if(RTL8192D_SUPPORT==1)
3073                                         FillH2CCmd92D(Adapter, H2C_RSSI_REPORT, 3, (u8 *)(&PWDB_rssi[i]));
3074                                         #elif((RTL8192C_SUPPORT==1)||(RTL8723A_SUPPORT==1))
3075                                         rtl8192c_set_rssi_cmd(Adapter, (u8*)&PWDB_rssi[i]);
3076                                         #endif
3077                                 }
3078                                 else{
3079                                         #if((RTL8188E_SUPPORT==1)&&(RATE_ADAPTIVE_SUPPORT == 1))
3080                                         ODM_RA_SetRSSI_8188E(
3081                                         &(pHalData->odmpriv), (PWDB_rssi[i]&0xFF), (u8)((PWDB_rssi[i]>>16) & 0xFF));
3082                                         #endif
3083                                 }
3084                         }
3085                 }
3086         }
3087
3088         if(tmpEntryMaxPWDB != 0)        // If associated entry is found
3089         {
3090                 pdmpriv->EntryMaxUndecoratedSmoothedPWDB = tmpEntryMaxPWDB;
3091         }
3092         else
3093         {
3094                 pdmpriv->EntryMaxUndecoratedSmoothedPWDB = 0;
3095         }
3096
3097         if(tmpEntryMinPWDB != 0xff) // If associated entry is found
3098         {
3099                 pdmpriv->EntryMinUndecoratedSmoothedPWDB = tmpEntryMinPWDB;
3100         }
3101         else
3102         {
3103                 pdmpriv->EntryMinUndecoratedSmoothedPWDB = 0;
3104         }
3105
3106         FindMinimumRSSI(Adapter);//get pdmpriv->MinUndecoratedPWDBForDM
3107
3108         #if(RTL8192D_SUPPORT==1)
3109         FindMinimumRSSI_Dmsp(Adapter);
3110         #endif
3111
3112         ODM_CmnInfoUpdate(&pHalData->odmpriv ,ODM_CMNINFO_RSSI_MIN, pdmpriv->MinUndecoratedPWDBForDM);
3113 }
3114 void
3115 odm_RSSIMonitorCheckAP(
3116                 PDM_ODM_T               pDM_Odm
3117         )
3118 {
3119 }
3120
3121
3122 void
3123 ODM_InitAllTimers(
3124  PDM_ODM_T      pDM_Odm
3125         )
3126 {
3127         ODM_InitializeTimer(pDM_Odm,&pDM_Odm->DM_SWAT_Table.SwAntennaSwitchTimer,
3128                 (RT_TIMER_CALL_BACK)odm_SwAntDivChkAntSwitchCallback, NULL, "SwAntennaSwitchTimer");
3129 }
3130
3131 void
3132 ODM_CancelAllTimers(
3133  PDM_ODM_T      pDM_Odm
3134         )
3135 {
3136         ODM_CancelTimer(pDM_Odm,&pDM_Odm->DM_SWAT_Table.SwAntennaSwitchTimer);
3137 }
3138
3139
3140 void
3141 ODM_ReleaseAllTimers(
3142  PDM_ODM_T      pDM_Odm
3143         )
3144 {
3145         ODM_ReleaseTimer(pDM_Odm,&pDM_Odm->DM_SWAT_Table.SwAntennaSwitchTimer);
3146
3147 #if (RTL8188E_SUPPORT == 1)
3148         ODM_ReleaseTimer(pDM_Odm,&pDM_Odm->FastAntTrainingTimer);
3149 #endif
3150
3151 }
3152
3153
3154
3155 //#endif
3156 //3============================================================
3157 //3 Tx Power Tracking
3158 //3============================================================
3159
3160 void
3161 odm_TXPowerTrackingInit(
3162         PDM_ODM_T       pDM_Odm
3163         )
3164 {
3165         odm_TXPowerTrackingThermalMeterInit(pDM_Odm);
3166 }
3167
3168
3169 void
3170 odm_TXPowerTrackingThermalMeterInit(
3171         PDM_ODM_T       pDM_Odm
3172         )
3173 {
3174         #ifdef CONFIG_RTL8188E
3175         {
3176                 pDM_Odm->RFCalibrateInfo.bTXPowerTracking = _TRUE;
3177                 pDM_Odm->RFCalibrateInfo.TXPowercount = 0;
3178                 pDM_Odm->RFCalibrateInfo.bTXPowerTrackingInit = _FALSE;
3179                 pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = _TRUE;
3180                 MSG_8723A("pDM_Odm TxPowerTrackControl = %d\n", pDM_Odm->RFCalibrateInfo.TxPowerTrackControl);
3181         }
3182         #else
3183         {
3184                 PADAPTER                Adapter = pDM_Odm->Adapter;
3185                 HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
3186                 struct dm_priv  *pdmpriv = &pHalData->dmpriv;
3187
3188                 pdmpriv->bTXPowerTracking = _TRUE;
3189                 pdmpriv->TXPowercount = 0;
3190                 pdmpriv->bTXPowerTrackingInit = _FALSE;
3191                 pdmpriv->TxPowerTrackControl = _TRUE;
3192                 MSG_8723A("pdmpriv->TxPowerTrackControl = %d\n", pdmpriv->TxPowerTrackControl);
3193
3194         }
3195         #endif//endif (CONFIG_RTL8188E==1)
3196
3197     pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = TRUE;
3198 }
3199
3200
3201 void
3202 ODM_TXPowerTrackingCheck(
3203                 PDM_ODM_T               pDM_Odm
3204         )
3205 {
3206         //
3207         // For AP/ADSL use prtl8192cd_priv
3208         // For CE/NIC use PADAPTER
3209         //
3210         PADAPTER                pAdapter = pDM_Odm->Adapter;
3211         prtl8192cd_priv priv            = pDM_Odm->priv;
3212
3213         //if (!(pDM_Odm->SupportAbility & ODM_RF_TX_PWR_TRACK))
3214                 //return;
3215
3216         //
3217         // 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate
3218         // at the same time. In the stage2/3, we need to prive universal interface and merge all
3219         // HW dynamic mechanism.
3220         //
3221         switch  (pDM_Odm->SupportPlatform)
3222         {
3223                 case    ODM_MP:
3224                         odm_TXPowerTrackingCheckMP(pDM_Odm);
3225                         break;
3226
3227                 case    ODM_CE:
3228                         odm_TXPowerTrackingCheckCE(pDM_Odm);
3229                         break;
3230
3231                 case    ODM_AP:
3232                         odm_TXPowerTrackingCheckAP(pDM_Odm);
3233                         break;
3234
3235                 case    ODM_ADSL:
3236                         //odm_DIGAP(pDM_Odm);
3237                         break;
3238         }
3239
3240 }
3241
3242 void
3243 odm_TXPowerTrackingCheckCE(
3244                 PDM_ODM_T               pDM_Odm
3245         )
3246 {
3247         PADAPTER        Adapter = pDM_Odm->Adapter;
3248         #if( (RTL8192C_SUPPORT==1) ||  (RTL8723A_SUPPORT==1) )
3249         rtl8192c_odm_CheckTXPowerTracking(Adapter);
3250         #endif
3251
3252         #if (RTL8192D_SUPPORT==1)
3253         #if (RTL8192D_EASY_SMART_CONCURRENT == 1)
3254         if(!Adapter->bSlaveOfDMSP)
3255         #endif
3256                 rtl8192d_odm_CheckTXPowerTracking(Adapter);
3257         #endif
3258         #if(RTL8188E_SUPPORT==1)
3259
3260         //if(!pMgntInfo->bTXPowerTracking /*|| (!pdmpriv->TxPowerTrackControl && pdmpriv->bAPKdone)*/)
3261         if(!(pDM_Odm->SupportAbility & ODM_RF_TX_PWR_TRACK))
3262         {
3263                 return;
3264         }
3265
3266         if(!pDM_Odm->RFCalibrateInfo.TM_Trigger)                //at least delay 1 sec
3267         {
3268                 //pHalData->TxPowerCheckCnt++;  //cosa add for debug
3269                 //ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_T_METER, bRFRegOffsetMask, 0x60);
3270                 PHY_SetRFReg(Adapter, RF_PATH_A, RF_T_METER_88E, BIT17 | BIT16, 0x03);
3271                 //DBG_8723A("Trigger 92C Thermal Meter!!\n");
3272
3273                 pDM_Odm->RFCalibrateInfo.TM_Trigger = 1;
3274                 return;
3275
3276         }
3277         else
3278         {
3279                 //DBG_8723A("Schedule TxPowerTracking direct call!!\n");
3280                 odm_TXPowerTrackingCallback_ThermalMeter_8188E(Adapter);
3281                 pDM_Odm->RFCalibrateInfo.TM_Trigger = 0;
3282         }
3283         #endif
3284 }
3285
3286 void
3287 odm_TXPowerTrackingCheckMP(
3288                 PDM_ODM_T               pDM_Odm
3289         )
3290 {
3291 }
3292
3293 void
3294 odm_TXPowerTrackingCheckAP(
3295                 PDM_ODM_T               pDM_Odm
3296         )
3297 {
3298 }
3299
3300
3301
3302 //antenna mapping info
3303 // 1: right-side antenna
3304 // 2/0: left-side antenna
3305 //PDM_SWAT_Table->CCK_Ant1_Cnt /OFDM_Ant1_Cnt:  for right-side antenna:   Ant:1    RxDefaultAnt1
3306 //PDM_SWAT_Table->CCK_Ant2_Cnt /OFDM_Ant2_Cnt:  for left-side antenna:     Ant:0    RxDefaultAnt2
3307 // We select left antenna as default antenna in initial process, modify it as needed
3308 //
3309
3310
3311 //3============================================================
3312 //3 SW Antenna Diversity
3313 //3============================================================
3314 #if(defined(CONFIG_SW_ANTENNA_DIVERSITY))
3315 void
3316 odm_SwAntDivInit(
3317                 PDM_ODM_T               pDM_Odm
3318         )
3319 {
3320         odm_SwAntDivInit_NIC(pDM_Odm);
3321 }
3322 #if (RTL8723A_SUPPORT==1)
3323 // Only for 8723A SW ANT DIV INIT--2012--07--17
3324 void
3325 odm_SwAntDivInit_NIC_8723A(
3326         PDM_ODM_T               pDM_Odm)
3327 {
3328         pSWAT_T         pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
3329         PADAPTER                Adapter = pDM_Odm->Adapter;
3330         u8                      btAntNum=BT_GetPGAntNum(Adapter);
3331
3332
3333         pDM_SWAT_Table->ANTA_ON =TRUE;
3334
3335         // Set default antenna B status by PG
3336         if(btAntNum == Ant_x2)
3337                 pDM_SWAT_Table->ANTB_ON = TRUE;
3338         else if(btAntNum ==Ant_x1)
3339                 pDM_SWAT_Table->ANTB_ON = FALSE;
3340         else
3341                 pDM_SWAT_Table->ANTB_ON = TRUE;
3342 }
3343 #endif
3344 void
3345 odm_SwAntDivInit_NIC(
3346                 PDM_ODM_T               pDM_Odm
3347         )
3348 {
3349         pSWAT_T         pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
3350 // Init SW ANT DIV mechanism for 8723AE/AU/AS// Neil Chen--2012--07--17---
3351 // CE/AP/ADSL no using SW ANT DIV for 8723A Series IC
3352 //#if (DM_ODM_SUPPORT_TYPE==ODM_MP)
3353 #if (RTL8723A_SUPPORT==1)
3354         if(pDM_Odm->SupportICType == ODM_RTL8723A)
3355         {
3356                 odm_SwAntDivInit_NIC_8723A(pDM_Odm);
3357         }
3358 #endif
3359         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SWAS:Init SW Antenna Switch\n"));
3360         pDM_SWAT_Table->RSSI_sum_A = 0;
3361         pDM_SWAT_Table->RSSI_cnt_A = 0;
3362         pDM_SWAT_Table->RSSI_sum_B = 0;
3363         pDM_SWAT_Table->RSSI_cnt_B = 0;
3364         pDM_SWAT_Table->CurAntenna = Antenna_A;
3365         pDM_SWAT_Table->PreAntenna = Antenna_A;
3366         pDM_SWAT_Table->try_flag = 0xff;
3367         pDM_SWAT_Table->PreRSSI = 0;
3368         pDM_SWAT_Table->SWAS_NoLink_State = 0;
3369         pDM_SWAT_Table->bTriggerAntennaSwitch = 0;
3370         pDM_SWAT_Table->SelectAntennaMap=0xAA;
3371         pDM_SWAT_Table->lastTxOkCnt = 0;
3372         pDM_SWAT_Table->lastRxOkCnt = 0;
3373         pDM_SWAT_Table->TXByteCnt_A = 0;
3374         pDM_SWAT_Table->TXByteCnt_B = 0;
3375         pDM_SWAT_Table->RXByteCnt_A = 0;
3376         pDM_SWAT_Table->RXByteCnt_B = 0;
3377         pDM_SWAT_Table->TrafficLoad = TRAFFIC_LOW;
3378         pDM_SWAT_Table->SWAS_NoLink_BK_Reg860 = ODM_Read4Byte(pDM_Odm, 0x860);
3379 }
3380
3381 //
3382 // 20100514 Joseph:
3383 // Add new function to reset the state of antenna diversity before link.
3384 //
3385 void
3386 ODM_SwAntDivResetBeforeLink(
3387                 PDM_ODM_T               pDM_Odm
3388         )
3389 {
3390
3391         pSWAT_T         pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
3392
3393         pDM_SWAT_Table->SWAS_NoLink_State = 0;
3394
3395 }
3396
3397 //
3398 // 20100514 Luke/Joseph:
3399 // Add new function to reset antenna diversity state after link.
3400 //
3401 void
3402 ODM_SwAntDivRestAfterLink(
3403  PDM_ODM_T      pDM_Odm
3404         )
3405 {
3406         pSWAT_T         pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
3407
3408         pDM_SWAT_Table->RSSI_cnt_A = 0;
3409         pDM_SWAT_Table->RSSI_cnt_B = 0;
3410         pDM_Odm->RSSI_test = FALSE;
3411         pDM_SWAT_Table->try_flag = 0xff;
3412         pDM_SWAT_Table->RSSI_Trying = 0;
3413         pDM_SWAT_Table->SelectAntennaMap=0xAA;
3414 }
3415
3416 void
3417 ODM_SwAntDivChkPerPktRssi(
3418  PDM_ODM_T      pDM_Odm,
3419  u8             StationID,
3420  PODM_PHY_INFO_T pPhyInfo
3421         )
3422 {
3423         SWAT_T          *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
3424
3425         if(!(pDM_Odm->SupportAbility & (ODM_BB_ANT_DIV)))
3426                 return;
3427
3428         if(StationID == pDM_SWAT_Table->RSSI_target)
3429         {
3430                 //1 RSSI for SW Antenna Switch
3431                 if(pDM_SWAT_Table->CurAntenna == Antenna_A)
3432                 {
3433                         pDM_SWAT_Table->RSSI_sum_A += pPhyInfo->RxPWDBAll;
3434                         pDM_SWAT_Table->RSSI_cnt_A++;
3435                 }
3436                 else
3437                 {
3438                         pDM_SWAT_Table->RSSI_sum_B += pPhyInfo->RxPWDBAll;
3439                         pDM_SWAT_Table->RSSI_cnt_B++;
3440
3441                 }
3442         }
3443
3444 }
3445
3446 //
3447 void
3448 odm_SwAntDivChkAntSwitch(
3449                 PDM_ODM_T               pDM_Odm,
3450                 u8                      Step
3451         )
3452 {
3453         //
3454         // For AP/ADSL use prtl8192cd_priv
3455         // For CE/NIC use PADAPTER
3456         //
3457         PADAPTER                pAdapter = pDM_Odm->Adapter;
3458         prtl8192cd_priv priv            = pDM_Odm->priv;
3459
3460         //
3461         // 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate
3462         // at the same time. In the stage2/3, we need to prive universal interface and merge all
3463         // HW dynamic mechanism.
3464         //
3465         switch  (pDM_Odm->SupportPlatform)
3466         {
3467                 case    ODM_MP:
3468                 case    ODM_CE:
3469                         odm_SwAntDivChkAntSwitchNIC(pDM_Odm, Step);
3470                         break;
3471
3472                 case    ODM_AP:
3473                 case    ODM_ADSL:
3474                         break;
3475         }
3476
3477 }
3478
3479 //
3480 // 20100514 Luke/Joseph:
3481 // Add new function for antenna diversity after link.
3482 // This is the main function of antenna diversity after link.
3483 // This function is called in HalDmWatchDog() and ODM_SwAntDivChkAntSwitchCallback().
3484 // HalDmWatchDog() calls this function with SWAW_STEP_PEAK to initialize the antenna test.
3485 // In SWAW_STEP_PEAK, another antenna and a 500ms timer will be set for testing.
3486 // After 500ms, ODM_SwAntDivChkAntSwitchCallback() calls this function to compare the signal just
3487 // listened on the air with the RSSI of original antenna.
3488 // It chooses the antenna with better RSSI.
3489 // There is also a aged policy for error trying. Each error trying will cost more 5 seconds waiting
3490 // penalty to get next try.
3491
3492
3493 void
3494 ODM_SetAntenna(
3495         PDM_ODM_T       pDM_Odm,
3496         u8              Antenna)
3497 {
3498         ODM_SetBBReg(pDM_Odm, 0x860, BIT8|BIT9, Antenna);
3499 }
3500 //--------------------------------2012--09--06--
3501 //Note: Antenna_Main--> Antenna_A
3502 //        Antenna_Aux---> Antenna_B
3503 //----------------------------------
3504 void
3505 odm_SwAntDivChkAntSwitchNIC(
3506                 PDM_ODM_T               pDM_Odm,
3507                 u8              Step
3508         )
3509 {
3510 #if ((RTL8192C_SUPPORT==1)||(RTL8723A_SUPPORT==1))
3511         //PMGNT_INFO            pMgntInfo = &(Adapter->MgntInfo);
3512         //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
3513         pSWAT_T         pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
3514         s4Byte                  curRSSI=100, RSSI_A, RSSI_B;
3515         u8                      nextAntenna=Antenna_B;
3516         //static u8Byte         lastTxOkCnt=0, lastRxOkCnt=0;
3517         u8Byte                  curTxOkCnt, curRxOkCnt;
3518         //static u8Byte         TXByteCnt_A=0, TXByteCnt_B=0, RXByteCnt_A=0, RXByteCnt_B=0;
3519         u8Byte                  CurByteCnt=0, PreByteCnt=0;
3520         //static u8             TrafficLoad = TRAFFIC_LOW;
3521         u8                      Score_A=0, Score_B=0;
3522         u8                      i;
3523
3524         if(!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV))
3525                 return;
3526
3527         if (pDM_Odm->SupportICType & (ODM_RTL8192D|ODM_RTL8188E))
3528                 return;
3529
3530         if((pDM_Odm->SupportICType == ODM_RTL8192C) &&(pDM_Odm->RFType == ODM_2T2R))
3531                 return;
3532
3533         if(pDM_Odm->SupportPlatform & ODM_MP)
3534         {
3535                 if(*(pDM_Odm->pAntennaTest))
3536                         return;
3537         }
3538
3539         if((pDM_SWAT_Table->ANTA_ON == FALSE) ||(pDM_SWAT_Table->ANTB_ON == FALSE))
3540         {
3541                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
3542                                 ("odm_SwAntDivChkAntSwitch(): No AntDiv Mechanism, Antenna A or B is off\n"));
3543                 return;
3544         }
3545
3546         // Radio off: Status reset to default and return.
3547         if(*(pDM_Odm->pbPowerSaving)==TRUE) //pHalData->eRFPowerState==eRfOff
3548         {
3549                 ODM_SwAntDivRestAfterLink(pDM_Odm);
3550                 return;
3551         }
3552
3553
3554         // Handling step mismatch condition.
3555         // Peak step is not finished at last time. Recover the variable and check again.
3556         if(     Step != pDM_SWAT_Table->try_flag        )
3557         {
3558                 ODM_SwAntDivRestAfterLink(pDM_Odm);
3559         }
3560
3561         if(pDM_SWAT_Table->try_flag == 0xff)
3562         {
3563                 pDM_SWAT_Table->RSSI_target = 0xff;
3564
3565                 {
3566                         u8                      index = 0;
3567                         PSTA_INFO_T             pEntry = NULL;
3568
3569
3570                         for(index=0; index<ODM_ASSOCIATE_ENTRY_NUM; index++)
3571                         {
3572                                 pEntry =  pDM_Odm->pODM_StaInfo[index];
3573                                 if(IS_STA_VALID(pEntry) ) {
3574                                         break;
3575                                 }
3576                         }
3577                         if(pEntry == NULL)
3578                         {
3579                                 ODM_SwAntDivRestAfterLink(pDM_Odm);
3580                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_SwAntDivChkAntSwitch(): No Link.\n"));
3581                                 return;
3582                         }
3583                         else
3584                         {
3585                                 pDM_SWAT_Table->RSSI_target = index;
3586                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_SwAntDivChkAntSwitch(): RSSI_target is PEER STA\n"));
3587                         }
3588                 }
3589
3590                 pDM_SWAT_Table->RSSI_cnt_A = 0;
3591                 pDM_SWAT_Table->RSSI_cnt_B = 0;
3592                 pDM_SWAT_Table->try_flag = 0;
3593                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("odm_SwAntDivChkAntSwitch(): Set try_flag to 0 prepare for peak!\n"));
3594                 return;
3595         }
3596         else
3597         {
3598                 curTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast) - pDM_SWAT_Table->lastTxOkCnt;
3599                 curRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast) - pDM_SWAT_Table->lastRxOkCnt;
3600                 pDM_SWAT_Table->lastTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast);
3601                 pDM_SWAT_Table->lastRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast);
3602              ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("curTxOkCnt = %lld\n",curTxOkCnt));
3603                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("curRxOkCnt = %lld\n",curRxOkCnt));
3604                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("lastTxOkCnt = %lld\n",pDM_SWAT_Table->lastTxOkCnt));
3605                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("lastRxOkCnt = %lld\n",pDM_SWAT_Table->lastRxOkCnt));
3606
3607                 if(pDM_SWAT_Table->try_flag == 1)
3608                 {
3609                         if(pDM_SWAT_Table->CurAntenna == Antenna_A)
3610                         {
3611                                 pDM_SWAT_Table->TXByteCnt_A += curTxOkCnt;
3612                                 pDM_SWAT_Table->RXByteCnt_A += curRxOkCnt;
3613                         }
3614                         else
3615                         {
3616                                 pDM_SWAT_Table->TXByteCnt_B += curTxOkCnt;
3617                                 pDM_SWAT_Table->RXByteCnt_B += curRxOkCnt;
3618                         }
3619
3620                         nextAntenna = (pDM_SWAT_Table->CurAntenna == Antenna_A)? Antenna_B : Antenna_A;
3621                         pDM_SWAT_Table->RSSI_Trying--;
3622                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("RSSI_Trying = %d\n",pDM_SWAT_Table->RSSI_Trying));
3623                         if(pDM_SWAT_Table->RSSI_Trying == 0)
3624                         {
3625                                 CurByteCnt = (pDM_SWAT_Table->CurAntenna == Antenna_A)? (pDM_SWAT_Table->TXByteCnt_A+pDM_SWAT_Table->RXByteCnt_A) : (pDM_SWAT_Table->TXByteCnt_B+pDM_SWAT_Table->RXByteCnt_B);
3626                                 PreByteCnt = (pDM_SWAT_Table->CurAntenna == Antenna_A)? (pDM_SWAT_Table->TXByteCnt_B+pDM_SWAT_Table->RXByteCnt_B) : (pDM_SWAT_Table->TXByteCnt_A+pDM_SWAT_Table->RXByteCnt_A);
3627
3628                                 if(pDM_SWAT_Table->TrafficLoad == TRAFFIC_HIGH)
3629                                         //CurByteCnt = PlatformDivision64(CurByteCnt, 9);
3630                                         PreByteCnt = PreByteCnt*9;
3631                                 else if(pDM_SWAT_Table->TrafficLoad == TRAFFIC_LOW)
3632                                         //CurByteCnt = PlatformDivision64(CurByteCnt, 2);
3633                                         PreByteCnt = PreByteCnt*2;
3634
3635                                 if(pDM_SWAT_Table->RSSI_cnt_A > 0)
3636                                         RSSI_A = pDM_SWAT_Table->RSSI_sum_A/pDM_SWAT_Table->RSSI_cnt_A;
3637                                 else
3638                                         RSSI_A = 0;
3639                                 if(pDM_SWAT_Table->RSSI_cnt_B > 0)
3640                                         RSSI_B = pDM_SWAT_Table->RSSI_sum_B/pDM_SWAT_Table->RSSI_cnt_B;
3641                                 else
3642                                         RSSI_B = 0;
3643                                 curRSSI = (pDM_SWAT_Table->CurAntenna == Antenna_A)? RSSI_A : RSSI_B;
3644                                 pDM_SWAT_Table->PreRSSI =  (pDM_SWAT_Table->CurAntenna == Antenna_A)? RSSI_B : RSSI_A;
3645                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Luke:PreRSSI = %d, CurRSSI = %d\n",pDM_SWAT_Table->PreRSSI, curRSSI));
3646                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SWAS: preAntenna= %s, curAntenna= %s \n",
3647                                 (pDM_SWAT_Table->PreAntenna == Antenna_A?"A":"B"), (pDM_SWAT_Table->CurAntenna == Antenna_A?"A":"B")));
3648                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Luke:RSSI_A= %d, RSSI_cnt_A = %d, RSSI_B= %d, RSSI_cnt_B = %d\n",
3649                                         RSSI_A, pDM_SWAT_Table->RSSI_cnt_A, RSSI_B, pDM_SWAT_Table->RSSI_cnt_B));
3650                         }
3651
3652                 }
3653                 else
3654                 {
3655
3656                         if(pDM_SWAT_Table->RSSI_cnt_A > 0)
3657                                 RSSI_A = pDM_SWAT_Table->RSSI_sum_A/pDM_SWAT_Table->RSSI_cnt_A;
3658                         else
3659                                 RSSI_A = 0;
3660                         if(pDM_SWAT_Table->RSSI_cnt_B > 0)
3661                                 RSSI_B = pDM_SWAT_Table->RSSI_sum_B/pDM_SWAT_Table->RSSI_cnt_B;
3662                         else
3663                                 RSSI_B = 0;
3664                         curRSSI = (pDM_SWAT_Table->CurAntenna == Antenna_A)? RSSI_A : RSSI_B;
3665                         pDM_SWAT_Table->PreRSSI =  (pDM_SWAT_Table->PreAntenna == Antenna_A)? RSSI_A : RSSI_B;
3666                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ekul:PreRSSI = %d, CurRSSI = %d\n", pDM_SWAT_Table->PreRSSI, curRSSI));
3667                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SWAS: preAntenna= %s, curAntenna= %s \n",
3668                         (pDM_SWAT_Table->PreAntenna == Antenna_A?"A":"B"), (pDM_SWAT_Table->CurAntenna == Antenna_A?"A":"B")));
3669
3670                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ekul:RSSI_A= %d, RSSI_cnt_A = %d, RSSI_B= %d, RSSI_cnt_B = %d\n",
3671                                 RSSI_A, pDM_SWAT_Table->RSSI_cnt_A, RSSI_B, pDM_SWAT_Table->RSSI_cnt_B));
3672                         //RT_TRACE(COMP_SWAS, DBG_LOUD, ("Ekul:curTxOkCnt = %d\n", curTxOkCnt));
3673                         //RT_TRACE(COMP_SWAS, DBG_LOUD, ("Ekul:curRxOkCnt = %d\n", curRxOkCnt));
3674                 }
3675
3676                 //1 Trying State
3677                 if((pDM_SWAT_Table->try_flag == 1)&&(pDM_SWAT_Table->RSSI_Trying == 0))
3678                 {
3679
3680                         if(pDM_SWAT_Table->TestMode == TP_MODE)
3681                         {
3682                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SWAS: TestMode = TP_MODE"));
3683                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("TRY:CurByteCnt = %lld,", CurByteCnt));
3684                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("TRY:PreByteCnt = %lld\n",PreByteCnt));
3685                                 if(CurByteCnt < PreByteCnt)
3686                                 {
3687                                         if(pDM_SWAT_Table->CurAntenna == Antenna_A)
3688                                                 pDM_SWAT_Table->SelectAntennaMap=pDM_SWAT_Table->SelectAntennaMap<<1;
3689                                         else
3690                                                 pDM_SWAT_Table->SelectAntennaMap=(pDM_SWAT_Table->SelectAntennaMap<<1)+1;
3691                                 }
3692                                 else
3693                                 {
3694                                         if(pDM_SWAT_Table->CurAntenna == Antenna_A)
3695                                                 pDM_SWAT_Table->SelectAntennaMap=(pDM_SWAT_Table->SelectAntennaMap<<1)+1;
3696                                         else
3697                                                 pDM_SWAT_Table->SelectAntennaMap=pDM_SWAT_Table->SelectAntennaMap<<1;
3698                                 }
3699                                 for (i= 0; i<8; i++)
3700                                 {
3701                                         if(((pDM_SWAT_Table->SelectAntennaMap>>i)&BIT0) == 1)
3702                                                 Score_A++;
3703                                         else
3704                                                 Score_B++;
3705                                 }
3706                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SelectAntennaMap=%x\n ",pDM_SWAT_Table->SelectAntennaMap));
3707                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Score_A=%d, Score_B=%d\n", Score_A, Score_B));
3708
3709                                 if(pDM_SWAT_Table->CurAntenna == Antenna_A)
3710                                 {
3711                                         nextAntenna = (Score_A > Score_B)?Antenna_A:Antenna_B;
3712                                 }
3713                                 else
3714                                 {
3715                                         nextAntenna = (Score_B > Score_A)?Antenna_B:Antenna_A;
3716                                 }
3717                                 //RT_TRACE(COMP_SWAS, DBG_LOUD, ("nextAntenna=%s\n",(nextAntenna==Antenna_A)?"A":"B"));
3718                                 //RT_TRACE(COMP_SWAS, DBG_LOUD, ("preAntenna= %s, curAntenna= %s \n",
3719                                 //(DM_SWAT_Table.PreAntenna == Antenna_A?"A":"B"), (DM_SWAT_Table.CurAntenna == Antenna_A?"A":"B")));
3720
3721                                 if(nextAntenna != pDM_SWAT_Table->CurAntenna)
3722                                 {
3723                                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SWAS: Switch back to another antenna"));
3724                                 }
3725                                 else
3726                                 {
3727                                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SWAS: current anntena is good\n"));
3728                                 }
3729                         }
3730
3731                         if(pDM_SWAT_Table->TestMode == RSSI_MODE)
3732                         {
3733                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SWAS: TestMode = RSSI_MODE"));
3734                                 pDM_SWAT_Table->SelectAntennaMap=0xAA;
3735                                 if(curRSSI < pDM_SWAT_Table->PreRSSI) //Current antenna is worse than previous antenna
3736                                 {
3737                                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SWAS: Switch back to another antenna"));
3738                                         nextAntenna = (pDM_SWAT_Table->CurAntenna == Antenna_A)? Antenna_B : Antenna_A;
3739                                 }
3740                                 else // current anntena is good
3741                                 {
3742                                         nextAntenna =pDM_SWAT_Table->CurAntenna;
3743                                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SWAS: current anntena is good\n"));
3744                                 }
3745                         }
3746                         pDM_SWAT_Table->try_flag = 0;
3747                         pDM_Odm->RSSI_test = FALSE;
3748                         pDM_SWAT_Table->RSSI_sum_A = 0;
3749                         pDM_SWAT_Table->RSSI_cnt_A = 0;
3750                         pDM_SWAT_Table->RSSI_sum_B = 0;
3751                         pDM_SWAT_Table->RSSI_cnt_B = 0;
3752                         pDM_SWAT_Table->TXByteCnt_A = 0;
3753                         pDM_SWAT_Table->TXByteCnt_B = 0;
3754                         pDM_SWAT_Table->RXByteCnt_A = 0;
3755                         pDM_SWAT_Table->RXByteCnt_B = 0;
3756
3757                 }
3758
3759                 //1 Normal State
3760                 else if(pDM_SWAT_Table->try_flag == 0)
3761                 {
3762                         if(pDM_SWAT_Table->TrafficLoad == TRAFFIC_HIGH)
3763                         {
3764                                 if ((curTxOkCnt+curRxOkCnt) > 3750000)//if(PlatformDivision64(curTxOkCnt+curRxOkCnt, 2) > 1875000)
3765                                         pDM_SWAT_Table->TrafficLoad = TRAFFIC_HIGH;
3766                                 else
3767                                         pDM_SWAT_Table->TrafficLoad = TRAFFIC_LOW;
3768                         }
3769                         else if(pDM_SWAT_Table->TrafficLoad == TRAFFIC_LOW)
3770                                 {
3771                                 if ((curTxOkCnt+curRxOkCnt) > 3750000) //if(PlatformDivision64(curTxOkCnt+curRxOkCnt, 2) > 1875000)
3772                                         pDM_SWAT_Table->TrafficLoad = TRAFFIC_HIGH;
3773                                 else
3774                                         pDM_SWAT_Table->TrafficLoad = TRAFFIC_LOW;
3775                         }
3776                         if(pDM_SWAT_Table->TrafficLoad == TRAFFIC_HIGH)
3777                                 pDM_SWAT_Table->bTriggerAntennaSwitch = 0;
3778                         //RT_TRACE(COMP_SWAS, DBG_LOUD, ("Normal:TrafficLoad = %llu\n", curTxOkCnt+curRxOkCnt));
3779
3780                         //Prepare To Try Antenna
3781                                         nextAntenna = (pDM_SWAT_Table->CurAntenna == Antenna_A)? Antenna_B : Antenna_A;
3782                                         pDM_SWAT_Table->try_flag = 1;
3783                                         pDM_Odm->RSSI_test = TRUE;
3784                         if((curRxOkCnt+curTxOkCnt) > 1000)
3785                         {
3786                                 pDM_SWAT_Table->RSSI_Trying = 4;
3787                                 pDM_SWAT_Table->TestMode = TP_MODE;
3788                                 }
3789                                 else
3790                                 {
3791                                 pDM_SWAT_Table->RSSI_Trying = 2;
3792                                 pDM_SWAT_Table->TestMode = RSSI_MODE;
3793
3794                         }
3795                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SWAS: Normal State -> Begin Trying!\n"));
3796
3797
3798                         pDM_SWAT_Table->RSSI_sum_A = 0;
3799                         pDM_SWAT_Table->RSSI_cnt_A = 0;
3800                         pDM_SWAT_Table->RSSI_sum_B = 0;
3801                         pDM_SWAT_Table->RSSI_cnt_B = 0;
3802                 }
3803         }
3804
3805         //1 4.Change TRX antenna
3806         if(nextAntenna != pDM_SWAT_Table->CurAntenna)
3807         {
3808                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SWAS: Change TX Antenna!\n "));
3809                 //PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300, nextAntenna);
3810                 {
3811                         bool bEnqueue;
3812                         bEnqueue = (pDM_Odm->SupportInterface ==  ODM_ITRF_PCIE)?FALSE :TRUE;
3813                         rtw_antenna_select_cmd(pDM_Odm->Adapter, nextAntenna, bEnqueue);
3814                 }
3815         }
3816
3817         //1 5.Reset Statistics
3818         pDM_SWAT_Table->PreAntenna = pDM_SWAT_Table->CurAntenna;
3819         pDM_SWAT_Table->CurAntenna = nextAntenna;
3820         pDM_SWAT_Table->PreRSSI = curRSSI;
3821
3822         //1 6.Set next timer
3823         {
3824                 PADAPTER                pAdapter = pDM_Odm->Adapter;
3825                 HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
3826
3827
3828         if(pDM_SWAT_Table->RSSI_Trying == 0)
3829                 return;
3830
3831         if(pDM_SWAT_Table->RSSI_Trying%2 == 0)
3832         {
3833                 if(pDM_SWAT_Table->TestMode == TP_MODE)
3834                 {
3835                         if(pDM_SWAT_Table->TrafficLoad == TRAFFIC_HIGH)
3836                         {
3837                                 //PlatformSetTimer( pAdapter, &pHalData->SwAntennaSwitchTimer, 10 ); //ms
3838                                 ODM_SetTimer(pDM_Odm,&pDM_SWAT_Table->SwAntennaSwitchTimer, 10 ); //ms
3839
3840                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("dm_SW_AntennaSwitch(): Test another antenna for 10 ms\n"));
3841                         }
3842                         else if(pDM_SWAT_Table->TrafficLoad == TRAFFIC_LOW)
3843                         {
3844                                 //PlatformSetTimer( pAdapter, &pHalData->SwAntennaSwitchTimer, 50 ); //ms
3845                                 ODM_SetTimer(pDM_Odm,&pDM_SWAT_Table->SwAntennaSwitchTimer, 50 ); //ms
3846                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("dm_SW_AntennaSwitch(): Test another antenna for 50 ms\n"));
3847                         }
3848                 }
3849                 else
3850                 {
3851                         //PlatformSetTimer( pAdapter, &pHalData->SwAntennaSwitchTimer, 500 ); //ms
3852                         ODM_SetTimer(pDM_Odm,&pDM_SWAT_Table->SwAntennaSwitchTimer, 500 ); //ms
3853                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("dm_SW_AntennaSwitch(): Test another antenna for 500 ms\n"));
3854                 }
3855         }
3856         else
3857         {
3858                 if(pDM_SWAT_Table->TestMode == TP_MODE)
3859                 {
3860                         if(pDM_SWAT_Table->TrafficLoad == TRAFFIC_HIGH)
3861                                 //PlatformSetTimer( pAdapter, &pHalData->SwAntennaSwitchTimer, 90 ); //ms
3862                                 ODM_SetTimer(pDM_Odm,&pDM_SWAT_Table->SwAntennaSwitchTimer, 90 ); //ms
3863                         else if(pDM_SWAT_Table->TrafficLoad == TRAFFIC_LOW)
3864                                 //PlatformSetTimer( pAdapter, &pHalData->SwAntennaSwitchTimer, 100 ); //ms
3865                                 ODM_SetTimer(pDM_Odm,&pDM_SWAT_Table->SwAntennaSwitchTimer, 100 ); //ms
3866                 }
3867                 else
3868                         //PlatformSetTimer( pAdapter, &pHalData->SwAntennaSwitchTimer, 500 ); //ms
3869                         ODM_SetTimer(pDM_Odm,&pDM_SWAT_Table->SwAntennaSwitchTimer, 500 ); //ms
3870         }
3871         }
3872 #endif  // #if (RTL8192C_SUPPORT==1)
3873 }
3874
3875
3876 //
3877 // 20100514 Luke/Joseph:
3878 // Callback function for 500ms antenna test trying.
3879 //
3880 void odm_SwAntDivChkAntSwitchCallback(void *FunctionContext)
3881 {
3882         PDM_ODM_T       pDM_Odm= (PDM_ODM_T)FunctionContext;
3883         PADAPTER        padapter = pDM_Odm->Adapter;
3884         if(padapter->net_closed == _TRUE)
3885             return;
3886         odm_SwAntDivChkAntSwitch(pDM_Odm, SWAW_STEP_DETERMINE);
3887 }
3888
3889 #else //#if(defined(CONFIG_SW_ANTENNA_DIVERSITY))
3890
3891 void odm_SwAntDivInit(          PDM_ODM_T               pDM_Odm ) {}
3892 void ODM_SwAntDivChkPerPktRssi(
3893  PDM_ODM_T      pDM_Odm,
3894  u8             StationID,
3895  PODM_PHY_INFO_T pPhyInfo
3896         ) {}
3897 void odm_SwAntDivChkAntSwitch(
3898                 PDM_ODM_T               pDM_Odm,
3899                 u8                      Step
3900         ) {}
3901 void ODM_SwAntDivResetBeforeLink(               PDM_ODM_T               pDM_Odm ){}
3902 void ODM_SwAntDivRestAfterLink(         PDM_ODM_T               pDM_Odm ){}
3903 void odm_SwAntDivChkAntSwitchCallback(void *FunctionContext){}
3904
3905 #endif //#if(defined(CONFIG_SW_ANTENNA_DIVERSITY))
3906
3907 //3============================================================
3908 //3 SW Antenna Diversity
3909 //3============================================================
3910
3911 #if(defined(CONFIG_HW_ANTENNA_DIVERSITY))
3912 void
3913 odm_InitHybridAntDiv_88C_92D(
3914  PDM_ODM_T      pDM_Odm
3915         )
3916 {
3917
3918         SWAT_T                  *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
3919         u8                  bTxPathSel=0;               //0:Path-A   1:Path-B
3920         u8                      i;
3921
3922         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("odm_InitHybridAntDiv==============>\n"));
3923
3924         if((pDM_Odm->SupportICType != ODM_RTL8192C) && (pDM_Odm->SupportICType != ODM_RTL8192D))
3925                 return;
3926
3927
3928         bTxPathSel=(pDM_Odm->RFType==ODM_1T1R)?FALSE:TRUE;
3929
3930         ODM_SetBBReg(pDM_Odm,ODM_REG_BB_PWR_SAV1_11N, BIT23, 0); //No update ANTSEL during GNT_BT=1
3931         ODM_SetBBReg(pDM_Odm,ODM_REG_TX_ANT_CTRL_11N, BIT21, 1); //TX atenna selection from tx_info
3932         ODM_SetBBReg(pDM_Odm,ODM_REG_ANTSEL_PIN_11N, BIT23, 1); //enable LED[1:0] pin as ANTSEL
3933         ODM_SetBBReg(pDM_Odm,ODM_REG_ANTSEL_CTRL_11N, BIT8|BIT9, 0x01); // 0x01: left antenna, 0x02: right antenna
3934         // check HW setting: ANTSEL pin connection
3935
3936         // only AP support different path selection temperarly
3937         if(!bTxPathSel){                 //PATH-A
3938                 ODM_SetBBReg(pDM_Odm,ODM_REG_PIN_CTRL_11N, BIT8|BIT9, 0 ); // ANTSEL as HW control
3939                 ODM_SetBBReg(pDM_Odm,ODM_REG_ANTSEL_PATH_11N, BIT13, 1);         //select TX ANTESEL from path A
3940         }
3941         else    {
3942                 ODM_SetBBReg(pDM_Odm,ODM_REG_PIN_CTRL_11N, BIT24|BIT25, 0 ); // ANTSEL as HW control
3943                 ODM_SetBBReg(pDM_Odm,ODM_REG_ANTSEL_PATH_11N, BIT13, 0);                 //select ANTESEL from path B
3944         }
3945
3946         //Set OFDM HW RX Antenna Diversity
3947         ODM_SetBBReg(pDM_Odm,ODM_REG_ANTDIV_PARA1_11N, 0x7FF, 0x0c0); //Pwdb threshold=8dB
3948         ODM_SetBBReg(pDM_Odm,ODM_REG_ANTDIV_PARA1_11N, BIT11, 0); //Switch to another antenna by checking pwdb threshold
3949         ODM_SetBBReg(pDM_Odm,ODM_REG_ANTDIV_PARA3_11N, BIT23, 1);       // Decide final antenna by comparing 2 antennas' pwdb
3950
3951         //Set CCK HW RX Antenna Diversity
3952         ODM_SetBBReg(pDM_Odm,ODM_REG_CCK_ANTDIV_PARA2_11N, BIT4, 0); //Antenna diversity decision period = 32 sample
3953         ODM_SetBBReg(pDM_Odm,ODM_REG_CCK_ANTDIV_PARA2_11N, 0xf, 0xf); //Threshold for antenna diversity. Check another antenna power if input power < ANT_lim*4
3954         ODM_SetBBReg(pDM_Odm,ODM_REG_CCK_ANTDIV_PARA3_11N, BIT13, 1); //polarity ana_A=1 and ana_B=0
3955         ODM_SetBBReg(pDM_Odm,ODM_REG_CCK_ANTDIV_PARA4_11N, 0x1f, 0x8); //default antenna power = inpwr*(0.5 + r_ant_step/16)
3956
3957
3958         //Enable HW Antenna Diversity
3959         if(!bTxPathSel)                 //PATH-A
3960                 ODM_SetBBReg(pDM_Odm,ODM_REG_IGI_A_11N, BIT7,1);        // Enable Hardware antenna switch
3961         else
3962                 ODM_SetBBReg(pDM_Odm,ODM_REG_IGI_B_11N, BIT7,1);        // Enable Hardware antenna switch
3963         ODM_SetBBReg(pDM_Odm,ODM_REG_CCK_ANTDIV_PARA1_11N, BIT15, 1);//Enable antenna diversity
3964
3965         pDM_SWAT_Table->CurAntenna=0;                   //choose left antenna as default antenna
3966         pDM_SWAT_Table->PreAntenna=0;
3967         for(i=0; i<ASSOCIATE_ENTRY_NUM ; i++)
3968         {
3969                 pDM_SWAT_Table->CCK_Ant1_Cnt[i] = 0;
3970                 pDM_SWAT_Table->CCK_Ant2_Cnt[i] = 0;
3971                 pDM_SWAT_Table->OFDM_Ant1_Cnt[i] = 0;
3972                 pDM_SWAT_Table->OFDM_Ant2_Cnt[i] = 0;
3973                 pDM_SWAT_Table->RSSI_Ant1_Sum[i] = 0;
3974                 pDM_SWAT_Table->RSSI_Ant2_Sum[i] = 0;
3975         }
3976         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("<==============odm_InitHybridAntDiv\n"));
3977 }
3978
3979
3980 void
3981 odm_InitHybridAntDiv(
3982  PDM_ODM_T      pDM_Odm
3983         )
3984 {
3985         if(!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV))
3986         {
3987                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("Return: Not Support HW AntDiv\n"));
3988                 return;
3989         }
3990
3991         if(pDM_Odm->SupportICType & (ODM_RTL8192C | ODM_RTL8192D))
3992         {
3993 #if ((RTL8192C_SUPPORT == 1)||(RTL8192D_SUPPORT == 1))
3994                 odm_InitHybridAntDiv_88C_92D(pDM_Odm);
3995 #endif
3996         }
3997         else if(pDM_Odm->SupportICType == ODM_RTL8188E)
3998         {
3999 #if (RTL8188E_SUPPORT == 1)
4000                 ODM_AntennaDiversityInit_88E(pDM_Odm);
4001 #endif
4002         }
4003
4004 }
4005
4006
4007 bool
4008 odm_StaDefAntSel(
4009  PDM_ODM_T      pDM_Odm,
4010  u4Byte         OFDM_Ant1_Cnt,
4011  u4Byte         OFDM_Ant2_Cnt,
4012  u4Byte         CCK_Ant1_Cnt,
4013  u4Byte         CCK_Ant2_Cnt,
4014  u8             *pDefAnt
4015
4016         )
4017 {
4018 #if 1
4019         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("odm_StaDefAntSelect==============>\n"));
4020
4021         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("OFDM_Ant1_Cnt:%d, OFDM_Ant2_Cnt:%d\n",OFDM_Ant1_Cnt,OFDM_Ant2_Cnt));
4022         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("CCK_Ant1_Cnt:%d, CCK_Ant2_Cnt:%d\n",CCK_Ant1_Cnt,CCK_Ant2_Cnt));
4023
4024
4025         if(((OFDM_Ant1_Cnt+OFDM_Ant2_Cnt)==0)&&((CCK_Ant1_Cnt + CCK_Ant2_Cnt) <10)){
4026                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("odm_StaDefAntSelect Fail: No enough packet info!\n"));
4027                 return  FALSE;
4028         }
4029
4030         if(OFDM_Ant1_Cnt || OFDM_Ant2_Cnt )     {
4031                 //if RX OFDM packet number larger than 0
4032                 if(OFDM_Ant1_Cnt > OFDM_Ant2_Cnt)
4033                         (*pDefAnt)=1;
4034                 else
4035                         (*pDefAnt)=0;
4036         }
4037         // else if RX CCK packet number larger than 10
4038         else if((CCK_Ant1_Cnt + CCK_Ant2_Cnt) >=10 )
4039         {
4040                 if(CCK_Ant1_Cnt > (5*CCK_Ant2_Cnt))
4041                         (*pDefAnt)=1;
4042                 else if(CCK_Ant2_Cnt > (5*CCK_Ant1_Cnt))
4043                         (*pDefAnt)=0;
4044                 else if(CCK_Ant1_Cnt > CCK_Ant2_Cnt)
4045                         (*pDefAnt)=0;
4046                 else
4047                         (*pDefAnt)=1;
4048
4049         }
4050
4051         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("TxAnt = %s\n",((*pDefAnt)==1)?"Ant1":"Ant2"));
4052
4053 #endif
4054         //u4Byte antsel = ODM_GetBBReg(pDM_Odm, 0xc88, bMaskByte0);
4055         //(*pDefAnt)= (u8) antsel;
4056
4057
4058
4059
4060         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("<==============odm_StaDefAntSelect\n"));
4061
4062         return TRUE;
4063
4064
4065 }
4066
4067
4068 void
4069 odm_SetRxIdleAnt(
4070         PDM_ODM_T       pDM_Odm,
4071         u8      Ant,
4072    bool   bDualPath
4073 )
4074 {
4075         SWAT_T                  *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
4076
4077         //ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("odm_SetRxIdleAnt==============>\n"));
4078
4079         if(Ant != pDM_SWAT_Table->RxIdleAnt)
4080         {
4081         //for path-A
4082         if(Ant==1)
4083                         ODM_SetBBReg(pDM_Odm,ODM_REG_RX_DEFUALT_A_11N, 0xFFFF, 0x65a9);   //right-side antenna
4084         else
4085                         ODM_SetBBReg(pDM_Odm,ODM_REG_RX_DEFUALT_A_11N, 0xFFFF, 0x569a);   //left-side antenna
4086
4087         //for path-B
4088         if(bDualPath){
4089                         if(Ant==0)
4090                                 ODM_SetBBReg(pDM_Odm,ODM_REG_RX_DEFUALT_A_11N, 0xFFFF0000, 0x65a9);   //right-side antenna
4091                 else
4092                                 ODM_SetBBReg(pDM_Odm,ODM_REG_RX_DEFUALT_A_11N, 0xFFFF0000, 0x569a);  //left-side antenna
4093                 }
4094         }
4095                 pDM_SWAT_Table->RxIdleAnt = Ant;
4096         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("RxIdleAnt: %s  Reg858=0x%x\n",(Ant==1)?"Ant1":"Ant2",(Ant==1)?0x65a9:0x569a));
4097
4098         //ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("<==============odm_SetRxIdleAnt\n"));
4099
4100         }
4101
4102 void
4103 ODM_AntselStatistics_88C(
4104                 PDM_ODM_T               pDM_Odm,
4105                 u8                      MacId,
4106                 u4Byte                  PWDBAll,
4107                 bool                    isCCKrate
4108 )
4109 {
4110         SWAT_T                  *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
4111
4112         if(pDM_SWAT_Table->antsel == 1)
4113         {
4114                 if(isCCKrate)
4115                         pDM_SWAT_Table->CCK_Ant1_Cnt[MacId]++;
4116                 else
4117                 {
4118                         pDM_SWAT_Table->OFDM_Ant1_Cnt[MacId]++;
4119                         pDM_SWAT_Table->RSSI_Ant1_Sum[MacId] += PWDBAll;
4120                 }
4121         }
4122         else
4123         {
4124                 if(isCCKrate)
4125                         pDM_SWAT_Table->CCK_Ant2_Cnt[MacId]++;
4126                 else
4127                 {
4128                         pDM_SWAT_Table->OFDM_Ant2_Cnt[MacId]++;
4129                         pDM_SWAT_Table->RSSI_Ant2_Sum[MacId] += PWDBAll;
4130                 }
4131         }
4132
4133 }
4134
4135
4136 void
4137 ODM_SetTxAntByTxInfo_88C_92D(
4138                 PDM_ODM_T               pDM_Odm
4139 )
4140 {
4141
4142 }
4143
4144 void
4145 odm_HwAntDiv_92C_92D(
4146         PDM_ODM_T       pDM_Odm
4147 )
4148 {
4149         SWAT_T                  *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
4150         u4Byte                  RSSI_Min=0xFF, RSSI, RSSI_Ant1, RSSI_Ant2;
4151         u8                      RxIdleAnt, i;
4152         bool            bRet=FALSE;
4153         PSTA_INFO_T     pEntry;
4154
4155         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("odm_HwAntDiv==============>\n"));
4156
4157         if(!(pDM_Odm->SupportAbility&ODM_BB_ANT_DIV))                                    //if don't support antenna diveristy
4158         {
4159                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("odm_HwAntDiv: Not supported!\n"));
4160                 return;
4161         }
4162
4163         if((pDM_Odm->SupportICType != ODM_RTL8192C) && (pDM_Odm->SupportICType != ODM_RTL8192D))
4164         {
4165                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("Return: IC Type is not 92C or 92D\n"));
4166                 return;
4167         }
4168
4169         if(!pDM_Odm->bLinked)
4170         {
4171                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("Return: bLinked is FALSE\n"));
4172                 return;
4173         }
4174
4175         for (i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++)
4176         {
4177                 pEntry = pDM_Odm->pODM_StaInfo[i];
4178                 if(IS_STA_VALID(pEntry))
4179                 {
4180
4181                         RSSI_Ant1 = (pDM_SWAT_Table->OFDM_Ant1_Cnt[i] == 0)?0:(pDM_SWAT_Table->RSSI_Ant1_Sum[i]/pDM_SWAT_Table->OFDM_Ant1_Cnt[i]);
4182                         RSSI_Ant2 = (pDM_SWAT_Table->OFDM_Ant2_Cnt[i] == 0)?0:(pDM_SWAT_Table->RSSI_Ant2_Sum[i]/pDM_SWAT_Table->OFDM_Ant2_Cnt[i]);
4183
4184                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("RSSI_Ant1=%d,  RSSI_Ant2=%d\n", RSSI_Ant1, RSSI_Ant2));
4185
4186                         if(RSSI_Ant1 ||RSSI_Ant2)
4187                         {
4188                                 RSSI = (RSSI_Ant1 < RSSI_Ant2) ? RSSI_Ant1 : RSSI_Ant2;
4189                                 if((!RSSI) || ( RSSI < RSSI_Min) ) {
4190                                         pDM_SWAT_Table->TargetSTA = i;
4191                                         RSSI_Min = RSSI;
4192                                 }
4193                         }
4194                         ///STA: found out default antenna
4195                         bRet=odm_StaDefAntSel(pDM_Odm,
4196                                                  pDM_SWAT_Table->OFDM_Ant1_Cnt[i],
4197                                                  pDM_SWAT_Table->OFDM_Ant2_Cnt[i],
4198                                                  pDM_SWAT_Table->CCK_Ant1_Cnt[i],
4199                                                  pDM_SWAT_Table->CCK_Ant2_Cnt[i],
4200                                                  &pDM_SWAT_Table->TxAnt[i]);
4201
4202                         //if Tx antenna selection: successful
4203                         if(bRet){
4204                                 pDM_SWAT_Table->RSSI_Ant1_Sum[i] = 0;
4205                                 pDM_SWAT_Table->RSSI_Ant2_Sum[i] = 0;
4206                                 pDM_SWAT_Table->OFDM_Ant1_Cnt[i] = 0;
4207                                 pDM_SWAT_Table->OFDM_Ant2_Cnt[i] = 0;
4208                                 pDM_SWAT_Table->CCK_Ant1_Cnt[i] = 0;
4209                                 pDM_SWAT_Table->CCK_Ant2_Cnt[i] = 0;
4210                         }
4211                 }
4212         }
4213
4214         //set RX Idle Ant
4215         RxIdleAnt = pDM_SWAT_Table->TxAnt[pDM_SWAT_Table->TargetSTA];
4216         odm_SetRxIdleAnt(pDM_Odm, RxIdleAnt, FALSE);
4217
4218         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("<==============odm_HwAntDiv\n"));
4219 }
4220
4221 void
4222 odm_HwAntDiv(
4223         PDM_ODM_T       pDM_Odm
4224 )
4225 {
4226         if(!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV))
4227         {
4228                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("Return: Not Support HW AntDiv\n"));
4229                 return;
4230         }
4231
4232         if(pDM_Odm->SupportICType & (ODM_RTL8192C | ODM_RTL8192D))
4233         {
4234 #if ((RTL8192C_SUPPORT == 1)||(RTL8192D_SUPPORT == 1))
4235                 odm_HwAntDiv_92C_92D(pDM_Odm);
4236 #endif
4237         }
4238         else if(pDM_Odm->SupportICType == ODM_RTL8188E)
4239         {
4240 #if (RTL8188E_SUPPORT == 1)
4241                 ODM_AntennaDiversity_88E(pDM_Odm);
4242 #endif
4243         }
4244
4245 }
4246
4247
4248
4249 #else //#if(defined(CONFIG_HW_ANTENNA_DIVERSITY))
4250
4251 void odm_InitHybridAntDiv( PDM_ODM_T    pDM_Odm         ){}
4252 void odm_HwAntDiv(      PDM_ODM_T       pDM_Odm){}
4253 void ODM_SetTxAntByTxInfo_88C_92D(              PDM_ODM_T               pDM_Odm){ }
4254
4255 #endif //#if(defined(CONFIG_HW_ANTENNA_DIVERSITY))
4256
4257
4258
4259 //============================================================
4260 //EDCA Turbo
4261 //============================================================
4262 void
4263 ODM_EdcaTurboInit(
4264     PDM_ODM_T           pDM_Odm)
4265 {
4266
4267         PADAPTER        Adapter = pDM_Odm->Adapter;
4268         pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = FALSE;
4269         pDM_Odm->DM_EDCA_Table.bIsCurRDLState = FALSE;
4270         Adapter->recvpriv.bIsAnyNonBEPkts =FALSE;
4271
4272         ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Orginial VO PARAM: 0x%x\n",ODM_Read4Byte(pDM_Odm,ODM_EDCA_VO_PARAM)));
4273         ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Orginial VI PARAM: 0x%x\n",ODM_Read4Byte(pDM_Odm,ODM_EDCA_VI_PARAM)));
4274         ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Orginial BE PARAM: 0x%x\n",ODM_Read4Byte(pDM_Odm,ODM_EDCA_BE_PARAM)));
4275         ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Orginial BK PARAM: 0x%x\n",ODM_Read4Byte(pDM_Odm,ODM_EDCA_BK_PARAM)));
4276
4277
4278 }       // ODM_InitEdcaTurbo
4279
4280 void
4281 odm_EdcaTurboCheck(
4282                 PDM_ODM_T               pDM_Odm
4283         )
4284 {
4285         //
4286         // For AP/ADSL use prtl8192cd_priv
4287         // For CE/NIC use PADAPTER
4288         //
4289         PADAPTER                pAdapter = pDM_Odm->Adapter;
4290         prtl8192cd_priv priv            = pDM_Odm->priv;
4291
4292         //
4293         // 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate
4294         // at the same time. In the stage2/3, we need to prive universal interface and merge all
4295         // HW dynamic mechanism.
4296         //
4297         ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("odm_EdcaTurboCheck========================>\n"));
4298
4299         if(!(pDM_Odm->SupportAbility& ODM_MAC_EDCA_TURBO ))
4300                 return;
4301
4302         switch  (pDM_Odm->SupportPlatform)
4303         {
4304                 case    ODM_MP:
4305                         break;
4306
4307                 case    ODM_CE:
4308                         odm_EdcaTurboCheckCE(pDM_Odm);
4309                         break;
4310
4311                 case    ODM_AP:
4312                 case    ODM_ADSL:
4313                         break;
4314         }
4315         ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("<========================odm_EdcaTurboCheck\n"));
4316
4317 }       // odm_CheckEdcaTurbo
4318
4319 void
4320 odm_EdcaTurboCheckCE(
4321                 PDM_ODM_T               pDM_Odm
4322         )
4323 {
4324         PADAPTER                       Adapter = pDM_Odm->Adapter;
4325
4326         u32     trafficIndex;
4327         u32     edca_param;
4328         u64     cur_tx_bytes = 0;
4329         u64     cur_rx_bytes = 0;
4330         u8      bbtchange = _FALSE;
4331         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);
4332         struct xmit_priv                *pxmitpriv = &(Adapter->xmitpriv);
4333         struct recv_priv                *precvpriv = &(Adapter->recvpriv);
4334         struct registry_priv    *pregpriv = &Adapter->registrypriv;
4335         struct mlme_ext_priv    *pmlmeext = &(Adapter->mlmeextpriv);
4336         struct mlme_ext_info    *pmlmeinfo = &(pmlmeext->mlmext_info);
4337
4338
4339         if ((pregpriv->wifi_spec == 1) )//|| (pmlmeinfo->HT_enable == 0))
4340         {
4341                 goto dm_CheckEdcaTurbo_EXIT;
4342         }
4343
4344         if (pmlmeinfo->assoc_AP_vendor >=  HT_IOT_PEER_MAX)
4345         {
4346                 goto dm_CheckEdcaTurbo_EXIT;
4347         }
4348
4349 #ifdef CONFIG_BT_COEXIST
4350         if (BT_DisableEDCATurbo(Adapter))
4351         {
4352                 goto dm_CheckEdcaTurbo_EXIT;
4353         }
4354 #endif
4355
4356         // Check if the status needs to be changed.
4357         if((bbtchange) || (!precvpriv->bIsAnyNonBEPkts) )
4358         {
4359                 cur_tx_bytes = pxmitpriv->tx_bytes - pxmitpriv->last_tx_bytes;
4360                 cur_rx_bytes = precvpriv->rx_bytes - precvpriv->last_rx_bytes;
4361
4362                 //traffic, TX or RX
4363                 if((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_RALINK)||(pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_ATHEROS))
4364                 {
4365                         if (cur_tx_bytes > (cur_rx_bytes << 2))
4366                         { // Uplink TP is present.
4367                                 trafficIndex = UP_LINK;
4368                         }
4369                         else
4370                         { // Balance TP is present.
4371                                 trafficIndex = DOWN_LINK;
4372                         }
4373                 }
4374                 else
4375                 {
4376                         if (cur_rx_bytes > (cur_tx_bytes << 2))
4377                         { // Downlink TP is present.
4378                                 trafficIndex = DOWN_LINK;
4379                         }
4380                         else
4381                         { // Balance TP is present.
4382                                 trafficIndex = UP_LINK;
4383                         }
4384                 }
4385
4386                 if ((pDM_Odm->DM_EDCA_Table.prv_traffic_idx != trafficIndex) || (!pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA))
4387                 {
4388                         if((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_CISCO) && (pmlmeext->cur_wireless_mode & WIRELESS_11_24N))
4389                         {
4390                                 edca_param = EDCAParam[pmlmeinfo->assoc_AP_vendor][trafficIndex];
4391                         }
4392                         else
4393                         {
4394                                 edca_param = EDCAParam[HT_IOT_PEER_UNKNOWN][trafficIndex];
4395                         }
4396                         rtw_write32(Adapter, REG_EDCA_BE_PARAM, edca_param);
4397
4398                         pDM_Odm->DM_EDCA_Table.prv_traffic_idx = trafficIndex;
4399                 }
4400
4401                 pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = _TRUE;
4402         }
4403         else
4404         {
4405                 //
4406                 // Turn Off EDCA turbo here.
4407                 // Restore original EDCA according to the declaration of AP.
4408                 //
4409                  if(pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA)
4410                 {
4411                         rtw_write32(Adapter, REG_EDCA_BE_PARAM, pHalData->AcParam_BE);
4412                         pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = _FALSE;
4413                 }
4414         }
4415
4416 dm_CheckEdcaTurbo_EXIT:
4417         // Set variables for next time.
4418         precvpriv->bIsAnyNonBEPkts = _FALSE;
4419         pxmitpriv->last_tx_bytes = pxmitpriv->tx_bytes;
4420         precvpriv->last_rx_bytes = precvpriv->rx_bytes;
4421 }
4422
4423
4424 // need to ODM CE Platform
4425 //move to here for ANT detection mechanism using
4426
4427 u4Byte
4428 GetPSDData(
4429  PDM_ODM_T      pDM_Odm,
4430         unsigned int    point,
4431         u8 initial_gain_psd)
4432 {
4433         //unsigned int  val, rfval;
4434         //int   psd_report;
4435         u4Byte  psd_report;
4436
4437         //HAL_DATA_TYPE         *pHalData = GET_HAL_DATA(Adapter);
4438         //Debug Message
4439         //val = PHY_QueryBBReg(Adapter,0x908, bMaskDWord);
4440         //DbgPrint("Reg908 = 0x%x\n",val);
4441         //val = PHY_QueryBBReg(Adapter,0xDF4, bMaskDWord);
4442         //rfval = PHY_QueryRFReg(Adapter, RF_PATH_A, 0x00, bRFRegOffsetMask);
4443         //DbgPrint("RegDF4 = 0x%x, RFReg00 = 0x%x\n",val, rfval);
4444         //DbgPrint("PHYTXON = %x, OFDMCCA_PP = %x, CCKCCA_PP = %x, RFReg00 = %x\n",
4445                 //(val&BIT25)>>25, (val&BIT14)>>14, (val&BIT15)>>15, rfval);
4446
4447         //Set DCO frequency index, offset=(40MHz/SamplePts)*point
4448         ODM_SetBBReg(pDM_Odm, 0x808, 0x3FF, point);
4449
4450         //Start PSD calculation, Reg808[22]=0->1
4451         ODM_SetBBReg(pDM_Odm, 0x808, BIT22, 1);
4452         //Need to wait for HW PSD report
4453         ODM_StallExecution(30);
4454         ODM_SetBBReg(pDM_Odm, 0x808, BIT22, 0);
4455         //Read PSD report, Reg8B4[15:0]
4456         psd_report = ODM_GetBBReg(pDM_Odm,0x8B4, bMaskDWord) & 0x0000FFFF;
4457
4458 #if 1//(DEV_BUS_TYPE == RT_PCI_INTERFACE) && ( (RT_PLATFORM == PLATFORM_LINUX) || (RT_PLATFORM == PLATFORM_MACOSX))
4459         psd_report = (u4Byte) (ConvertTo_dB(psd_report))+(u4Byte)(initial_gain_psd-0x1c);
4460 #else
4461         psd_report = (int) (20*log10((double)psd_report))+(int)(initial_gain_psd-0x1c);
4462 #endif
4463
4464         return psd_report;
4465
4466 }
4467
4468 u4Byte
4469 ConvertTo_dB(
4470         u4Byte  Value)
4471 {
4472         u8 i;
4473         u8 j;
4474         u4Byte dB;
4475
4476         Value = Value & 0xFFFF;
4477
4478         for (i=0;i<8;i++)
4479         {
4480                 if (Value <= dB_Invert_Table[i][11])
4481                 {
4482                         break;
4483                 }
4484         }
4485
4486         if (i >= 8)
4487         {
4488                 return (96);    // maximum 96 dB
4489         }
4490
4491         for (j=0;j<12;j++)
4492         {
4493                 if (Value <= dB_Invert_Table[i][j])
4494                 {
4495                         break;
4496                 }
4497         }
4498
4499         dB = i*12 + j + 1;
4500
4501         return (dB);
4502 }
4503
4504 //
4505 // 2011/09/22 MH Add for 92D global spin lock utilization.
4506 //
4507 void
4508 odm_GlobalAdapterCheck(
4509                 void
4510         )
4511 {
4512 }       // odm_GlobalAdapterCheck
4513
4514
4515 //
4516 // Description:
4517 //      Set Single/Dual Antenna default setting for products that do not do detection in advance.
4518 //
4519 // Added by Joseph, 2012.03.22
4520 //
4521 void
4522 ODM_SingleDualAntennaDefaultSetting(
4523                 PDM_ODM_T               pDM_Odm
4524         )
4525 {
4526         pSWAT_T         pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
4527         pDM_SWAT_Table->ANTA_ON=TRUE;
4528         pDM_SWAT_Table->ANTB_ON=TRUE;
4529 }
4530
4531
4532 //2 8723A ANT DETECT
4533
4534
4535 void
4536 odm_PHY_SaveAFERegisters(
4537         PDM_ODM_T       pDM_Odm,
4538         pu4Byte         AFEReg,
4539         pu4Byte         AFEBackup,
4540         u4Byte          RegisterNum
4541         )
4542 {
4543         u4Byte  i;
4544
4545         //RTPRINT(FINIT, INIT_IQK, ("Save ADDA parameters.\n"));
4546         for( i = 0 ; i < RegisterNum ; i++){
4547                 AFEBackup[i] = ODM_GetBBReg(pDM_Odm, AFEReg[i], bMaskDWord);
4548         }
4549 }
4550
4551 void
4552 odm_PHY_ReloadAFERegisters(
4553         PDM_ODM_T       pDM_Odm,
4554         pu4Byte         AFEReg,
4555         pu4Byte         AFEBackup,
4556         u4Byte          RegiesterNum
4557         )
4558 {
4559         u4Byte  i;
4560
4561         //RTPRINT(FINIT, INIT_IQK, ("Reload ADDA power saving parameters !\n"));
4562         for(i = 0 ; i < RegiesterNum; i++)
4563         {
4564
4565                 ODM_SetBBReg(pDM_Odm, AFEReg[i], bMaskDWord, AFEBackup[i]);
4566         }
4567 }
4568
4569 //2 8723A ANT DETECT
4570 //
4571 // Description:
4572 //      Implement IQK single tone for RF DPK loopback and BB PSD scanning.
4573 //      This function is cooperated with BB team Neil.
4574 //
4575 // Added by Roger, 2011.12.15
4576 //
4577 bool
4578 ODM_SingleDualAntennaDetection(
4579                 PDM_ODM_T               pDM_Odm,
4580                 u8                      mode
4581         )
4582 {
4583
4584         //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
4585         //PDM_ODM_T             pDM_Odm = &pHalData->DM_OutSrc;
4586         pSWAT_T         pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
4587         u4Byte          CurrentChannel,RfLoopReg;
4588         u8              n;
4589         u4Byte          Reg88c, Regc08, Reg874, Regc50;
4590         u8              initial_gain = 0x5a;
4591         u4Byte          PSD_report_tmp;
4592         u4Byte          AntA_report = 0x0, AntB_report = 0x0,AntO_report=0x0;
4593         bool            bResult = TRUE;
4594         u4Byte          AFE_Backup[16];
4595         u4Byte          AFE_REG_8723A[16] = {
4596                                         rRx_Wait_CCA,   rTx_CCK_RFON,
4597                                         rTx_CCK_BBON,   rTx_OFDM_RFON,
4598                                         rTx_OFDM_BBON,  rTx_To_Rx,
4599                                         rTx_To_Tx,              rRx_CCK,
4600                                         rRx_OFDM,               rRx_Wait_RIFS,
4601                                         rRx_TO_Rx,              rStandby,
4602                                         rSleep,                 rPMPD_ANAEN,
4603                                         rFPGA0_XCD_SwitchControl, rBlue_Tooth};
4604
4605         if(!(pDM_Odm->SupportICType & (ODM_RTL8723A|ODM_RTL8192C)))
4606                 return bResult;
4607
4608         if(!(pDM_Odm->SupportAbility&ODM_BB_ANT_DIV))
4609                 return bResult;
4610
4611         if(pDM_Odm->SupportICType == ODM_RTL8192C)
4612         {
4613                 //Which path in ADC/DAC is turnned on for PSD: both I/Q
4614                 ODM_SetBBReg(pDM_Odm, 0x808, BIT10|BIT11, 0x3);
4615                 //Ageraged number: 8
4616                 ODM_SetBBReg(pDM_Odm, 0x808, BIT12|BIT13, 0x1);
4617                 //pts = 128;
4618                 ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x0);
4619         }
4620
4621         //1 Backup Current RF/BB Settings
4622
4623         CurrentChannel = ODM_GetRFReg(pDM_Odm, RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask);
4624         RfLoopReg = ODM_GetRFReg(pDM_Odm, RF_PATH_A, 0x00, bRFRegOffsetMask);
4625         ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, ODM_DPDT, Antenna_A);  // change to Antenna A
4626         // Step 1: USE IQK to transmitter single tone
4627
4628         ODM_StallExecution(10);
4629
4630         //Store A Path Register 88c, c08, 874, c50
4631         Reg88c = ODM_GetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord);
4632         Regc08 = ODM_GetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord);
4633         Reg874 = ODM_GetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord);
4634         Regc50 = ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskDWord);
4635
4636         // Store AFE Registers
4637         odm_PHY_SaveAFERegisters(pDM_Odm, AFE_REG_8723A, AFE_Backup, 16);
4638
4639         //Set PSD 128 pts
4640         ODM_SetBBReg(pDM_Odm, rFPGA0_PSDFunction, BIT14|BIT15, 0x0);  //128 pts
4641
4642         // To SET CH1 to do
4643         ODM_SetRFReg(pDM_Odm, RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask, 0x01);     //Channel 1
4644
4645         // AFE all on step
4646         ODM_SetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord, 0x6FDB25A4);
4647         ODM_SetBBReg(pDM_Odm, rTx_CCK_RFON, bMaskDWord, 0x6FDB25A4);
4648         ODM_SetBBReg(pDM_Odm, rTx_CCK_BBON, bMaskDWord, 0x6FDB25A4);
4649         ODM_SetBBReg(pDM_Odm, rTx_OFDM_RFON, bMaskDWord, 0x6FDB25A4);
4650         ODM_SetBBReg(pDM_Odm, rTx_OFDM_BBON, bMaskDWord, 0x6FDB25A4);
4651         ODM_SetBBReg(pDM_Odm, rTx_To_Rx, bMaskDWord, 0x6FDB25A4);
4652         ODM_SetBBReg(pDM_Odm, rTx_To_Tx, bMaskDWord, 0x6FDB25A4);
4653         ODM_SetBBReg(pDM_Odm, rRx_CCK, bMaskDWord, 0x6FDB25A4);
4654         ODM_SetBBReg(pDM_Odm, rRx_OFDM, bMaskDWord, 0x6FDB25A4);
4655         ODM_SetBBReg(pDM_Odm, rRx_Wait_RIFS, bMaskDWord, 0x6FDB25A4);
4656         ODM_SetBBReg(pDM_Odm, rRx_TO_Rx, bMaskDWord, 0x6FDB25A4);
4657         ODM_SetBBReg(pDM_Odm, rStandby, bMaskDWord, 0x6FDB25A4);
4658         ODM_SetBBReg(pDM_Odm, rSleep, bMaskDWord, 0x6FDB25A4);
4659         ODM_SetBBReg(pDM_Odm, rPMPD_ANAEN, bMaskDWord, 0x6FDB25A4);
4660         ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_SwitchControl, bMaskDWord, 0x6FDB25A4);
4661         ODM_SetBBReg(pDM_Odm, rBlue_Tooth, bMaskDWord, 0x6FDB25A4);
4662
4663         // 3 wire Disable
4664         ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord, 0xCCF000C0);
4665
4666         //BB IQK Setting
4667         ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, 0x000800E4);
4668         ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22208000);
4669
4670         //IQK setting tone@ 4.34Mhz
4671         ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x10008C1C);
4672         ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00);
4673
4674
4675         //Page B init
4676         ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00080000);
4677         ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x0f600000);
4678         ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800);
4679         ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x10008c1f);
4680         ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82150008);
4681         ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28150008);
4682         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x001028d0);
4683
4684         //RF loop Setting
4685         ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x0, 0xFFFFF, 0x50008);
4686
4687         //IQK Single tone start
4688         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x80800000);
4689         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
4690         ODM_StallExecution(1000);
4691         PSD_report_tmp=0x0;
4692
4693         for (n=0;n<2;n++)
4694         {
4695                 PSD_report_tmp =  GetPSDData(pDM_Odm, 14, initial_gain);
4696                 if(PSD_report_tmp >AntA_report)
4697                         AntA_report=PSD_report_tmp;
4698         }
4699
4700         PSD_report_tmp=0x0;
4701
4702         ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_B);  // change to Antenna B
4703         ODM_StallExecution(10);
4704
4705
4706         for (n=0;n<2;n++)
4707         {
4708                 PSD_report_tmp =  GetPSDData(pDM_Odm, 14, initial_gain);
4709                 if(PSD_report_tmp > AntB_report)
4710                         AntB_report=PSD_report_tmp;
4711         }
4712
4713         // change to open case
4714         ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, 0x300, 0);  // change to Ant A and B all open case
4715         ODM_StallExecution(10);
4716
4717         for (n=0;n<2;n++)
4718         {
4719                 PSD_report_tmp =  GetPSDData(pDM_Odm, 14, initial_gain);
4720                 if(PSD_report_tmp > AntO_report)
4721                         AntO_report=PSD_report_tmp;
4722         }
4723
4724         //Close IQK Single Tone function
4725         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000);
4726         PSD_report_tmp = 0x0;
4727
4728         //1 Return to antanna A
4729         ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_A);
4730         ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord, Reg88c);
4731         ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, Regc08);
4732         ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, Reg874);
4733         ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, 0x7F, 0x40);
4734         ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskDWord, Regc50);
4735         ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask,CurrentChannel);
4736         ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x00, bRFRegOffsetMask,RfLoopReg);
4737
4738         //Reload AFE Registers
4739         odm_PHY_ReloadAFERegisters(pDM_Odm, AFE_REG_8723A, AFE_Backup, 16);
4740
4741         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_A[%d]= %d \n", 2416, AntA_report));
4742         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_B[%d]= %d \n", 2416, AntB_report));
4743         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_O[%d]= %d \n", 2416, AntO_report));
4744
4745
4746         if(pDM_Odm->SupportICType == ODM_RTL8723A)
4747         {
4748         //2 Test Ant B based on Ant A is ON
4749         if(mode==ANTTESTB)
4750         {
4751         if(AntA_report >=       100)
4752         {
4753                 if(AntB_report > (AntA_report+1))
4754                 {
4755                         pDM_SWAT_Table->ANTB_ON=FALSE;
4756                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Single Antenna A\n"));
4757                 }
4758                 else
4759                 {
4760                         pDM_SWAT_Table->ANTB_ON=TRUE;
4761                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Dual Antenna is A and B\n"));
4762                 }
4763         }
4764         else
4765         {
4766                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Need to check again\n"));
4767                 pDM_SWAT_Table->ANTB_ON=FALSE; // Set Antenna B off as default
4768                 bResult = FALSE;
4769         }
4770         }
4771         //2 Test Ant A and B based on DPDT Open
4772         else if(mode==ANTTESTALL)
4773         {
4774                 if((AntO_report >=100)&(AntO_report <118))
4775                 {
4776                         if(AntA_report > (AntO_report+1))
4777                         {
4778                                 pDM_SWAT_Table->ANTA_ON=FALSE;
4779                                 //RT_TRACE(COMP_ANTENNA, DBG_LOUD, ("ODM_AntennaDetection(): Antenna A is OFF\n"));
4780                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("Ant A is OFF"));
4781                         }
4782                         else
4783                         {
4784                                 pDM_SWAT_Table->ANTA_ON=TRUE;
4785                                 //RT_TRACE(COMP_ANTENNA, DBG_LOUD, ("ODM_AntennaDetection(): Antenna A is ON\n"));
4786                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("Ant A is ON"));
4787                         }
4788
4789                                 if(AntB_report > (AntO_report+2))
4790                         {
4791                                 pDM_SWAT_Table->ANTB_ON=FALSE;
4792                                 //RT_TRACE(COMP_ANTENNA, DBG_LOUD, ("ODM_AntennaDetection(): Antenna B is OFF\n"));
4793                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("Ant B is OFF"));
4794                         }
4795                         else
4796                         {
4797                                 pDM_SWAT_Table->ANTB_ON=TRUE;
4798                                 //RT_TRACE(COMP_ANTENNA, DBG_LOUD, ("ODM_AntennaDetection(): Antenna B is ON\n"));
4799                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("Ant B is ON"));
4800                         }
4801                 }
4802         }
4803         }
4804         else if(pDM_Odm->SupportICType == ODM_RTL8192C)
4805         {
4806                 if(AntA_report >=       100)
4807                 {
4808                         if(AntB_report > (AntA_report+2))
4809                         {
4810                                 pDM_SWAT_Table->ANTA_ON=FALSE;
4811                                 pDM_SWAT_Table->ANTB_ON=TRUE;
4812                                 ODM_SetBBReg(pDM_Odm,  rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_B);
4813                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Single Antenna B\n"));
4814                         }
4815                         else if(AntA_report > (AntB_report+2))
4816                         {
4817                                 pDM_SWAT_Table->ANTA_ON=TRUE;
4818                                 pDM_SWAT_Table->ANTB_ON=FALSE;
4819                                 ODM_SetBBReg(pDM_Odm,  rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_A);
4820                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Single Antenna A\n"));
4821                         }
4822                         else
4823                         {
4824                                 pDM_SWAT_Table->ANTA_ON=TRUE;
4825                                 pDM_SWAT_Table->ANTB_ON=TRUE;
4826                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Dual Antenna \n"));
4827                         }
4828                 }
4829                 else
4830                 {
4831                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Need to check again\n"));
4832                         pDM_SWAT_Table->ANTA_ON=TRUE; // Set Antenna A on as default
4833                         pDM_SWAT_Table->ANTB_ON=FALSE; // Set Antenna B off as default
4834                         bResult = FALSE;
4835                 }
4836         }
4837         return bResult;
4838
4839 }
4840
4841 /* Justin: According to the current RRSI to adjust Response Frame TX power, 2012/11/05 */
4842 void odm_dtc(PDM_ODM_T pDM_Odm)
4843 {
4844 #ifdef CONFIG_DM_RESP_TXAGC
4845         #define DTC_BASE            35  /* RSSI higher than this value, start to decade TX power */
4846         #define DTC_DWN_BASE       (DTC_BASE-5) /* RSSI lower than this value, start to increase TX power */
4847
4848         /* RSSI vs TX power step mapping: decade TX power */
4849         static const u8 dtc_table_down[]={
4850                 DTC_BASE,
4851                 (DTC_BASE+5),
4852                 (DTC_BASE+10),
4853                 (DTC_BASE+15),
4854                 (DTC_BASE+20),
4855                 (DTC_BASE+25)
4856         };
4857
4858         /* RSSI vs TX power step mapping: increase TX power */
4859         static const u8 dtc_table_up[]={
4860                 DTC_DWN_BASE,
4861                 (DTC_DWN_BASE-5),
4862                 (DTC_DWN_BASE-10),
4863                 (DTC_DWN_BASE-15),
4864                 (DTC_DWN_BASE-15),
4865                 (DTC_DWN_BASE-20),
4866                 (DTC_DWN_BASE-20),
4867                 (DTC_DWN_BASE-25),
4868                 (DTC_DWN_BASE-25),
4869                 (DTC_DWN_BASE-30),
4870                 (DTC_DWN_BASE-35)
4871         };
4872
4873         u8 i;
4874         u8 dtc_steps=0;
4875         u8 sign;
4876         u8 resp_txagc=0;
4877
4878         if (DTC_BASE < pDM_Odm->RSSI_Min) {
4879                 /* need to decade the CTS TX power */
4880                 sign = 1;
4881                 for (i=0;i<ARRAY_SIZE(dtc_table_down);i++)
4882                 {
4883                         if ((dtc_table_down[i] >= pDM_Odm->RSSI_Min) || (dtc_steps >= 6))
4884                                 break;
4885                         else
4886                                 dtc_steps++;
4887                 }
4888         }
4889         else
4890         {
4891                 sign = 0;
4892                 dtc_steps = 0;
4893         }
4894
4895         resp_txagc = dtc_steps | (sign << 4);
4896         resp_txagc = resp_txagc | (resp_txagc << 5);
4897         ODM_Write1Byte(pDM_Odm, 0x06d9, resp_txagc);
4898
4899         DBG_8723A("%s RSSI_Min:%u, set RESP_TXAGC to %s %u\n",
4900                 __func__, pDM_Odm->RSSI_Min, sign?"minus":"plus", dtc_steps);
4901 #endif /* CONFIG_RESP_TXAGC_ADJUST */
4902 }