include/odm.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
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   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
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  15  * this program; if not, write to the Free Software Foundation, Inc.,
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  20
  21
  22 #ifndef __HALDMOUTSRC_H__
  23 #define __HALDMOUTSRC_H__
  24
  25 //============================================================
  26 // Definition
  27 //============================================================
  28 //
  29 // 2011/09/22 MH Define all team supprt ability.
  30 //
  31
  32 //
  33 // 2011/09/22 MH Define for all teams. Please Define the constan in your precomp header.
  34 //
  35 //#define               DM_ODM_SUPPORT_AP                       0
  36 //#define               DM_ODM_SUPPORT_ADSL                     0
  37 //#define               DM_ODM_SUPPORT_CE                       0
  38 //#define               DM_ODM_SUPPORT_MP                       1
  39
  40 //
  41 // 2011/09/28 MH Define ODM SW team support flag.
  42 //
  43
  44
  45
  46 //
  47 // Antenna Switch Relative Definition.
  48 //
  49
  50 //
  51 // 20100503 Joseph:
  52 // Add new function SwAntDivCheck8192C().
  53 // This is the main function of Antenna diversity function before link.
  54 // Mainly, it just retains last scan result and scan again.
  55 // After that, it compares the scan result to see which one gets better RSSI.
  56 // It selects antenna with better receiving power and returns better scan result.
  57 //
  58 #define TP_MODE         0
  59 #define RSSI_MODE               1
  60 #define TRAFFIC_LOW     0
  61 #define TRAFFIC_HIGH    1
  62
  63
  64 //============================================================
  65 //3 Tx Power Tracking
  66 //3============================================================
  67 #define         DPK_DELTA_MAPPING_NUM   13
  68 #define         index_mapping_HP_NUM    15
  69
  70
  71 //============================================================
  72 //3 PSD Handler
  73 //3============================================================
  74
  75 #define AFH_PSD         1       //0:normal PSD scan, 1: only do 20 pts PSD
  76 #define MODE_40M                0       //0:20M, 1:40M
  77 #define PSD_TH2         3
  78 #define PSD_CHMIN               20   // Minimum channel number for BT AFH
  79 #define SIR_STEP_SIZE   3
  80 #define   Smooth_Size_1         5
  81 #define Smooth_TH_1     3
  82 #define   Smooth_Size_2         10
  83 #define Smooth_TH_2     4
  84 #define   Smooth_Size_3         20
  85 #define Smooth_TH_3     4
  86 #define   Smooth_Step_Size 5
  87 #define Adaptive_SIR    1
  88 #if(RTL8723_FPGA_VERIFICATION == 1)
  89 #define PSD_RESCAN              1
  90 #else
  91 #define PSD_RESCAN              4
  92 #endif
  93 #define PSD_SCAN_INTERVAL       700 //ms
  94
  95
  96
  97 //8723A High Power IGI Setting
  98 #define         DM_DIG_HIGH_PWR_IGI_LOWER_BOUND 0x22
  99 #define                 DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND 0x28
 100 #define         DM_DIG_HIGH_PWR_THRESHOLD       0x3a
 101
 102 // LPS define
 103 #define DM_DIG_FA_TH0_LPS                               4 //-> 4 in lps
 104 #define DM_DIG_FA_TH1_LPS                               15 //-> 15 lps
 105 #define DM_DIG_FA_TH2_LPS                               30 //-> 30 lps
 106 #define RSSI_OFFSET_DIG                                 0x05;
 107
 108 //ANT Test
 109 #define                 ANTTESTALL              0x00            //Ant A or B will be Testing
 110 #define         ANTTESTA                0x01            //Ant A will be Testing
 111 #define         ANTTESTB                0x02            //Ant B will be testing
 112
 113
 114 //============================================================
 115 // structure and define
 116 //============================================================
 117
 118 //
 119 // 2011/09/20 MH Add for AP/ADSLpseudo DM structuer requirement.
 120 // We need to remove to other position???
 121 //
 122 typedef         struct rtl8192cd_priv {
 123         u8              temp;
 124
 125 }rtl8192cd_priv, *prtl8192cd_priv;
 126
 127
 128 typedef struct _Dynamic_Initial_Gain_Threshold_
 129 {
 130         u8              Dig_Enable_Flag;
 131         u8              Dig_Ext_Port_Stage;
 132
 133         int                     RssiLowThresh;
 134         int                     RssiHighThresh;
 135
 136         u32             FALowThresh;
 137         u32             FAHighThresh;
 138
 139         u8              CurSTAConnectState;
 140         u8              PreSTAConnectState;
 141         u8              CurMultiSTAConnectState;
 142
 143         u8              PreIGValue;
 144         u8              CurIGValue;
 145         u8              BackupIGValue;
 146
 147         s1Byte          BackoffVal;
 148         s1Byte          BackoffVal_range_max;
 149         s1Byte          BackoffVal_range_min;
 150         u8              rx_gain_range_max;
 151         u8              rx_gain_range_min;
 152         u8              Rssi_val_min;
 153
 154         u8              PreCCK_CCAThres;
 155         u8              CurCCK_CCAThres;
 156         u8              PreCCKPDState;
 157         u8              CurCCKPDState;
 158
 159         u8              LargeFAHit;
 160         u8              ForbiddenIGI;
 161         u32             Recover_cnt;
 162
 163         u8              DIG_Dynamic_MIN_0;
 164         u8              DIG_Dynamic_MIN_1;
 165         bool            bMediaConnect_0;
 166         bool            bMediaConnect_1;
 167
 168         u32             AntDiv_RSSI_max;
 169         u32             RSSI_max;
 170 }DIG_T,*pDIG_T;
 171
 172 typedef struct _Dynamic_Power_Saving_
 173 {
 174         u8              PreCCAState;
 175         u8              CurCCAState;
 176
 177         u8              PreRFState;
 178         u8              CurRFState;
 179
 180         int                 Rssi_val_min;
 181
 182         u8              initialize;
 183         u32             Reg874,RegC70,Reg85C,RegA74;
 184
 185 }PS_T,*pPS_T;
 186
 187 typedef struct _FALSE_ALARM_STATISTICS{
 188         u32     Cnt_Parity_Fail;
 189         u32     Cnt_Rate_Illegal;
 190         u32     Cnt_Crc8_fail;
 191         u32     Cnt_Mcs_fail;
 192         u32     Cnt_Ofdm_fail;
 193         u32     Cnt_Cck_fail;
 194         u32     Cnt_all;
 195         u32     Cnt_Fast_Fsync;
 196         u32     Cnt_SB_Search_fail;
 197         u32     Cnt_OFDM_CCA;
 198         u32     Cnt_CCK_CCA;
 199         u32     Cnt_CCA_all;
 200         u32     Cnt_BW_USC;     //Gary
 201         u32     Cnt_BW_LSC;     //Gary
 202 }FALSE_ALARM_STATISTICS, *PFALSE_ALARM_STATISTICS;
 203
 204 typedef struct _Dynamic_Primary_CCA{
 205         u8              PriCCA_flag;
 206         u8              intf_flag;
 207         u8              intf_type;
 208         u8              DupRTS_flag;
 209         u8              Monitor_flag;
 210 }Pri_CCA_T, *pPri_CCA_T;
 211
 212 typedef struct _RX_High_Power_
 213 {
 214         u8              RXHP_flag;
 215         u8              PSD_func_trigger;
 216         u8              PSD_bitmap_RXHP[80];
 217         u8              Pre_IGI;
 218         u8              Cur_IGI;
 219         u8              Pre_pw_th;
 220         u8              Cur_pw_th;
 221         bool            First_time_enter;
 222         bool            RXHP_enable;
 223         u8              TP_Mode;
 224         RT_TIMER        PSDTimer;
 225 }RXHP_T, *pRXHP_T;
 226
 227 #define ASSOCIATE_ENTRY_NUM                                     32 // Max size of AsocEntry[].
 228 #define ODM_ASSOCIATE_ENTRY_NUM                         ASSOCIATE_ENTRY_NUM
 229
 230 //#ifdef CONFIG_ANTENNA_DIVERSITY
 231 // This indicates two different the steps.
 232 // In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air.
 233 // In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK
 234 // with original RSSI to determine if it is necessary to switch antenna.
 235 #define SWAW_STEP_PEAK          0
 236 #define SWAW_STEP_DETERMINE     1
 237
 238 #define TP_MODE         0
 239 #define RSSI_MODE               1
 240 #define TRAFFIC_LOW     0
 241 #define TRAFFIC_HIGH    1
 242
 243 typedef struct _SW_Antenna_Switch_
 244 {
 245         u8              try_flag;
 246         s4Byte          PreRSSI;
 247         u8              CurAntenna;
 248         u8              PreAntenna;
 249         u8              RSSI_Trying;
 250         u8              TestMode;
 251         u8              bTriggerAntennaSwitch;
 252         u8              SelectAntennaMap;
 253         u8              RSSI_target;
 254
 255         // Before link Antenna Switch check
 256         u8              SWAS_NoLink_State;
 257         u32             SWAS_NoLink_BK_Reg860;
 258         bool            ANTA_ON;        //To indicate Ant A is or not
 259         bool            ANTB_ON;        //To indicate Ant B is on or not
 260
 261         s4Byte          RSSI_sum_A;
 262         s4Byte          RSSI_sum_B;
 263         s4Byte          RSSI_cnt_A;
 264         s4Byte          RSSI_cnt_B;
 265
 266         u64             lastTxOkCnt;
 267         u64             lastRxOkCnt;
 268         u64             TXByteCnt_A;
 269         u64             TXByteCnt_B;
 270         u64             RXByteCnt_A;
 271         u64             RXByteCnt_B;
 272         u8              TrafficLoad;
 273         RT_TIMER        SwAntennaSwitchTimer;
 274 /* CE Platform use
 275 #ifdef CONFIG_SW_ANTENNA_DIVERSITY
 276         _timer SwAntennaSwitchTimer;
 277         u64 lastTxOkCnt;
 278         u64 lastRxOkCnt;
 279         u64 TXByteCnt_A;
 280         u64 TXByteCnt_B;
 281         u64 RXByteCnt_A;
 282         u64 RXByteCnt_B;
 283         u8 DoubleComfirm;
 284         u8 TrafficLoad;
 285         //SW Antenna Switch
 286
 287
 288 #endif
 289 */
 290 #ifdef CONFIG_HW_ANTENNA_DIVERSITY
 291         //Hybrid Antenna Diversity
 292         u32             CCK_Ant1_Cnt[ASSOCIATE_ENTRY_NUM];
 293         u32             CCK_Ant2_Cnt[ASSOCIATE_ENTRY_NUM];
 294         u32             OFDM_Ant1_Cnt[ASSOCIATE_ENTRY_NUM];
 295         u32             OFDM_Ant2_Cnt[ASSOCIATE_ENTRY_NUM];
 296         u32             RSSI_Ant1_Sum[ASSOCIATE_ENTRY_NUM];
 297         u32             RSSI_Ant2_Sum[ASSOCIATE_ENTRY_NUM];
 298         u8              TxAnt[ASSOCIATE_ENTRY_NUM];
 299         u8              TargetSTA;
 300         u8              antsel;
 301         u8              RxIdleAnt;
 302
 303 #endif
 304
 305 }SWAT_T, *pSWAT_T;
 306 //#endif
 307
 308 typedef struct _EDCA_TURBO_
 309 {
 310         bool bCurrentTurboEDCA;
 311         bool bIsCurRDLState;
 312         u32     prv_traffic_idx; // edca turbo
 313
 314 }EDCA_T,*pEDCA_T;
 315
 316 typedef struct _ODM_RATE_ADAPTIVE
 317 {
 318         u8                              Type;                           // DM_Type_ByFW/DM_Type_ByDriver
 319         u8                              HighRSSIThresh;         // if RSSI > HighRSSIThresh     => RATRState is DM_RATR_STA_HIGH
 320         u8                              LowRSSIThresh;          // if RSSI <= LowRSSIThresh     => RATRState is DM_RATR_STA_LOW
 321         u8                              RATRState;                      // Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW
 322         u32                             LastRATR;                       // RATR Register Content
 323
 324 } ODM_RATE_ADAPTIVE, *PODM_RATE_ADAPTIVE;
 325
 326
 327 #define IQK_MAC_REG_NUM         4
 328 #define IQK_ADDA_REG_NUM                16
 329 #define IQK_BB_REG_NUM_MAX      10
 330 #if (RTL8192D_SUPPORT==1)
 331 #define IQK_BB_REG_NUM          10
 332 #else
 333 #define IQK_BB_REG_NUM          9
 334 #endif
 335 #define HP_THERMAL_NUM          8
 336
 337 #define AVG_THERMAL_NUM         8
 338 #define IQK_Matrix_REG_NUM      8
 339 #define IQK_Matrix_Settings_NUM 1+24+21
 340
 341 #define         DM_Type_ByFW                    0
 342 #define         DM_Type_ByDriver                1
 343
 344 //
 345 // Declare for common info
 346 //
 347 // Declare for common info
 348 //
 349 #define MAX_PATH_NUM_92CS               2
 350
 351 typedef struct _ODM_Phy_Status_Info_
 352 {
 353         u8              RxPWDBAll;
 354         u8              SignalQuality;   // in 0-100 index.
 355         u8              RxMIMOSignalQuality[MAX_PATH_NUM_92CS]; //EVM
 356         u8              RxMIMOSignalStrength[MAX_PATH_NUM_92CS];// in 0~100 index
 357         s1Byte          RxPower; // in dBm Translate from PWdB
 358         s1Byte          RecvSignalPower;// Real power in dBm for this packet, no beautification and aggregation. Keep this raw info to be used for the other procedures.
 359         u8              BTRxRSSIPercentage;
 360         u8              SignalStrength; // in 0-100 index.
 361         u8              RxPwr[MAX_PATH_NUM_92CS];//per-path's pwdb
 362         u8              RxSNR[MAX_PATH_NUM_92CS];//per-path's SNR
 363 }ODM_PHY_INFO_T,*PODM_PHY_INFO_T;
 364
 365
 366 typedef struct _ODM_Phy_Dbg_Info_
 367 {
 368         //ODM Write,debug info
 369         s1Byte          RxSNRdB[MAX_PATH_NUM_92CS];
 370         u64             NumQryPhyStatus;
 371         u64             NumQryPhyStatusCCK;
 372         u64             NumQryPhyStatusOFDM;
 373         //Others
 374         s4Byte          RxEVM[MAX_PATH_NUM_92CS];
 375
 376 }ODM_PHY_DBG_INFO_T;
 377
 378 typedef struct _ODM_Per_Pkt_Info_
 379 {
 380         u8              Rate;
 381         u8              StationID;
 382         bool            bPacketMatchBSSID;
 383         bool            bPacketToSelf;
 384         bool            bPacketBeacon;
 385 }ODM_PACKET_INFO_T,*PODM_PACKET_INFO_T;
 386
 387 typedef struct _ODM_Mac_Status_Info_
 388 {
 389         u8      test;
 390
 391 }ODM_MAC_INFO;
 392
 393
 394 typedef enum tag_Dynamic_ODM_Support_Ability_Type
 395 {
 396         // BB Team
 397         ODM_DIG                         = 0x00000001,
 398         ODM_HIGH_POWER          = 0x00000002,
 399         ODM_CCK_CCA_TH          = 0x00000004,
 400         ODM_FA_STATISTICS               = 0x00000008,
 401         ODM_RAMASK                      = 0x00000010,
 402         ODM_RSSI_MONITOR                = 0x00000020,
 403         ODM_SW_ANTDIV           = 0x00000040,
 404         ODM_HW_ANTDIV           = 0x00000080,
 405         ODM_BB_PWRSV                    = 0x00000100,
 406         ODM_2TPATHDIV                   = 0x00000200,
 407         ODM_1TPATHDIV                   = 0x00000400,
 408         ODM_PSD2AFH                     = 0x00000800
 409 }ODM_Ability_E;
 410
 411 //
 412 // 2011/20/20 MH For MP driver RT_WLAN_STA =  STA_INFO_T
 413 // Please declare below ODM relative info in your STA info structure.
 414 //
 415 #if 1
 416 typedef         struct _ODM_STA_INFO{
 417         // Driver Write
 418         bool            bUsed;                          // record the sta status link or not?
 419         //u8            WirelessMode;           //
 420         u8              IOTPeer;                        // Enum value.  HT_IOT_PEER_E
 421
 422         // ODM Write
 423         //1 PHY_STATUS_INFO
 424         u8              RSSI_Path[4];           //
 425         u8              RSSI_Ave;
 426         u8              RXEVM[4];
 427         u8              RXSNR[4];
 428
 429         // ODM Write
 430         //1 TX_INFO (may changed by IC)
 431         //TX_INFO_T             pTxInfo;                                // Define in IC folder. Move lower layer.
 432
 433         //
 434         //      Please use compile flag to disabe the strcutrue for other IC except 88E.
 435         //      Move To lower layer.
 436         //
 437         // ODM Write Wilson will handle this part(said by Luke.Lee)
 438         //TX_RPT_T              pTxRpt;                         // Define in IC folder. Move lower layer.
 439 }ODM_STA_INFO_T, *PODM_STA_INFO_T;
 440 #endif
 441
 442 //
 443 // 2011/10/20 MH Define Common info enum for all team.
 444 //
 445 typedef enum _ODM_Common_Info_Definition
 446 {
 447 //-------------REMOVED CASE-----------//
 448         //ODM_CMNINFO_CCK_HP,
 449         //ODM_CMNINFO_RFPATH_ENABLE,            // Define as ODM write???
 450         //ODM_CMNINFO_BT_COEXIST,                               // ODM_BT_COEXIST_E
 451         //ODM_CMNINFO_OP_MODE,                          // ODM_OPERATION_MODE_E
 452 //-------------REMOVED CASE-----------//
 453
 454         //
 455         // Fixed value:
 456         //
 457
 458         //-----------HOOK BEFORE REG INIT-----------//
 459         ODM_CMNINFO_PLATFORM = 0,
 460         ODM_CMNINFO_ABILITY,                                    // ODM_ABILITY_E
 461         ODM_CMNINFO_INTERFACE,                          // ODM_INTERFACE_E
 462         ODM_CMNINFO_MP_TEST_CHIP,
 463         ODM_CMNINFO_IC_TYPE,                                    // ODM_IC_TYPE_E
 464         ODM_CMNINFO_CUT_VER,                                    // ODM_CUT_VERSION_E
 465         ODM_CMNINFO_FAB_VER,                                    // ODM_FAB_E
 466         ODM_CMNINFO_RF_TYPE,                                    // ODM_RF_PATH_E or ODM_RF_TYPE_E?
 467         ODM_CMNINFO_BOARD_TYPE,                         // ODM_BOARD_TYPE_E
 468         ODM_CMNINFO_EXT_LNA,                                    // TRUE
 469         ODM_CMNINFO_EXT_PA,
 470         ODM_CMNINFO_EXT_TRSW,
 471         ODM_CMNINFO_PATCH_ID,                           //CUSTOMER ID
 472         ODM_CMNINFO_BINHCT_TEST,
 473         ODM_CMNINFO_BWIFI_TEST,
 474         ODM_CMNINFO_SMART_CONCURRENT,
 475         //-----------HOOK BEFORE REG INIT-----------//
 476
 477
 478         //
 479         // Dynamic value:
 480         //
 481 //--------- POINTER REFERENCE-----------//
 482         ODM_CMNINFO_MAC_PHY_MODE,                       // ODM_MAC_PHY_MODE_E
 483         ODM_CMNINFO_TX_UNI,
 484         ODM_CMNINFO_RX_UNI,
 485         ODM_CMNINFO_WM_MODE,                            // ODM_WIRELESS_MODE_E
 486         ODM_CMNINFO_BAND,                                       // ODM_BAND_TYPE_E
 487         ODM_CMNINFO_SEC_CHNL_OFFSET,            // ODM_SEC_CHNL_OFFSET_E
 488         ODM_CMNINFO_SEC_MODE,                           // ODM_SECURITY_E
 489         ODM_CMNINFO_BW,                                         // ODM_BW_E
 490         ODM_CMNINFO_CHNL,
 491
 492         ODM_CMNINFO_DMSP_GET_VALUE,
 493         ODM_CMNINFO_BUDDY_ADAPTOR,
 494         ODM_CMNINFO_DMSP_IS_MASTER,
 495         ODM_CMNINFO_SCAN,
 496         ODM_CMNINFO_POWER_SAVING,
 497         ODM_CMNINFO_ONE_PATH_CCA,                       // ODM_CCA_PATH_E
 498         ODM_CMNINFO_DRV_STOP,
 499         ODM_CMNINFO_PNP_IN,
 500         ODM_CMNINFO_INIT_ON,
 501         ODM_CMNINFO_ANT_TEST,
 502         ODM_CMNINFO_NET_CLOSED,
 503         ODM_CMNINFO_MP_MODE,
 504 //--------- POINTER REFERENCE-----------//
 505
 506 //------------CALL BY VALUE-------------//
 507         ODM_CMNINFO_WIFI_DIRECT,
 508         ODM_CMNINFO_WIFI_DISPLAY,
 509         ODM_CMNINFO_LINK,
 510         ODM_CMNINFO_RSSI_MIN,
 511         ODM_CMNINFO_DBG_COMP,                           // u64
 512         ODM_CMNINFO_DBG_LEVEL,                          // u32
 513         ODM_CMNINFO_RA_THRESHOLD_HIGH,          // u8
 514         ODM_CMNINFO_RA_THRESHOLD_LOW,           // u8
 515         ODM_CMNINFO_RF_ANTENNA_TYPE,            // u8
 516         ODM_CMNINFO_BT_DISABLED,
 517         ODM_CMNINFO_BT_OPERATION,
 518         ODM_CMNINFO_BT_DIG,
 519         ODM_CMNINFO_BT_BUSY,                                    //Check Bt is using or not//neil
 520         ODM_CMNINFO_BT_DISABLE_EDCA,
 521 //------------CALL BY VALUE-------------//
 522
 523         //
 524         // Dynamic ptr array hook itms.
 525         //
 526         ODM_CMNINFO_STA_STATUS,
 527         ODM_CMNINFO_PHY_STATUS,
 528         ODM_CMNINFO_MAC_STATUS,
 529
 530         ODM_CMNINFO_MAX,
 531
 532
 533 }ODM_CMNINFO_E;
 534
 535 //
 536 // 2011/10/20 MH Define ODM support ability.  ODM_CMNINFO_ABILITY
 537 //
 538 typedef enum _ODM_Support_Ability_Definition
 539 {
 540         //
 541         // BB ODM section BIT 0-15
 542         //
 543         ODM_BB_DIG                                      = BIT0,
 544         ODM_BB_RA_MASK                          = BIT1,
 545         ODM_BB_DYNAMIC_TXPWR            = BIT2,
 546         ODM_BB_FA_CNT                                   = BIT3,
 547         ODM_BB_RSSI_MONITOR                     = BIT4,
 548         ODM_BB_CCK_PD                                   = BIT5,
 549         ODM_BB_ANT_DIV                          = BIT6,
 550         ODM_BB_PWR_SAVE                         = BIT7,
 551         ODM_BB_PWR_TRAIN                                = BIT8,
 552         ODM_BB_RATE_ADAPTIVE                    = BIT9,
 553         ODM_BB_PATH_DIV                         = BIT10,
 554         ODM_BB_PSD                                      = BIT11,
 555         ODM_BB_RXHP                                     = BIT12,
 556
 557         //
 558         // MAC DM section BIT 16-23
 559         //
 560         ODM_MAC_EDCA_TURBO                      = BIT16,
 561         ODM_MAC_EARLY_MODE                      = BIT17,
 562
 563         //
 564         // RF ODM section BIT 24-31
 565         //
 566         ODM_RF_TX_PWR_TRACK                     = BIT24,
 567         ODM_RF_RX_GAIN_TRACK                    = BIT25,
 568         ODM_RF_CALIBRATION                              = BIT26,
 569
 570 }ODM_ABILITY_E;
 571
 572 //      ODM_CMNINFO_INTERFACE
 573 typedef enum tag_ODM_Support_Interface_Definition
 574 {
 575         ODM_ITRF_PCIE   =       0x1,
 576         ODM_ITRF_USB    =       0x2,
 577         ODM_ITRF_SDIO   =       0x4,
 578         ODM_ITRF_ALL    =       0x7,
 579 }ODM_INTERFACE_E;
 580
 581 // ODM_CMNINFO_IC_TYPE
 582 typedef enum tag_ODM_Support_IC_Type_Definition
 583 {
 584         ODM_RTL8192S    =       BIT0,
 585         ODM_RTL8192C    =       BIT1,
 586         ODM_RTL8192D    =       BIT2,
 587         ODM_RTL8723A    =       BIT3,
 588         ODM_RTL8188E    =       BIT4,
 589         ODM_RTL8812     =       BIT5,
 590         ODM_RTL8821     =       BIT6,
 591 }ODM_IC_TYPE_E;
 592
 593 #define ODM_IC_11N_SERIES               (ODM_RTL8192S|ODM_RTL8192C|ODM_RTL8192D|ODM_RTL8723A|ODM_RTL8188E)
 594 #define ODM_IC_11AC_SERIES              (ODM_RTL8812)
 595
 596 //ODM_CMNINFO_CUT_VER
 597 typedef enum tag_ODM_Cut_Version_Definition
 598 {
 599         ODM_CUT_A               =       1,
 600         ODM_CUT_B               =       2,
 601         ODM_CUT_C               =       3,
 602         ODM_CUT_D               =       4,
 603         ODM_CUT_E               =       5,
 604         ODM_CUT_F               =       6,
 605         ODM_CUT_TEST    =       7,
 606 }ODM_CUT_VERSION_E;
 607
 608 // ODM_CMNINFO_FAB_VER
 609 typedef enum tag_ODM_Fab_Version_Definition
 610 {
 611         ODM_TSMC        =       0,
 612         ODM_UMC         =       1,
 613 }ODM_FAB_E;
 614
 615 // ODM_CMNINFO_RF_TYPE
 616 //
 617 // For example 1T2R (A+AB = BIT0|BIT4|BIT5)
 618 //
 619 typedef enum tag_ODM_RF_Path_Bit_Definition
 620 {
 621         ODM_RF_TX_A     =       BIT0,
 622         ODM_RF_TX_B     =       BIT1,
 623         ODM_RF_TX_C     =       BIT2,
 624         ODM_RF_TX_D     =       BIT3,
 625         ODM_RF_RX_A     =       BIT4,
 626         ODM_RF_RX_B     =       BIT5,
 627         ODM_RF_RX_C     =       BIT6,
 628         ODM_RF_RX_D     =       BIT7,
 629 }ODM_RF_PATH_E;
 630
 631
 632 typedef enum tag_ODM_RF_Type_Definition
 633 {
 634         ODM_1T1R        =       0,
 635         ODM_1T2R        =       1,
 636         ODM_2T2R        =       2,
 637         ODM_2T3R        =       3,
 638         ODM_2T4R        =       4,
 639         ODM_3T3R        =       5,
 640         ODM_3T4R        =       6,
 641         ODM_4T4R        =       7,
 642 }ODM_RF_TYPE_E;
 643
 644
 645 //
 646 // ODM Dynamic common info value definition
 647 //
 648
 649 //typedef enum _MACPHY_MODE_8192D{
 650 //      SINGLEMAC_SINGLEPHY,
 651 //      DUALMAC_DUALPHY,
 652 //      DUALMAC_SINGLEPHY,
 653 //}MACPHY_MODE_8192D,*PMACPHY_MODE_8192D;
 654 // Above is the original define in MP driver. Please use the same define. THX.
 655 typedef enum tag_ODM_MAC_PHY_Mode_Definition
 656 {
 657         ODM_SMSP        = 0,
 658         ODM_DMSP        = 1,
 659         ODM_DMDP        = 2,
 660 }ODM_MAC_PHY_MODE_E;
 661
 662
 663 typedef enum tag_BT_Coexist_Definition
 664 {
 665         ODM_BT_BUSY             = 1,
 666         ODM_BT_ON                       = 2,
 667         ODM_BT_OFF              = 3,
 668         ODM_BT_NONE             = 4,
 669 }ODM_BT_COEXIST_E;
 670
 671 // ODM_CMNINFO_OP_MODE
 672 typedef enum tag_Operation_Mode_Definition
 673 {
 674         ODM_NO_LINK             = BIT0,
 675         ODM_LINK                        = BIT1,
 676         ODM_SCAN                        = BIT2,
 677         ODM_POWERSAVE   = BIT3,
 678         ODM_AP_MODE             = BIT4,
 679         ODM_CLIENT_MODE = BIT5,
 680         ODM_AD_HOC              = BIT6,
 681         ODM_WIFI_DIRECT = BIT7,
 682         ODM_WIFI_DISPLAY        = BIT8,
 683 }ODM_OPERATION_MODE_E;
 684
 685 // ODM_CMNINFO_WM_MODE
 686 typedef enum tag_Wireless_Mode_Definition
 687 {
 688         ODM_WM_UNKNOW   = 0x0,
 689         ODM_WM_B                        = BIT0,
 690         ODM_WM_G                        = BIT1,
 691         ODM_WM_A                        = BIT2,
 692         ODM_WM_N24G             = BIT3,
 693         ODM_WM_N5G              = BIT4,
 694         ODM_WM_AUTO             = BIT5,
 695         ODM_WM_AC               = BIT6,
 696 }ODM_WIRELESS_MODE_E;
 697
 698 // ODM_CMNINFO_BAND
 699 typedef enum tag_Band_Type_Definition
 700 {
 701         ODM_BAND_2_4G   = BIT0,
 702         ODM_BAND_5G             = BIT1,
 703
 704 }ODM_BAND_TYPE_E;
 705
 706 // ODM_CMNINFO_SEC_CHNL_OFFSET
 707 typedef enum tag_Secondary_Channel_Offset_Definition
 708 {
 709         ODM_DONT_CARE   = 0,
 710         ODM_BELOW               = 1,
 711         ODM_ABOVE                       = 2
 712 }ODM_SEC_CHNL_OFFSET_E;
 713
 714 // ODM_CMNINFO_SEC_MODE
 715 typedef enum tag_Security_Definition
 716 {
 717         ODM_SEC_OPEN                    = 0,
 718         ODM_SEC_WEP40           = 1,
 719         ODM_SEC_TKIP                    = 2,
 720         ODM_SEC_RESERVE                 = 3,
 721         ODM_SEC_AESCCMP                 = 4,
 722         ODM_SEC_WEP104          = 5,
 723         ODM_WEP_WPA_MIXED    = 6, // WEP + WPA
 724         ODM_SEC_SMS4                    = 7,
 725 }ODM_SECURITY_E;
 726
 727 // ODM_CMNINFO_BW
 728 typedef enum tag_Bandwidth_Definition
 729 {
 730         ODM_BW20M               = 0,
 731         ODM_BW40M               = 1,
 732         ODM_BW80M               = 2,
 733         ODM_BW160M              = 3,
 734         ODM_BW10M               = 4,
 735 }ODM_BW_E;
 736
 737 // ODM_CMNINFO_CHNL
 738
 739 // ODM_CMNINFO_BOARD_TYPE
 740 typedef enum tag_Board_Definition
 741 {
 742         ODM_BOARD_NORMAL        = 0,
 743         ODM_BOARD_HIGHPWR       = 1,
 744         ODM_BOARD_MINICARD      = 2,
 745         ODM_BOARD_SLIM          = 3,
 746         ODM_BOARD_COMBO         = 4,
 747
 748 }ODM_BOARD_TYPE_E;
 749
 750 // ODM_CMNINFO_ONE_PATH_CCA
 751 typedef enum tag_CCA_Path
 752 {
 753         ODM_CCA_2R                      = 0,
 754         ODM_CCA_1R_A                    = 1,
 755         ODM_CCA_1R_B                    = 2,
 756 }ODM_CCA_PATH_E;
 757
 758
 759 typedef struct _ODM_RA_Info_
 760 {
 761         u8 RateID;
 762         u32 RateMask;
 763         u32 RAUseRate;
 764         u8 RateSGI;
 765         u8 RssiStaRA;
 766         u8 PreRssiStaRA;
 767         u8 SGIEnable;
 768         u8 DecisionRate;
 769         u8 PreRate;
 770         u8 HighestRate;
 771         u8 LowestRate;
 772         u32 NscUp;
 773         u32 NscDown;
 774         u16 RTY[5];
 775         u32 TOTAL;
 776         u16 DROP;
 777         u8 Active;
 778         u16 RptTime;
 779         u8 RAWaitingCounter;
 780         u8 RAPendingCounter;
 781 #if 1 //POWER_TRAINING_ACTIVE == 1 // For compile  pass only~!
 782         u8 PTActive;  // on or off
 783         u8 PTTryState;  // 0 trying state, 1 for decision state
 784         u8 PTStage;  // 0~6
 785         u8 PTStopCount; //Stop PT counter
 786         u8 PTPreRate;  // if rate change do PT
 787         u8 PTPreRssi; // if RSSI change 5% do PT
 788         u8 PTModeSS;  // decide whitch rate should do PT
 789         u8 RAstage;  // StageRA, decide how many times RA will be done between PT
 790         u8 PTSmoothFactor;
 791 #endif
 792 } ODM_RA_INFO_T,*PODM_RA_INFO_T;
 793
 794 typedef struct _IQK_MATRIX_REGS_SETTING{
 795         bool    bIQKDone;
 796         s4Byte          Value[1][IQK_Matrix_REG_NUM];
 797 }IQK_MATRIX_REGS_SETTING,*PIQK_MATRIX_REGS_SETTING;
 798
 799
 800 typedef struct ODM_RF_Calibration_Structure
 801 {
 802         //for tx power tracking
 803
 804         u32     RegA24; // for TempCCK
 805         s4Byte  RegE94;
 806         s4Byte  RegE9C;
 807         s4Byte  RegEB4;
 808         s4Byte  RegEBC;
 809
 810         //u8 bTXPowerTracking;
 811         u8              TXPowercount;
 812         bool bTXPowerTrackingInit;
 813         bool bTXPowerTracking;
 814         u8              TxPowerTrackControl; //for mp mode, turn off txpwrtracking as default
 815         u8              TM_Trigger;
 816         u8              InternalPA5G[2];        //pathA / pathB
 817
 818         u8              ThermalMeter[2];    // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1
 819         u8              ThermalValue;
 820         u8              ThermalValue_LCK;
 821         u8              ThermalValue_IQK;
 822         u8      ThermalValue_DPK;
 823         u8      ThermalValue_AVG[AVG_THERMAL_NUM];
 824         u8      ThermalValue_AVG_index;
 825         u8      ThermalValue_RxGain;
 826         u8      ThermalValue_Crystal;
 827         u8      ThermalValue_DPKstore;
 828         u8      ThermalValue_DPKtrack;
 829         bool    TxPowerTrackingInProgress;
 830         bool    bDPKenable;
 831
 832         bool    bReloadtxpowerindex;
 833         u8      bRfPiEnable;
 834         u32     TXPowerTrackingCallbackCnt; //cosa add for debug
 835
 836         u8      bCCKinCH14;
 837         u8      CCK_index;
 838         u8      OFDM_index[2];
 839         bool bDoneTxpower;
 840
 841         u8      ThermalValue_HP[HP_THERMAL_NUM];
 842         u8      ThermalValue_HP_index;
 843         IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM];
 844
 845         u8      Delta_IQK;
 846         u8      Delta_LCK;
 847
 848         //for IQK
 849         u32     RegC04;
 850         u32     Reg874;
 851         u32     RegC08;
 852         u32     RegB68;
 853         u32     RegB6C;
 854         u32     Reg870;
 855         u32     Reg860;
 856         u32     Reg864;
 857
 858         bool    bIQKInitialized;
 859         bool bLCKInProgress;
 860         bool    bAntennaDetected;
 861         u32     ADDA_backup[IQK_ADDA_REG_NUM];
 862         u32     IQK_MAC_backup[IQK_MAC_REG_NUM];
 863         u32     IQK_BB_backup_recover[9];
 864         u32     IQK_BB_backup[IQK_BB_REG_NUM];
 865
 866         //for APK
 867         u32     APKoutput[2][2]; //path A/B; output1_1a/output1_2a
 868         u8      bAPKdone;
 869         u8      bAPKThermalMeterIgnore;
 870         u8      bDPdone;
 871         u8      bDPPathAOK;
 872         u8      bDPPathBOK;
 873 }ODM_RF_CAL_T,*PODM_RF_CAL_T;
 874 //
 875 // ODM Dynamic common info value definition
 876 //
 877
 878 typedef struct _FAST_ANTENNA_TRAINNING_
 879 {
 880         u8      Bssid[6];
 881         u8      antsel_rx_keep_0;
 882         u8      antsel_rx_keep_1;
 883         u8      antsel_rx_keep_2;
 884         u32     antSumRSSI[7];
 885         u32     antRSSIcnt[7];
 886         u32     antAveRSSI[7];
 887         u8      FAT_State;
 888         u32     TrainIdx;
 889         u8      antsel_a[ODM_ASSOCIATE_ENTRY_NUM];
 890         u8      antsel_b[ODM_ASSOCIATE_ENTRY_NUM];
 891         u8      antsel_c[ODM_ASSOCIATE_ENTRY_NUM];
 892         u32     MainAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
 893         u32     AuxAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
 894         u32     MainAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
 895         u32     AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
 896         u8      RxIdleAnt;
 897         bool            bBecomeLinked;
 898
 899 }FAT_T,*pFAT_T;
 900
 901 typedef enum _FAT_STATE
 902 {
 903         FAT_NORMAL_STATE                        = 0,
 904         FAT_TRAINING_STATE              = 1,
 905 }FAT_STATE_E, *PFAT_STATE_E;
 906
 907 typedef enum _ANT_DIV_TYPE
 908 {
 909         NO_ANTDIV                                       = 0xFF,
 910         CG_TRX_HW_ANTDIV                        = 0x01,
 911         CGCS_RX_HW_ANTDIV               = 0x02,
 912         FIXED_HW_ANTDIV                         = 0x03,
 913         CG_TRX_SMART_ANTDIV             = 0x04,
 914         CGCS_RX_SW_ANTDIV               = 0x05,
 915
 916 }ANT_DIV_TYPE_E, *PANT_DIV_TYPE_E;
 917
 918
 919
 920
 921
 922
 923
 924
 925
 926
 927
 928
 929
 930 //
 931 // 2011/09/22 MH Copy from SD4 defined structure. We use to support PHY DM integration.
 932 //
 933 typedef  struct DM_Out_Source_Dynamic_Mechanism_Structure
 934 {
 935         //RT_TIMER      FastAntTrainingTimer;
 936         //
 937         //      Add for different team use temporarily
 938         //
 939         PADAPTER                Adapter;                // For CE/NIC team
 940         prtl8192cd_priv priv;                   // For AP/ADSL team
 941         // WHen you use Adapter or priv pointer, you must make sure the pointer is ready.
 942         bool                    odm_ready;
 943
 944         rtl8192cd_priv          fake_priv;
 945
 946         u64                     DebugComponents;
 947         u32                     DebugLevel;
 948
 949 //------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------//
 950         bool                    bCckHighPower;
 951         u8                      RFPathRxEnable;         // ODM_CMNINFO_RFPATH_ENABLE
 952         u8                      ControlChannel;
 953 //------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------//
 954
 955 //--------REMOVED COMMON INFO----------//
 956         //u8                            PseudoMacPhyMode;
 957         //bool                  *BTCoexist;
 958         //bool                  PseudoBtCoexist;
 959         //u8                            OPMode;
 960         //bool                  bAPMode;
 961         //bool                  bClientMode;
 962         //bool                  bAdHocMode;
 963         //bool                  bSlaveOfDMSP;
 964 //--------REMOVED COMMON INFO----------//
 965
 966
 967 //1  COMMON INFORMATION
 968
 969         //
 970         // Init Value
 971         //
 972 //-----------HOOK BEFORE REG INIT-----------//
 973         // ODM Platform info AP/ADSL/CE/MP = 1/2/3/4
 974         u8                      SupportPlatform;
 975         // ODM Support Ability DIG/RATR/TX_PWR_TRACK/ ¡K¡K = 1/2/3/¡K
 976         u32                     SupportAbility;
 977         // ODM PCIE/USB/SDIO/GSPI = 0/1/2/3
 978         u8                      SupportInterface;
 979         // ODM composite or independent. Bit oriented/ 92C+92D+ .... or any other type = 1/2/3/...
 980         u32                     SupportICType;
 981         // Cut Version TestChip/A-cut/B-cut... = 0/1/2/3/...
 982         u8                      CutVersion;
 983         // Fab Version TSMC/UMC = 0/1
 984         u8                      FabVersion;
 985         // RF Type 4T4R/3T3R/2T2R/1T2R/1T1R/...
 986         u8                      RFType;
 987         // Board Type Normal/HighPower/MiniCard/SLIM/Combo/... = 0/1/2/3/4/...
 988         u8                      BoardType;
 989         // with external LNA  NO/Yes = 0/1
 990         u8                      ExtLNA;
 991         // with external PA  NO/Yes = 0/1
 992         u8                      ExtPA;
 993         // with external TRSW  NO/Yes = 0/1
 994         u8                      ExtTRSW;
 995         u8                      PatchID; //Customer ID
 996         bool                    bInHctTest;
 997         bool                    bWIFITest;
 998
 999         bool                    bDualMacSmartConcurrent;
1000         u32                     BK_SupportAbility;
1001         u8                      AntDivType;
1002 //-----------HOOK BEFORE REG INIT-----------//
1003
1004         //
1005         // Dynamic Value
1006         //
1007 //--------- POINTER REFERENCE-----------//
1008
1009         u8                      u8_temp;
1010         bool                    bool_temp;
1011         PADAPTER                PADAPTER_temp;
1012
1013         // MAC PHY Mode SMSP/DMSP/DMDP = 0/1/2
1014         u8                      *pMacPhyMode;
1015         //TX Unicast byte count
1016         u64                     *pNumTxBytesUnicast;
1017         //RX Unicast byte count
1018         u64                     *pNumRxBytesUnicast;
1019         // Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3
1020         u8                      *pWirelessMode; //ODM_WIRELESS_MODE_E
1021         // Frequence band 2.4G/5G = 0/1
1022         u8                      *pBandType;
1023         // Secondary channel offset don't_care/below/above = 0/1/2
1024         u8                      *pSecChOffset;
1025         // Security mode Open/WEP/AES/TKIP = 0/1/2/3
1026         u8                      *pSecurity;
1027         // BW info 20M/40M/80M = 0/1/2
1028         u8                      *pBandWidth;
1029         // Central channel location Ch1/Ch2/....
1030         u8                      *pChannel;      //central channel number
1031         // Common info for 92D DMSP
1032
1033         bool                    *pbGetValueFromOtherMac;
1034         PADAPTER                *pBuddyAdapter;
1035         bool                    *pbMasterOfDMSP; //MAC0: master, MAC1: slave
1036         // Common info for Status
1037         bool                    *pbScanInProcess;
1038         bool                    *pbPowerSaving;
1039         // CCA Path 2-path/path-A/path-B = 0/1/2; using ODM_CCA_PATH_E.
1040         u8                      *pOnePathCCA;
1041         //pMgntInfo->AntennaTest
1042         u8                      *pAntennaTest;
1043         bool                    *pbNet_closed;
1044 //--------- POINTER REFERENCE-----------//
1045         //
1046 //------------CALL BY VALUE-------------//
1047         bool                    bWIFI_Direct;
1048         bool                    bWIFI_Display;
1049         bool                    bLinked;
1050         u8                      RSSI_Min;
1051         u8                      InterfaceIndex; // Add for 92D  dual MAC: 0--Mac0 1--Mac1
1052         bool            bIsMPChip;
1053         bool                    bOneEntryOnly;
1054         // Common info for BTDM
1055         bool                    bBtDisabled;                    // BT is disabled
1056         bool                    bBtHsOperation;         // BT HS mode is under progress
1057         u8                      btHsDigVal;                     // use BT rssi to decide the DIG value
1058         bool                    bBtDisableEdcaTurbo;    // Under some condition, don't enable the EDCA Turbo
1059         bool                    bBtBusy;                        // BT is busy.
1060 //------------CALL BY VALUE-------------//
1061
1062         //2 Define STA info.
1063         // _ODM_STA_INFO
1064         // 2012/01/12 MH For MP, we need to reduce one array pointer for default port.??
1065         PSTA_INFO_T             pODM_StaInfo[ODM_ASSOCIATE_ENTRY_NUM];
1066
1067 #if (RATE_ADAPTIVE_SUPPORT == 1)
1068         u16                     CurrminRptTime;
1069         ODM_RA_INFO_T   RAInfo[ODM_ASSOCIATE_ENTRY_NUM]; //Use MacID as array index. STA MacID=0, VWiFi Client MacID={1, ODM_ASSOCIATE_ENTRY_NUM-1} //YJ,add,120119
1070 #endif
1071         //
1072         // 2012/02/14 MH Add to share 88E ra with other SW team.
1073         // We need to colelct all support abilit to a proper area.
1074         //
1075         bool                            RaSupport88E;
1076
1077         // Define ...........
1078
1079         // Latest packet phy info (ODM write)
1080         ODM_PHY_DBG_INFO_T       PhyDbgInfo;
1081         //PHY_INFO_88E          PhyInfo;
1082
1083         // Latest packet phy info (ODM write)
1084         ODM_MAC_INFO            *pMacInfo;
1085         //MAC_INFO_88E          MacInfo;
1086
1087         // Different Team independt structure??
1088
1089         //
1090         //TX_RTP_CMN            TX_retrpo;
1091         //TX_RTP_88E            TX_retrpo;
1092         //TX_RTP_8195           TX_retrpo;
1093
1094         //
1095         //ODM Structure
1096         //
1097         FAT_T           DM_FatTable;
1098         DIG_T           DM_DigTable;
1099         PS_T            DM_PSTable;
1100         Pri_CCA_T       DM_PriCCA;
1101         RXHP_T          DM_RXHP_Table;
1102         FALSE_ALARM_STATISTICS  FalseAlmCnt;
1103         FALSE_ALARM_STATISTICS  FlaseAlmCntBuddyAdapter;
1104         //#ifdef CONFIG_ANTENNA_DIVERSITY
1105         SWAT_T          DM_SWAT_Table;
1106         bool            RSSI_test;
1107         //#endif
1108
1109         EDCA_T          DM_EDCA_Table;
1110         u32             WMMEDCA_BE;
1111         // Copy from SD4 structure
1112         //
1113         // ==================================================
1114         //
1115
1116         //common
1117         //u8            DM_Type;
1118         //u8    PSD_Report_RXHP[80];   // Add By Gary
1119         //u8    PSD_func_flag;               // Add By Gary
1120         //for DIG
1121         //u8            bDMInitialGainEnable;
1122         //u8            binitialized; // for dm_initial_gain_Multi_STA use.
1123         //for Antenna diversity
1124         //u8    AntDivCfg;// 0:OFF , 1:ON, 2:by efuse
1125         //PSTA_INFO_T RSSI_target;
1126
1127         bool                    *pbDriverStopped;
1128         bool                    *pbDriverIsGoingToPnpSetPowerSleep;
1129         bool                    *pinit_adpt_in_progress;
1130
1131         //PSD
1132         bool                    bUserAssignLevel;
1133         RT_TIMER                PSDTimer;
1134         u8                      RSSI_BT;                        //come from BT
1135         bool                    bPSDinProcess;
1136         bool                    bDMInitialGainEnable;
1137
1138         //for rate adaptive, in fact,  88c/92c fw will handle this
1139         u8                      bUseRAMask;
1140
1141         ODM_RATE_ADAPTIVE       RateAdaptive;
1142
1143
1144         ODM_RF_CAL_T    RFCalibrateInfo;
1145
1146         //
1147         // TX power tracking
1148         //
1149         u8                      BbSwingIdxOfdm;
1150         u8                      BbSwingIdxOfdmCurrent;
1151         u8                      BbSwingIdxOfdmBase;
1152         bool                    BbSwingFlagOfdm;
1153         u8                      BbSwingIdxCck;
1154         u8                      BbSwingIdxCckCurrent;
1155         u8                      BbSwingIdxCckBase;
1156         bool                    BbSwingFlagCck;
1157         //
1158         // ODM system resource.
1159         //
1160
1161         // ODM relative time.
1162         RT_TIMER                                PathDivSwitchTimer;
1163         //2011.09.27 add for Path Diversity
1164         RT_TIMER                                CCKPathDiversityTimer;
1165         RT_TIMER        FastAntTrainingTimer;
1166
1167         // ODM relative workitem.
1168 } DM_ODM_T, *PDM_ODM_T;         // DM_Dynamic_Mechanism_Structure
1169
1170
1171
1172 #if 1 //92c-series
1173 #define ODM_RF_PATH_MAX 2
1174 #else //jaguar - series
1175 #define ODM_RF_PATH_MAX 4
1176 #endif
1177
1178 typedef enum _ODM_RF_RADIO_PATH {
1179     ODM_RF_PATH_A = 0,   //Radio Path A
1180     ODM_RF_PATH_B = 1,   //Radio Path B
1181     ODM_RF_PATH_C = 2,   //Radio Path C
1182     ODM_RF_PATH_D = 3,   //Radio Path D
1183   //  ODM_RF_PATH_MAX,    //Max RF number 90 support
1184 } ODM_RF_RADIO_PATH_E, *PODM_RF_RADIO_PATH_E;
1185
1186  typedef enum _ODM_RF_CONTENT{
1187         odm_radioa_txt = 0x1000,
1188         odm_radiob_txt = 0x1001,
1189         odm_radioc_txt = 0x1002,
1190         odm_radiod_txt = 0x1003
1191 } ODM_RF_CONTENT;
1192
1193 typedef enum _ODM_BB_Config_Type{
1194     CONFIG_BB_PHY_REG,
1195     CONFIG_BB_AGC_TAB,
1196     CONFIG_BB_AGC_TAB_2G,
1197     CONFIG_BB_AGC_TAB_5G,
1198     CONFIG_BB_PHY_REG_PG,
1199 } ODM_BB_Config_Type, *PODM_BB_Config_Type;
1200
1201 // Status code
1202 typedef enum _RT_STATUS{
1203         RT_STATUS_SUCCESS,
1204         RT_STATUS_FAILURE,
1205         RT_STATUS_PENDING,
1206         RT_STATUS_RESOURCE,
1207         RT_STATUS_INVALID_CONTEXT,
1208         RT_STATUS_INVALID_PARAMETER,
1209         RT_STATUS_NOT_SUPPORT,
1210         RT_STATUS_OS_API_FAILED,
1211 }RT_STATUS,*PRT_STATUS;
1212
1213 //#include "odm_function.h"
1214
1215 //3===========================================================
1216 //3 DIG
1217 //3===========================================================
1218
1219 typedef enum tag_Dynamic_Init_Gain_Operation_Type_Definition
1220 {
1221         DIG_TYPE_THRESH_HIGH    = 0,
1222         DIG_TYPE_THRESH_LOW     = 1,
1223         DIG_TYPE_BACKOFF                = 2,
1224         DIG_TYPE_RX_GAIN_MIN    = 3,
1225         DIG_TYPE_RX_GAIN_MAX    = 4,
1226         DIG_TYPE_ENABLE                 = 5,
1227         DIG_TYPE_DISABLE                = 6,
1228         DIG_OP_TYPE_MAX
1229 }DM_DIG_OP_E;
1230 /*
1231 typedef enum tag_CCK_Packet_Detection_Threshold_Type_Definition
1232 {
1233         CCK_PD_STAGE_LowRssi = 0,
1234         CCK_PD_STAGE_HighRssi = 1,
1235         CCK_PD_STAGE_MAX = 3,
1236 }DM_CCK_PDTH_E;
1237
1238 typedef enum tag_DIG_EXT_PORT_ALGO_Definition
1239 {
1240         DIG_EXT_PORT_STAGE_0 = 0,
1241         DIG_EXT_PORT_STAGE_1 = 1,
1242         DIG_EXT_PORT_STAGE_2 = 2,
1243         DIG_EXT_PORT_STAGE_3 = 3,
1244         DIG_EXT_PORT_STAGE_MAX = 4,
1245 }DM_DIG_EXT_PORT_ALG_E;
1246
1247 typedef enum tag_DIG_Connect_Definition
1248 {
1249         DIG_STA_DISCONNECT = 0,
1250         DIG_STA_CONNECT = 1,
1251         DIG_STA_BEFORE_CONNECT = 2,
1252         DIG_MultiSTA_DISCONNECT = 3,
1253         DIG_MultiSTA_CONNECT = 4,
1254         DIG_CONNECT_MAX
1255 }DM_DIG_CONNECT_E;
1256
1257
1258 #define DM_MultiSTA_InitGainChangeNotify(Event) {DM_DigTable.CurMultiSTAConnectState = Event;}
1259
1260 #define DM_MultiSTA_InitGainChangeNotify_CONNECT(_ADAPTER)      \
1261         DM_MultiSTA_InitGainChangeNotify(DIG_MultiSTA_CONNECT)
1262
1263 #define DM_MultiSTA_InitGainChangeNotify_DISCONNECT(_ADAPTER)   \
1264         DM_MultiSTA_InitGainChangeNotify(DIG_MultiSTA_DISCONNECT)
1265 */
1266 #define         DM_DIG_THRESH_HIGH                      40
1267 #define         DM_DIG_THRESH_LOW                       35
1268
1269 #define         DM_SCAN_RSSI_TH                         0x14 //scan return issue for LC
1270
1271
1272 #define         DM_FALSEALARM_THRESH_LOW        400
1273 #define         DM_FALSEALARM_THRESH_HIGH       1000
1274
1275 #define         DM_DIG_MAX_NIC                          0x4e
1276 #define         DM_DIG_MIN_NIC                          0x1e //0x22//0x1c
1277
1278 #define         DM_DIG_MAX_AP                                   0x32
1279 #define         DM_DIG_MIN_AP                                   0x20
1280
1281 #define         DM_DIG_MAX_NIC_HP                       0x46
1282 #define         DM_DIG_MIN_NIC_HP                       0x2e
1283
1284 #define         DM_DIG_MAX_AP_HP                                0x42
1285 #define         DM_DIG_MIN_AP_HP                                0x30
1286
1287 //vivi 92c&92d has different definition, 20110504
1288 //this is for 92c
1289 #define         DM_DIG_FA_TH0                           0x200//0x20
1290 #define         DM_DIG_FA_TH1                           0x300//0x100
1291 #define         DM_DIG_FA_TH2                           0x400//0x200
1292 //this is for 92d
1293 #define         DM_DIG_FA_TH0_92D                       0x100
1294 #define         DM_DIG_FA_TH1_92D                       0x400
1295 #define         DM_DIG_FA_TH2_92D                       0x600
1296
1297 #define         DM_DIG_BACKOFF_MAX                      12
1298 #define         DM_DIG_BACKOFF_MIN                      -4
1299 #define         DM_DIG_BACKOFF_DEFAULT          10
1300
1301 //3===========================================================
1302 //3 AGC RX High Power Mode
1303 //3===========================================================
1304 #define          LNA_Low_Gain_1                      0x64
1305 #define          LNA_Low_Gain_2                      0x5A
1306 #define          LNA_Low_Gain_3                      0x58
1307
1308 #define          FA_RXHP_TH1                           5000
1309 #define          FA_RXHP_TH2                           1500
1310 #define          FA_RXHP_TH3                             800
1311 #define          FA_RXHP_TH4                             600
1312 #define          FA_RXHP_TH5                             500
1313
1314 //3===========================================================
1315 //3 EDCA
1316 //3===========================================================
1317
1318 //3===========================================================
1319 //3 Dynamic Tx Power
1320 //3===========================================================
1321 //Dynamic Tx Power Control Threshold
1322 #define         TX_POWER_NEAR_FIELD_THRESH_LVL2 74
1323 #define         TX_POWER_NEAR_FIELD_THRESH_LVL1 67
1324 #define         TX_POWER_NEAR_FIELD_THRESH_AP           0x3F
1325
1326 #define         TxHighPwrLevel_Normal           0
1327 #define         TxHighPwrLevel_Level1           1
1328 #define         TxHighPwrLevel_Level2           2
1329 #define         TxHighPwrLevel_BT1                      3
1330 #define         TxHighPwrLevel_BT2                      4
1331 #define         TxHighPwrLevel_15                       5
1332 #define         TxHighPwrLevel_35                       6
1333 #define         TxHighPwrLevel_50                       7
1334 #define         TxHighPwrLevel_70                       8
1335 #define         TxHighPwrLevel_100                      9
1336
1337 //3===========================================================
1338 //3 Rate Adaptive
1339 //3===========================================================
1340 #define         DM_RATR_STA_INIT                        0
1341 #define         DM_RATR_STA_HIGH                        1
1342 #define                 DM_RATR_STA_MIDDLE              2
1343 #define                 DM_RATR_STA_LOW                 3
1344
1345 //3===========================================================
1346 //3 BB Power Save
1347 //3===========================================================
1348
1349
1350 typedef enum tag_1R_CCA_Type_Definition
1351 {
1352         CCA_1R =0,
1353         CCA_2R = 1,
1354         CCA_MAX = 2,
1355 }DM_1R_CCA_E;
1356
1357 typedef enum tag_RF_Type_Definition
1358 {
1359         RF_Save =0,
1360         RF_Normal = 1,
1361         RF_MAX = 2,
1362 }DM_RF_E;
1363
1364 //3===========================================================
1365 //3 Antenna Diversity
1366 //3===========================================================
1367 typedef enum tag_SW_Antenna_Switch_Definition
1368 {
1369         Antenna_A = 1,
1370         Antenna_B = 2,
1371         Antenna_MAX = 3,
1372 }DM_SWAS_E;
1373
1374
1375 // Maximal number of antenna detection mechanism needs to perform, added by Roger, 2011.12.28.
1376 #define MAX_ANTENNA_DETECTION_CNT       10
1377
1378 //
1379 // Extern Global Variables.
1380 //
1381 #define OFDM_TABLE_SIZE_92C     37
1382 #define OFDM_TABLE_SIZE_92D     43
1383 #define CCK_TABLE_SIZE          33
1384
1385 extern  u32 OFDMSwingTable[OFDM_TABLE_SIZE_92D];
1386 extern  u8 CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8];
1387 extern  u8 CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8];
1388
1389
1390
1391 //
1392 // check Sta pointer valid or not
1393 //
1394 #define IS_STA_VALID(pSta)              (pSta)
1395 // 20100514 Joseph: Add definition for antenna switching test after link.
1396 // This indicates two different the steps.
1397 // In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air.
1398 // In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK
1399 // with original RSSI to determine if it is necessary to switch antenna.
1400 #define SWAW_STEP_PEAK          0
1401 #define SWAW_STEP_DETERMINE     1
1402
1403 void ODM_Write_DIG(PDM_ODM_T    pDM_Odm,        u8      CurrentIGI);
1404 void ODM_Write_CCK_CCA_Thres(PDM_ODM_T  pDM_Odm, u8     CurCCK_CCAThres);
1405
1406 void
1407 ODM_SetAntenna(
1408         PDM_ODM_T       pDM_Odm,
1409         u8              Antenna);
1410
1411
1412 #define dm_RF_Saving    ODM_RF_Saving
1413 void ODM_RF_Saving(     PDM_ODM_T       pDM_Odm,
1414                                                         u8              bForceInNormal );
1415
1416 #define SwAntDivRestAfterLink   ODM_SwAntDivRestAfterLink
1417 void ODM_SwAntDivRestAfterLink( PDM_ODM_T       pDM_Odm);
1418
1419 #define dm_CheckTXPowerTracking         ODM_TXPowerTrackingCheck
1420 void
1421 ODM_TXPowerTrackingCheck(
1422                 PDM_ODM_T               pDM_Odm
1423         );
1424
1425 bool
1426 ODM_RAStateCheck(
1427                 PDM_ODM_T               pDM_Odm,
1428                 s4Byte                  RSSI,
1429                 bool                    bForceUpdate,
1430                 u8 *                    pRATRState
1431         );
1432
1433
1434 #define dm_SWAW_RSSI_Check      ODM_SwAntDivChkPerPktRssi
1435 void ODM_SwAntDivChkPerPktRssi(
1436  PDM_ODM_T              pDM_Odm,
1437  u8                     StationID,
1438  PODM_PHY_INFO_T pPhyInfo
1439         );
1440
1441 u32 ConvertTo_dB(u32 Value);
1442
1443 u32
1444 GetPSDData(
1445         PDM_ODM_T       pDM_Odm,
1446         unsigned int    point,
1447         u8 initial_gain_psd);
1448
1449 void
1450 odm_DIGbyRSSI_LPS(
1451                 PDM_ODM_T               pDM_Odm
1452         );
1453
1454 u32 ODM_Get_Rate_Bitmap(
1455         PDM_ODM_T       pDM_Odm,
1456         u32             macid,
1457         u32             ra_mask,
1458         u8              rssi_level);
1459
1460
1461 void ODM_DMInit(PDM_ODM_T       pDM_Odm);
1462
1463 void
1464 ODM_DMWatchdog(
1465                 PDM_ODM_T                       pDM_Odm                 // For common use in the future
1466         );
1467
1468 void
1469 ODM_CmnInfoInit(
1470                 PDM_ODM_T               pDM_Odm,
1471                 ODM_CMNINFO_E   CmnInfo,
1472                 u32                     Value
1473         );
1474
1475 void
1476 ODM_CmnInfoHook(
1477                 PDM_ODM_T               pDM_Odm,
1478                 ODM_CMNINFO_E   CmnInfo,
1479                 void *                  pValue
1480         );
1481
1482 void
1483 ODM_CmnInfoPtrArrayHook(
1484                 PDM_ODM_T               pDM_Odm,
1485                 ODM_CMNINFO_E   CmnInfo,
1486                 u16                     Index,
1487                 void *                  pValue
1488         );
1489
1490 void
1491 ODM_CmnInfoUpdate(
1492                 PDM_ODM_T               pDM_Odm,
1493                 u32                     CmnInfo,
1494                 u64                     Value
1495         );
1496
1497 void
1498 ODM_InitAllTimers(
1499         PDM_ODM_T       pDM_Odm
1500     );
1501
1502 void
1503 ODM_CancelAllTimers(
1504         PDM_ODM_T    pDM_Odm
1505     );
1506
1507 void
1508 ODM_ReleaseAllTimers(
1509         PDM_ODM_T       pDM_Odm
1510     );
1511
1512 void
1513 ODM_ResetIQKResult(
1514         PDM_ODM_T pDM_Odm
1515     );
1516
1517
1518 void
1519 ODM_AntselStatistics_88C(
1520                 PDM_ODM_T               pDM_Odm,
1521                 u8                      MacId,
1522                 u32                     PWDBAll,
1523                 bool                    isCCKrate
1524 );
1525
1526
1527 void
1528 ODM_SingleDualAntennaDefaultSetting(
1529                 PDM_ODM_T               pDM_Odm
1530         );
1531
1532 bool
1533 ODM_SingleDualAntennaDetection(
1534                 PDM_ODM_T               pDM_Odm,
1535                 u8                      mode
1536         );
1537
1538 void odm_dtc(PDM_ODM_T pDM_Odm);
1539
1540 #endif