include/rtl8723a_hal.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  *
  19  ******************************************************************************/
  20 #ifndef __RTL8723A_HAL_H__
  21 #define __RTL8723A_HAL_H__
  22
  23 #include "rtl8723a_spec.h"
  24 #include "rtl8723a_pg.h"
  25 #include "Hal8723APhyReg.h"
  26 #include "Hal8723APhyCfg.h"
  27 #include "rtl8723a_rf.h"
  28 #ifdef CONFIG_BT_COEXIST
  29 #include "rtl8723a_bt-coexist.h"
  30 #endif
  31 #include "rtl8723a_dm.h"
  32 #include "rtl8723a_recv.h"
  33 #include "rtl8723a_xmit.h"
  34 #include "rtl8723a_cmd.h"
  35 #ifdef DBG_CONFIG_ERROR_DETECT
  36 #include "rtl8723a_sreset.h"
  37 #endif
  38 #include "rtw_efuse.h"
  39
  40 #include "odm_precomp.h"
  41
  42
  43 //2TODO: We should define 8192S firmware related macro settings here!!
  44 #define RTL819X_DEFAULT_RF_TYPE                 RF_1T2R
  45 #define RTL819X_TOTAL_RF_PATH                           2
  46
  47 //TODO:  The following need to check!!
  48 #define RTL8723_FW_UMC_IMG                              "rtl8192CU\\rtl8723fw.bin"
  49 #define RTL8723_FW_UMC_B_IMG                    "rtl8192CU\\rtl8723fw_B.bin"
  50 #define RTL8723_PHY_REG                                 "rtl8723S\\PHY_REG_1T.txt"
  51 #define RTL8723_PHY_RADIO_A                             "rtl8723S\\radio_a_1T.txt"
  52 #define RTL8723_PHY_RADIO_B                             "rtl8723S\\radio_b_1T.txt"
  53 #define RTL8723_AGC_TAB                                 "rtl8723S\\AGC_TAB_1T.txt"
  54 #define RTL8723_PHY_MACREG                              "rtl8723S\\MAC_REG.txt"
  55 #define RTL8723_PHY_REG_PG                              "rtl8723S\\PHY_REG_PG.txt"
  56 #define RTL8723_PHY_REG_MP                              "rtl8723S\\PHY_REG_MP.txt"
  57
  58 //---------------------------------------------------------------------
  59 //              RTL8723S From header
  60 //---------------------------------------------------------------------
  61
  62 // Fw Array
  63 #define Rtl8723_FwImageArray                            Rtl8723UFwImgArray
  64 #define Rtl8723_FwUMCBCutImageArrayWithBT               Rtl8723UFwUMCBCutImgArrayWithBT
  65 #define Rtl8723_FwUMCBCutImageArrayWithoutBT    Rtl8723UFwUMCBCutImgArrayWithoutBT
  66
  67 #define Rtl8723_ImgArrayLength                          Rtl8723UImgArrayLength
  68 #define Rtl8723_UMCBCutImgArrayWithBTLength             Rtl8723UUMCBCutImgArrayWithBTLength
  69 #define Rtl8723_UMCBCutImgArrayWithoutBTLength  Rtl8723UUMCBCutImgArrayWithoutBTLength
  70
  71 #define Rtl8723_PHY_REG_Array_PG                        Rtl8723UPHY_REG_Array_PG
  72 #define Rtl8723_PHY_REG_Array_PGLength          Rtl8723UPHY_REG_Array_PGLength
  73
  74 #define Rtl8723_FwUMCBCutMPImageArray           Rtl8723SFwUMCBCutMPImgAr
  75 #define Rtl8723_UMCBCutMPImgArrayLength         Rtl8723SUMCBCutMPImgArrayLength
  76
  77 #if 0 /* CONFIG_MP_INCLUDED */
  78         #define Rtl8723E_FwBTImgArray                           Rtl8723EFwBTImgArray
  79         #define Rtl8723E_FwBTImgArrayLength                     Rtl8723EBTImgArrayLength
  80
  81 ray
  82
  83         #define Rtl8723_PHY_REG_Array_MP                        Rtl8723UPHY_REG_Array_MP
  84         #define Rtl8723_PHY_REG_Array_MPLength          Rtl8723UPHY_REG_Array_MPLength
  85 #endif
  86 #ifndef CONFIG_PHY_SETTING_WITH_ODM
  87         // MAC/BB/PHY Array
  88         #define Rtl8723_MAC_Array                                       Rtl8723UMAC_2T_Array
  89         //#define Rtl8723_AGCTAB_2TArray                                Rtl8723UAGCTAB_2TArray
  90         #define Rtl8723_AGCTAB_1TArray                          Rtl8723UAGCTAB_1TArray
  91         //#define Rtl8723_PHY_REG_2TArray                               Rtl8723UPHY_REG_2TArray
  92         #define Rtl8723_PHY_REG_1TArray                         Rtl8723UPHY_REG_1TArray
  93         //#define Rtl8723_RadioA_2TArray                                Rtl8723URadioA_2TArray
  94         #define Rtl8723_RadioA_1TArray                          Rtl8723URadioA_1TArray
  95         //#define Rtl8723_RadioB_2TArray                                Rtl8723URadioB_2TArray
  96         #define Rtl8723_RadioB_1TArray                          Rtl8723URadioB_1TArray
  97
  98
  99
 100         // Array length
 101
 102         #define Rtl8723_MAC_ArrayLength                         Rtl8723UMAC_2T_ArrayLength
 103         #define Rtl8723_AGCTAB_1TArrayLength                    Rtl8723UAGCTAB_1TArrayLength
 104         #define Rtl8723_PHY_REG_1TArrayLength                   Rtl8723UPHY_REG_1TArrayLength
 105
 106
 107         #define Rtl8723_RadioA_1TArrayLength                    Rtl8723URadioA_1TArrayLength
 108         #define Rtl8723_RadioB_1TArrayLength                    Rtl8723URadioB_1TArrayLength
 109 #endif
 110
 111 #define DRVINFO_SZ                              4 // unit is 8bytes
 112 #define PageNum_128(_Len)               (u32)(((_Len)>>7) + ((_Len)&0x7F ? 1:0))
 113
 114 #define FW_8723A_SIZE                   0x8000
 115 #define FW_8723A_START_ADDRESS  0x1000
 116 #define FW_8723A_END_ADDRESS            0x1FFF //0x5FFF
 117
 118 #define MAX_PAGE_SIZE                   4096    // @ page : 4k bytes
 119
 120 #define IS_FW_HEADER_EXIST(_pFwHdr)     ((le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x92C0 ||\
 121                                                                         (le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x88C0 ||\
 122                                                                         (le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x2300)
 123
 124 typedef enum _FIRMWARE_SOURCE {
 125         FW_SOURCE_IMG_FILE = 0,
 126         FW_SOURCE_HEADER_FILE = 1,              //from header file
 127 } FIRMWARE_SOURCE, *PFIRMWARE_SOURCE;
 128
 129 typedef struct _RT_FIRMWARE {
 130         FIRMWARE_SOURCE eFWSource;
 131 #ifdef CONFIG_EMBEDDED_FWIMG
 132         u8*                     szFwBuffer;
 133 #else
 134         u8                      szFwBuffer[FW_8723A_SIZE];
 135 #endif
 136         u32                     ulFwLength;
 137
 138 #ifdef CONFIG_EMBEDDED_FWIMG
 139         u8*                     szBTFwBuffer;
 140 #else
 141         u8                      szBTFwBuffer[FW_8723A_SIZE];
 142 #endif
 143         u32                     ulBTFwLength;
 144 } RT_FIRMWARE, *PRT_FIRMWARE, RT_FIRMWARE_8723A, *PRT_FIRMWARE_8723A;
 145
 146 //
 147 // This structure must be cared byte-ordering
 148 //
 149 // Added by tynli. 2009.12.04.
 150 typedef struct _RT_8723A_FIRMWARE_HDR
 151 {
 152         // 8-byte alinment required
 153
 154         //--- LONG WORD 0 ----
 155         u16             Signature;      // 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut
 156         u8              Category;       // AP/NIC and USB/PCI
 157         u8              Function;       // Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions
 158         u16             Version;                // FW Version
 159         u8              Subversion;     // FW Subversion, default 0x00
 160         u16             Rsvd1;
 161
 162
 163         //--- LONG WORD 1 ----
 164         u8              Month;  // Release time Month field
 165         u8              Date;   // Release time Date field
 166         u8              Hour;   // Release time Hour field
 167         u8              Minute; // Release time Minute field
 168         u16             RamCodeSize;    // The size of RAM code
 169         u16             Rsvd2;
 170
 171         //--- LONG WORD 2 ----
 172         u32             SvnIdx; // The SVN entry index
 173         u32             Rsvd3;
 174
 175         //--- LONG WORD 3 ----
 176         u32             Rsvd4;
 177         u32             Rsvd5;
 178 }RT_8723A_FIRMWARE_HDR, *PRT_8723A_FIRMWARE_HDR;
 179
 180 #define DRIVER_EARLY_INT_TIME           0x05
 181 #define BCN_DMA_ATIME_INT_TIME          0x02
 182
 183 #ifdef CONFIG_USB_RX_AGGREGATION
 184
 185 typedef enum _USB_RX_AGG_MODE{
 186         USB_RX_AGG_DISABLE,
 187         USB_RX_AGG_DMA,
 188         USB_RX_AGG_USB,
 189         USB_RX_AGG_MIX
 190 }USB_RX_AGG_MODE;
 191
 192 #define MAX_RX_DMA_BUFFER_SIZE  10240           // 10K for 8192C RX DMA buffer
 193
 194 #endif
 195
 196
 197 // BK, BE, VI, VO, HCCA, MANAGEMENT, COMMAND, HIGH, BEACON.
 198 #define MAX_TX_QUEUE            9
 199
 200 #define TX_SELE_HQ                      BIT(0)          // High Queue
 201 #define TX_SELE_LQ                      BIT(1)          // Low Queue
 202 #define TX_SELE_NQ                      BIT(2)          // Normal Queue
 203
 204 // Note: We will divide number of page equally for each queue other than public queue!
 205 #define TX_TOTAL_PAGE_NUMBER    0xF8
 206 #define TX_PAGE_BOUNDARY                (TX_TOTAL_PAGE_NUMBER + 1)
 207
 208 // For Normal Chip Setting
 209 // (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER
 210 #define NORMAL_PAGE_NUM_PUBQ    0xE7
 211 #define NORMAL_PAGE_NUM_HPQ             0x0C
 212 #define NORMAL_PAGE_NUM_LPQ             0x02
 213 #define NORMAL_PAGE_NUM_NPQ             0x02
 214
 215 // For Test Chip Setting
 216 // (HPQ + LPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER
 217 #define TEST_PAGE_NUM_PUBQ              0x7E
 218
 219 // For Test Chip Setting
 220 #define WMM_TEST_TX_TOTAL_PAGE_NUMBER   0xF5
 221 #define WMM_TEST_TX_PAGE_BOUNDARY               (WMM_TEST_TX_TOTAL_PAGE_NUMBER + 1) //F6
 222
 223 #define WMM_TEST_PAGE_NUM_PUBQ          0xA3
 224 #define WMM_TEST_PAGE_NUM_HPQ           0x29
 225 #define WMM_TEST_PAGE_NUM_LPQ           0x29
 226
 227 // Note: For Normal Chip Setting, modify later
 228 #define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER 0xF5
 229 #define WMM_NORMAL_TX_PAGE_BOUNDARY             (WMM_TEST_TX_TOTAL_PAGE_NUMBER + 1) //F6
 230
 231 #define WMM_NORMAL_PAGE_NUM_PUBQ        0xB0
 232 #define WMM_NORMAL_PAGE_NUM_HPQ         0x29
 233 #define WMM_NORMAL_PAGE_NUM_LPQ         0x1C
 234 #define WMM_NORMAL_PAGE_NUM_NPQ         0x1C
 235
 236
 237 //-------------------------------------------------------------------------
 238 //      Chip specific
 239 //-------------------------------------------------------------------------
 240 #define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22)&0x3)
 241 #define CHIP_BONDING_92C_1T2R                   0x1
 242 #define CHIP_BONDING_88C_USB_MCARD              0x2
 243 #define CHIP_BONDING_88C_USB_HP                 0x1
 244
 245 #include "HalVerDef.h"
 246 #include "hal_com.h"
 247
 248 //-------------------------------------------------------------------------
 249 //      Channel Plan
 250 //-------------------------------------------------------------------------
 251 enum ChannelPlan
 252 {
 253         CHPL_FCC        = 0,
 254         CHPL_IC         = 1,
 255         CHPL_ETSI       = 2,
 256         CHPL_SPAIN      = 3,
 257         CHPL_FRANCE     = 4,
 258         CHPL_MKK        = 5,
 259         CHPL_MKK1       = 6,
 260         CHPL_ISRAEL     = 7,
 261         CHPL_TELEC      = 8,
 262         CHPL_GLOBAL     = 9,
 263         CHPL_WORLD      = 10,
 264 };
 265
 266 #define HAL_EFUSE_MEMORY
 267
 268 #define EFUSE_REAL_CONTENT_LEN          512
 269 #define EFUSE_MAP_LEN                           128
 270 #define EFUSE_MAX_SECTION                       16
 271 #define EFUSE_IC_ID_OFFSET                      506     //For some inferiority IC purpose. added by Roger, 2009.09.02.
 272 #define AVAILABLE_EFUSE_ADDR(addr)      (addr < EFUSE_REAL_CONTENT_LEN)
 273 //
 274 // <Roger_Notes>
 275 // To prevent out of boundary programming case,
 276 // leave 1byte and program full section
 277 // 9bytes + 1byt + 5bytes and pre 1byte.
 278 // For worst case:
 279 // | 1byte|----8bytes----|1byte|--5bytes--|
 280 // |         |            Reserved(14bytes)           |
 281 //
 282
 283 // PG data exclude header, dummy 6 bytes frome CP test and reserved 1byte.
 284 #define EFUSE_OOB_PROTECT_BYTES                 15
 285
 286 #define EFUSE_REAL_CONTENT_LEN_8723A    512
 287 #define EFUSE_MAP_LEN_8723A                             256
 288 #define EFUSE_MAX_SECTION_8723A                 32
 289
 290 //========================================================
 291 //                      EFUSE for BT definition
 292 //========================================================
 293 #define EFUSE_BT_REAL_BANK_CONTENT_LEN  512
 294 #define EFUSE_BT_REAL_CONTENT_LEN               1536    // 512*3
 295 #define EFUSE_BT_MAP_LEN                                1024    // 1k bytes
 296 #define EFUSE_BT_MAX_SECTION                    128             // 1024/8
 297
 298 #define EFUSE_PROTECT_BYTES_BANK                16
 299
 300 //
 301 // <Roger_Notes> For RTL8723 WiFi/BT/GPS multi-function configuration. 2010.10.06.
 302 //
 303 typedef enum _RT_MULTI_FUNC {
 304         RT_MULTI_FUNC_NONE = 0x00,
 305         RT_MULTI_FUNC_WIFI = 0x01,
 306         RT_MULTI_FUNC_BT = 0x02,
 307         RT_MULTI_FUNC_GPS = 0x04,
 308 } RT_MULTI_FUNC, *PRT_MULTI_FUNC;
 309
 310 //
 311 // <Roger_Notes> For RTL8723 WiFi PDn/GPIO polarity control configuration. 2010.10.08.
 312 //
 313 typedef enum _RT_POLARITY_CTL {
 314         RT_POLARITY_LOW_ACT = 0,
 315         RT_POLARITY_HIGH_ACT = 1,
 316 } RT_POLARITY_CTL, *PRT_POLARITY_CTL;
 317
 318 // For RTL8723 regulator mode. by tynli. 2011.01.14.
 319 typedef enum _RT_REGULATOR_MODE {
 320         RT_SWITCHING_REGULATOR = 0,
 321         RT_LDO_REGULATOR = 1,
 322 } RT_REGULATOR_MODE, *PRT_REGULATOR_MODE;
 323
 324 // Description: Determine the types of C2H events that are the same in driver and Fw.
 325 // Fisrt constructed by tynli. 2009.10.09.
 326 typedef enum _RTL8192C_C2H_EVT
 327 {
 328         C2H_DBG = 0,
 329         C2H_TSF = 1,
 330         C2H_AP_RPT_RSP = 2,
 331         C2H_CCX_TX_RPT = 3,     // The FW notify the report of the specific tx packet.
 332         C2H_BT_RSSI = 4,
 333         C2H_BT_OP_MODE = 5,
 334         C2H_EXT_RA_RPT = 6,
 335         C2H_HW_INFO_EXCH = 10,
 336         C2H_C2H_H2C_TEST = 11,
 337         C2H_BT_INFO = 12,
 338         C2H_BT_MP_INFO = 15,
 339         MAX_C2HEVENT
 340 } RTL8192C_C2H_EVT;
 341
 342 typedef struct hal_data_8723a
 343 {
 344         HAL_VERSION                     VersionID;
 345         RT_CUSTOMER_ID  CustomerID;
 346
 347         u16     FirmwareVersion;
 348         u16     FirmwareVersionRev;
 349         u16     FirmwareSubVersion;
 350         u16     FirmwareSignature;
 351
 352         //current WIFI_PHY values
 353         u32     ReceiveConfig;
 354         WIRELESS_MODE           CurrentWirelessMode;
 355         HT_CHANNEL_WIDTH        CurrentChannelBW;
 356         u8      CurrentChannel;
 357         u8      nCur40MhzPrimeSC;// Control channel sub-carrier
 358
 359         u16     BasicRateSet;
 360
 361         //rf_ctrl
 362         u8      rf_chip;
 363         u8      rf_type;
 364         u8      NumTotalRFPath;
 365
 366         u8      BoardType;
 367         u8      CrystalCap;
 368         //
 369         // EEPROM setting.
 370         //
 371         u8      EEPROMVersion;
 372         u16     EEPROMVID;
 373         u16     EEPROMPID;
 374         u16     EEPROMSVID;
 375         u16     EEPROMSDID;
 376         u8      EEPROMCustomerID;
 377         u8      EEPROMSubCustomerID;
 378         u8      EEPROMRegulatory;
 379         u8      EEPROMThermalMeter;
 380         u8      EEPROMBluetoothCoexist;
 381         u8      EEPROMBluetoothType;
 382         u8      EEPROMBluetoothAntNum;
 383         u8      EEPROMBluetoothAntIsolation;
 384         u8      EEPROMBluetoothRadioShared;
 385
 386         u8      bTXPowerDataReadFromEEPORM;
 387         u8      bAPKThermalMeterIgnore;
 388
 389         u8      bIQKInitialized;
 390         u8      bAntennaDetected;
 391
 392         u8      TxPwrLevelCck[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
 393         u8      TxPwrLevelHT40_1S[RF_PATH_MAX][CHANNEL_MAX_NUMBER];     // For HT 40MHZ pwr
 394         u8      TxPwrLevelHT40_2S[RF_PATH_MAX][CHANNEL_MAX_NUMBER];     // For HT 40MHZ pwr
 395         u8      TxPwrHt20Diff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];// HT 20<->40 Pwr diff
 396         u8      TxPwrLegacyHtDiff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];// For HT<->legacy pwr diff
 397         // For power group
 398         u8      PwrGroupHT20[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
 399         u8      PwrGroupHT40[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
 400
 401         u8      LegacyHTTxPowerDiff;// Legacy to HT rate power diff
 402
 403         // Read/write are allow for following hardware information variables
 404         u8      framesync;
 405         u32     framesyncC34;
 406         u8      framesyncMonitor;
 407         u8      DefaultInitialGain[4];
 408         u8      pwrGroupCnt;
 409         u32     MCSTxPowerLevelOriginalOffset[7][16];
 410         u32     CCKTxPowerLevelOriginalOffset;
 411
 412         u32     AntennaTxPath;                                  // Antenna path Tx
 413         u32     AntennaRxPath;                                  // Antenna path Rx
 414         u8      ExternalPA;
 415
 416         u8      bLedOpenDrain; // Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16.
 417
 418         //u32   LedControlNum;
 419         //u32   LedControlMode;
 420         //u32   TxPowerTrackControl;
 421         u8      b1x1RecvCombine;        // for 1T1R receive combining
 422
 423         // For EDCA Turbo mode
 424 //      u8      bIsAnyNonBEPkts; // Adapter->recvpriv.bIsAnyNonBEPkts
 425 //      u8      bCurrentTurboEDCA;
 426 //      u8      bForcedDisableTurboEDCA;
 427 //      u8      bIsCurRDLState; // pdmpriv->prv_traffic_idx
 428
 429         u32     AcParam_BE; //Original parameter for BE, use for EDCA turbo.
 430
 431         //vivi, for tx power tracking, 20080407
 432         //u16   TSSI_13dBm;
 433         //u32   Pwr_Track;
 434         // The current Tx Power Level
 435         u8      CurrentCckTxPwrIdx;
 436         u8      CurrentOfdm24GTxPwrIdx;
 437
 438         BB_REGISTER_DEFINITION_T        PHYRegDef[4];   //Radio A/B/C/D
 439
 440         bool            bRFPathRxEnable[4];     // We support 4 RF path now.
 441
 442         u32     RfRegChnlVal[2];
 443
 444         u8      bCckHighPower;
 445
 446         //RDG enable
 447         bool     bRDGEnable;
 448
 449         //for host message to fw
 450         u8      LastHMEBoxNum;
 451
 452         u8      fw_ractrl;
 453         u8      RegTxPause;
 454         // Beacon function related global variable.
 455         u32     RegBcnCtrlVal;
 456         u8      RegFwHwTxQCtrl;
 457         u8      RegReg542;
 458
 459         struct dm_priv  dmpriv;
 460         DM_ODM_T                odmpriv;
 461         //spinlock_t                    odm_stainfo_lock;
 462 #ifdef DBG_CONFIG_ERROR_DETECT
 463         struct sreset_priv srestpriv;
 464 #endif
 465
 466 #ifdef CONFIG_BT_COEXIST
 467         u8                              bBTMode;
 468         // BT only.
 469         BT30Info                BtInfo;
 470         // For bluetooth co-existance
 471         BT_COEXIST_STR  bt_coexist;
 472 #endif
 473
 474 #ifdef CONFIG_ANTENNA_DIVERSITY
 475         u8      CurAntenna;
 476
 477         // SW Antenna Switch
 478         s32     RSSI_sum_A;
 479         s32     RSSI_sum_B;
 480         s32     RSSI_cnt_A;
 481         s32     RSSI_cnt_B;
 482         u8      RSSI_test;
 483         u8      AntDivCfg;
 484 #endif
 485
 486         u8      bDumpRxPkt;//for debug
 487         u8      FwRsvdPageStartOffset; //2010.06.23. Added by tynli. Reserve page start offset except beacon in TxQ.
 488
 489         // 2010/08/09 MH Add CU power down mode.
 490         u8      pwrdown;
 491
 492         // Add for dual MAC  0--Mac0 1--Mac1
 493         u32     interfaceIndex;
 494
 495         u8      OutEpQueueSel;
 496         u8      OutEpNumber;
 497
 498         // 2010/12/10 MH Add for USB aggreation mode dynamic shceme.
 499         bool            UsbRxHighSpeedMode;
 500
 501         // 2010/11/22 MH Add for slim combo debug mode selective.
 502         // This is used for fix the drawback of CU TSMC-A/UMC-A cut. HW auto suspend ability. Close BT clock.
 503         bool            SlimComboDbg;
 504
 505         //
 506         // Add For EEPROM Efuse switch and  Efuse Shadow map Setting
 507         //
 508         u8                      EepromOrEfuse;
 509 //      u8                      EfuseMap[2][HWSET_MAX_SIZE_512]; //92C:256bytes, 88E:512bytes, we use union set (512bytes)
 510         u16                     EfuseUsedBytes;
 511         u8                      EfuseUsedPercentage;
 512 #ifdef HAL_EFUSE_MEMORY
 513         EFUSE_HAL       EfuseHal;
 514 #endif
 515
 516         // Interrupt relatd register information.
 517         u32                     SysIntrStatus;
 518         u32                     SysIntrMask;
 519
 520         //
 521         // 2011/02/23 MH Add for 8723 mylti function definition. The define should be moved to an
 522         // independent file in the future.
 523         //
 524         //------------------------8723-----------------------------------------//
 525         RT_MULTI_FUNC                   MultiFunc; // For multi-function consideration.
 526         RT_POLARITY_CTL                 PolarityCtl; // For Wifi PDn Polarity control.
 527         RT_REGULATOR_MODE               RegulatorMode; // switching regulator or LDO
 528         //------------------------8723-----------------------------------------//
 529         //
 530         // 2011/02/23 MH Add for 8723 mylti function definition. The define should be moved to an
 531         // independent file in the future.
 532
 533         bool                            bMACFuncEnable;
 534
 535 #ifdef CONFIG_P2P
 536         struct P2P_PS_Offload_t p2p_ps_offload;
 537 #endif
 538
 539
 540         //
 541         // For USB Interface HAL related
 542         //
 543         u32     UsbBulkOutSize;
 544
 545         // Interrupt related register information.
 546         u32     IntArray[2];
 547         u32     IntrMask[2];
 548
 549         //
 550         // For SDIO Interface HAL related
 551         //
 552
 553         // Auto FSM to Turn On, include clock, isolation, power control for MAC only
 554         u8                      bMacPwrCtrlOn;
 555
 556 } HAL_DATA_8723A, *PHAL_DATA_8723A;
 557
 558 typedef struct hal_data_8723a HAL_DATA_TYPE, *PHAL_DATA_TYPE;
 559
 560 #define GET_HAL_DATA(__pAdapter)        ((HAL_DATA_TYPE *)((__pAdapter)->HalData))
 561 #define GET_RF_TYPE(priv)                       (GET_HAL_DATA(priv)->rf_type)
 562
 563 #define INCLUDE_MULTI_FUNC_BT(_Adapter)         (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT)
 564 #define INCLUDE_MULTI_FUNC_GPS(_Adapter)        (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)
 565
 566 typedef struct rxreport_8723a
 567 {
 568         u32 pktlen:14;
 569         u32 crc32:1;
 570         u32 icverr:1;
 571         u32 drvinfosize:4;
 572         u32 security:3;
 573         u32 qos:1;
 574         u32 shift:2;
 575         u32 physt:1;
 576         u32 swdec:1;
 577         u32 ls:1;
 578         u32 fs:1;
 579         u32 eor:1;
 580         u32 own:1;
 581
 582         u32 macid:5;
 583         u32 tid:4;
 584         u32 hwrsvd:4;
 585         u32 amsdu:1;
 586         u32 paggr:1;
 587         u32 faggr:1;
 588         u32 a1fit:4;
 589         u32 a2fit:4;
 590         u32 pam:1;
 591         u32 pwr:1;
 592         u32 md:1;
 593         u32 mf:1;
 594         u32 type:2;
 595         u32 mc:1;
 596         u32 bc:1;
 597
 598         u32 seq:12;
 599         u32 frag:4;
 600         u32 nextpktlen:14;
 601         u32 nextind:1;
 602         u32 rsvd0831:1;
 603
 604         u32 rxmcs:6;
 605         u32 rxht:1;
 606         u32 gf:1;
 607         u32 splcp:1;
 608         u32 bw:1;
 609         u32 htc:1;
 610         u32 eosp:1;
 611         u32 bssidfit:2;
 612         u32 rsvd1214:16;
 613         u32 unicastwake:1;
 614         u32 magicwake:1;
 615
 616         u32 pattern0match:1;
 617         u32 pattern1match:1;
 618         u32 pattern2match:1;
 619         u32 pattern3match:1;
 620         u32 pattern4match:1;
 621         u32 pattern5match:1;
 622         u32 pattern6match:1;
 623         u32 pattern7match:1;
 624         u32 pattern8match:1;
 625         u32 pattern9match:1;
 626         u32 patternamatch:1;
 627         u32 patternbmatch:1;
 628         u32 patterncmatch:1;
 629         u32 rsvd1613:19;
 630
 631         u32 tsfl;
 632
 633         u32 bassn:12;
 634         u32 bavld:1;
 635         u32 rsvd2413:19;
 636 } RXREPORT, *PRXREPORT;
 637
 638 typedef struct phystatus_8723a
 639 {
 640         u32 rxgain_a:7;
 641         u32 trsw_a:1;
 642         u32 rxgain_b:7;
 643         u32 trsw_b:1;
 644         u32 chcorr_l:16;
 645
 646         u32 sigqualcck:8;
 647         u32 cfo_a:8;
 648         u32 cfo_b:8;
 649         u32 chcorr_h:8;
 650
 651         u32 noisepwrdb_h:8;
 652         u32 cfo_tail_a:8;
 653         u32 cfo_tail_b:8;
 654         u32 rsvd0824:8;
 655
 656         u32 rsvd1200:8;
 657         u32 rxevm_a:8;
 658         u32 rxevm_b:8;
 659         u32 rxsnr_a:8;
 660
 661         u32 rxsnr_b:8;
 662         u32 noisepwrdb_l:8;
 663         u32 rsvd1616:8;
 664         u32 postsnr_a:8;
 665
 666         u32 postsnr_b:8;
 667         u32 csi_a:8;
 668         u32 csi_b:8;
 669         u32 targetcsi_a:8;
 670
 671         u32 targetcsi_b:8;
 672         u32 sigevm:8;
 673         u32 maxexpwr:8;
 674         u32 exintflag:1;
 675         u32 sgien:1;
 676         u32 rxsc:2;
 677         u32 idlelong:1;
 678         u32 anttrainen:1;
 679         u32 antselb:1;
 680         u32 antsel:1;
 681 } PHYSTATUS, *PPHYSTATUS;
 682
 683
 684 // rtl8723a_hal_init.c
 685 int FirmwareDownloadBT(IN PADAPTER Adapter, PRT_FIRMWARE_8723A pFirmware);
 686 s32 rtl8723a_FirmwareDownload(PADAPTER padapter);
 687 void rtl8723a_FirmwareSelfReset(PADAPTER padapter);
 688 void rtl8723a_InitializeFirmwareVars(PADAPTER padapter);
 689
 690 void rtl8723a_InitAntenna_Selection(PADAPTER padapter);
 691 void rtl8723a_DeinitAntenna_Selection(PADAPTER padapter);
 692 void rtl8723a_CheckAntenna_Selection(PADAPTER padapter);
 693 void rtl8723a_init_default_value(PADAPTER padapter);
 694
 695 s32 InitLLTTable(PADAPTER padapter, u32 boundary);
 696
 697 s32 CardDisableHWSM(PADAPTER padapter, u8 resetMCU);
 698 s32 CardDisableWithoutHWSM(PADAPTER padapter);
 699
 700 // EFuse
 701 u8 GetEEPROMSize8723A(PADAPTER padapter);
 702 void Hal_InitPGData(PADAPTER padapter, u8 *PROMContent);
 703 void Hal_EfuseParseIDCode(PADAPTER padapter, u8 *hwinfo);
 704 void Hal_EfuseParseTxPowerInfo_8723A(PADAPTER padapter, u8 *PROMContent, bool AutoLoadFail);
 705 void Hal_EfuseParseBTCoexistInfo_8723A(PADAPTER padapter, u8 *hwinfo, bool AutoLoadFail);
 706 void Hal_EfuseParseEEPROMVer(PADAPTER padapter, u8 *hwinfo, bool AutoLoadFail);
 707 void rtl8723a_EfuseParseChnlPlan(PADAPTER padapter, u8 *hwinfo, bool AutoLoadFail);
 708 void Hal_EfuseParseCustomerID(PADAPTER padapter, u8 *hwinfo, bool AutoLoadFail);
 709 void Hal_EfuseParseAntennaDiversity(PADAPTER padapter, u8 *hwinfo, bool AutoLoadFail);
 710 void Hal_EfuseParseRateIndicationOption(PADAPTER padapter, u8 *hwinfo, bool AutoLoadFail);
 711 void Hal_EfuseParseXtal_8723A(PADAPTER pAdapter, u8 *hwinfo, u8 AutoLoadFail);
 712 void Hal_EfuseParseThermalMeter_8723A(PADAPTER padapter, u8 *hwinfo, u8 AutoLoadFail);
 713
 714 //RT_CHANNEL_DOMAIN rtl8723a_HalMapChannelPlan(PADAPTER padapter, u8 HalChannelPlan);
 715 //VERSION_8192C rtl8723a_ReadChipVersion(PADAPTER padapter);
 716 //void rtl8723a_ReadBluetoothCoexistInfo(PADAPTER padapter, u8 *PROMContent, bool AutoloadFail);
 717 void Hal_InitChannelPlan(PADAPTER padapter);
 718
 719 void rtl8723a_set_hal_ops(struct hal_ops *pHalFunc);
 720 void SetHwReg8723A(PADAPTER padapter, u8 variable, u8 *val);
 721 void GetHwReg8723A(PADAPTER padapter, u8 variable, u8 *val);
 722 #ifdef CONFIG_BT_COEXIST
 723 void rtl8723a_SingleDualAntennaDetection(PADAPTER padapter);
 724 #endif
 725
 726 // register
 727 void SetBcnCtrlReg(PADAPTER padapter, u8 SetBits, u8 ClearBits);
 728 void rtl8723a_InitBeaconParameters(PADAPTER padapter);
 729 void rtl8723a_InitBeaconMaxError(PADAPTER padapter, u8 InfraMode);
 730
 731 void rtl8723a_clone_haldata(_adapter *dst_adapter, _adapter *src_adapter);
 732 void rtl8723a_start_thread(_adapter *padapter);
 733 void rtl8723a_stop_thread(_adapter *padapter);
 734
 735 s32 c2h_id_filter_ccx_8723a(u8 id);
 736
 737
 738 #if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST)
 739 void rtl8723a_init_checkbthang_workqueue(_adapter * padapter);
 740 void rtl8723a_free_checkbthang_workqueue(_adapter * padapter);
 741 void rtl8723a_cancel_checkbthang_workqueue(_adapter * padapter);
 742 void rtl8723a_hal_check_bt_hang(_adapter * padapter);
 743 #endif
 744 #endif