0x30, 0xE0, 0x0A, 0x90, 0x00, 0x01, 0x12, 0x1F, 0x0F, 0x90, 0x93, 0xE1, 0xF0, 0x22, 0x7E, 0xBF,
};
-#ifdef CONFIG_MP_INCLUDED/* BT_MP 16980 const u1Byte Rtl8723EFwBTImgArray[Rtl8723EBTImgArrayLength] = { */
+#ifdef CONFIG_MP_INCLUDED/* BT_MP 16980 const u8 Rtl8723EFwBTImgArray[Rtl8723EBTImgArrayLength] = { */
u8 Rtl8723EFwBTImgArray[Rtl8723EBTImgArrayLength] = {
0xFB, 0x63, 0x08, 0x62, 0x07, 0xD1, 0x06, 0xD0, 0x4E, 0xB2, 0xCF, 0xF7, 0x12, 0x6B, 0x6B, 0xEB,
0x4F, 0xB4, 0x60, 0xCA, 0x4C, 0xB2, 0x68, 0xF1, 0x1A, 0x6B, 0x4E, 0xB5, 0x60, 0xCA, 0x4B, 0xB2,
u4Byte i = 0;
u2Byte count = 0;
pu4Byte ptr_array = NULL;
- u1Byte platform = pDM_Odm->SupportPlatform;
- u1Byte interfaceValue = pDM_Odm->SupportInterface;
- u1Byte board = pDM_Odm->BoardType;
+ u8 platform = pDM_Odm->SupportPlatform;
+ u8 interfaceValue = pDM_Odm->SupportInterface;
+ u8 board = pDM_Odm->BoardType;
u4Byte ArrayLen = sizeof(Array_AGC_TAB_1T_8723A)/sizeof(u4Byte);
pu4Byte Array = Array_AGC_TAB_1T_8723A;
u4Byte i = 0;
u2Byte count = 0;
pu4Byte ptr_array = NULL;
- u1Byte platform = pDM_Odm->SupportPlatform;
- u1Byte interfaceValue = pDM_Odm->SupportInterface;
- u1Byte board = pDM_Odm->BoardType;
+ u8 platform = pDM_Odm->SupportPlatform;
+ u8 interfaceValue = pDM_Odm->SupportInterface;
+ u8 board = pDM_Odm->BoardType;
u4Byte ArrayLen = sizeof(Array_PHY_REG_1T_8723A)/sizeof(u4Byte);
pu4Byte Array = Array_PHY_REG_1T_8723A;
u4Byte i = 0;
u2Byte count = 0;
pu4Byte ptr_array = NULL;
- u1Byte platform = pDM_Odm->SupportPlatform;
- u1Byte interfaceValue = pDM_Odm->SupportInterface;
- u1Byte board = pDM_Odm->BoardType;
+ u8 platform = pDM_Odm->SupportPlatform;
+ u8 interfaceValue = pDM_Odm->SupportInterface;
+ u8 board = pDM_Odm->BoardType;
u4Byte ArrayLen = sizeof(Array_PHY_REG_MP_8723A)/sizeof(u4Byte);
pu4Byte Array = Array_PHY_REG_MP_8723A;
u4Byte i = 0;
u2Byte count = 0;
pu4Byte ptr_array = NULL;
- u1Byte platform = pDM_Odm->SupportPlatform;
- u1Byte interfaceValue = pDM_Odm->SupportInterface;
- u1Byte board = pDM_Odm->BoardType;
+ u8 platform = pDM_Odm->SupportPlatform;
+ u8 interfaceValue = pDM_Odm->SupportInterface;
+ u8 board = pDM_Odm->BoardType;
u4Byte ArrayLen = sizeof(Array_PHY_REG_PG_8723A)/sizeof(u4Byte);
pu4Byte Array = Array_PHY_REG_PG_8723A;
u4Byte i = 0;
u2Byte count = 0;
pu4Byte ptr_array = NULL;
- u1Byte platform = pDM_Odm->SupportPlatform;
- u1Byte interfaceValue = pDM_Odm->SupportInterface;
- u1Byte board = pDM_Odm->BoardType;
+ u8 platform = pDM_Odm->SupportPlatform;
+ u8 interfaceValue = pDM_Odm->SupportInterface;
+ u8 board = pDM_Odm->BoardType;
u4Byte ArrayLen = sizeof(Array_MAC_REG_8723A)/sizeof(u4Byte);
pu4Byte Array = Array_MAC_REG_8723A;
// This (offset, data) pair meets the condition.
if ( v1 < 0xCDCDCDCD )
{
- odm_ConfigMAC_8723A(pDM_Odm, v1, (u1Byte)v2);
+ odm_ConfigMAC_8723A(pDM_Odm, v1, (u8)v2);
continue;
}
else
v2 != 0xCDEF &&
v2 != 0xCDCD && i < ArrayLen -2)
{
- odm_ConfigMAC_8723A(pDM_Odm, v1, (u1Byte)v2);
+ odm_ConfigMAC_8723A(pDM_Odm, v1, (u8)v2);
READ_NEXT_PAIR(v1, v2, i);
}
u4Byte i = 0;
u2Byte count = 0;
pu4Byte ptr_array = NULL;
- u1Byte platform = pDM_Odm->SupportPlatform;
- u1Byte interfaceValue = pDM_Odm->SupportInterface;
- u1Byte board = pDM_Odm->BoardType;
+ u8 platform = pDM_Odm->SupportPlatform;
+ u8 interfaceValue = pDM_Odm->SupportInterface;
+ u8 board = pDM_Odm->BoardType;
u4Byte ArrayLen = sizeof(Array_RadioA_1T_8723A)/sizeof(u4Byte);
pu4Byte Array = Array_RadioA_1T_8723A;
{ 17783, 19953, 22387, 25119, 28184, 31623, 35481, 39811, 44668, 50119, 56234, 65535}};
// 20100515 Joseph: Add global variable to keep temporary scan list for antenna switching test.
-//u1Byte tmpNumBssDesc;
+//u8 tmpNumBssDesc;
//RT_WLAN_BSS tmpbssDesc[MAX_BSS_DESC];
};
-u1Byte CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8] = {
+u8 CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8] = {
{0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, // 0, +0dB
{0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, // 1, -0.5dB
{0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, // 2, -1.0dB
};
-u1Byte CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8]= {
+u8 CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8]= {
{0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, // 0, +0dB
{0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, // 1, -0.5dB
{0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, // 2, -1.0dB
void
odm_DynamicTxPowerWritePowerIndex(
PDM_ODM_T pDM_Odm,
- u1Byte Value);
+ u8 Value);
void
odm_DynamicTxPower_92C(
void
odm_SwAntDivChkAntSwitch(
PDM_ODM_T pDM_Odm,
- u1Byte Step
+ u8 Step
);
void
odm_SwAntDivChkAntSwitchNIC(
PDM_ODM_T pDM_Odm,
- u1Byte Step
+ u8 Step
);
u4Byte OFDM_Ant2_Cnt,
u4Byte CCK_Ant1_Cnt,
u4Byte CCK_Ant2_Cnt,
- u1Byte *pDefAnt
+ u8 *pDefAnt
);
void
odm_SetRxIdleAnt(
PDM_ODM_T pDM_Odm,
- u1Byte Ant,
+ u8 Ant,
bool bDualPath
);
pDM_Odm->SupportAbility = (u4Byte)Value;
break;
case ODM_CMNINFO_PLATFORM:
- pDM_Odm->SupportPlatform = (u1Byte)Value;
+ pDM_Odm->SupportPlatform = (u8)Value;
break;
case ODM_CMNINFO_INTERFACE:
- pDM_Odm->SupportInterface = (u1Byte)Value;
+ pDM_Odm->SupportInterface = (u8)Value;
break;
case ODM_CMNINFO_MP_TEST_CHIP:
- pDM_Odm->bIsMPChip= (u1Byte)Value;
+ pDM_Odm->bIsMPChip= (u8)Value;
break;
case ODM_CMNINFO_IC_TYPE:
break;
case ODM_CMNINFO_CUT_VER:
- pDM_Odm->CutVersion = (u1Byte)Value;
+ pDM_Odm->CutVersion = (u8)Value;
break;
case ODM_CMNINFO_FAB_VER:
- pDM_Odm->FabVersion = (u1Byte)Value;
+ pDM_Odm->FabVersion = (u8)Value;
break;
case ODM_CMNINFO_RF_TYPE:
- pDM_Odm->RFType = (u1Byte)Value;
+ pDM_Odm->RFType = (u8)Value;
break;
case ODM_CMNINFO_RF_ANTENNA_TYPE:
- pDM_Odm->AntDivType= (u1Byte)Value;
+ pDM_Odm->AntDivType= (u8)Value;
break;
case ODM_CMNINFO_BOARD_TYPE:
- pDM_Odm->BoardType = (u1Byte)Value;
+ pDM_Odm->BoardType = (u8)Value;
break;
case ODM_CMNINFO_EXT_LNA:
- pDM_Odm->ExtLNA = (u1Byte)Value;
+ pDM_Odm->ExtLNA = (u8)Value;
break;
case ODM_CMNINFO_EXT_PA:
- pDM_Odm->ExtPA = (u1Byte)Value;
+ pDM_Odm->ExtPA = (u8)Value;
break;
case ODM_CMNINFO_EXT_TRSW:
- pDM_Odm->ExtTRSW = (u1Byte)Value;
+ pDM_Odm->ExtTRSW = (u8)Value;
break;
case ODM_CMNINFO_PATCH_ID:
- pDM_Odm->PatchID = (u1Byte)Value;
+ pDM_Odm->PatchID = (u8)Value;
break;
case ODM_CMNINFO_BINHCT_TEST:
pDM_Odm->bInHctTest = (bool)Value;
// Dynamic call by reference pointer.
//
case ODM_CMNINFO_MAC_PHY_MODE:
- pDM_Odm->pMacPhyMode = (u1Byte *)pValue;
+ pDM_Odm->pMacPhyMode = (u8 *)pValue;
break;
case ODM_CMNINFO_TX_UNI:
break;
case ODM_CMNINFO_WM_MODE:
- pDM_Odm->pWirelessMode = (u1Byte *)pValue;
+ pDM_Odm->pWirelessMode = (u8 *)pValue;
break;
case ODM_CMNINFO_BAND:
- pDM_Odm->pBandType = (u1Byte *)pValue;
+ pDM_Odm->pBandType = (u8 *)pValue;
break;
case ODM_CMNINFO_SEC_CHNL_OFFSET:
- pDM_Odm->pSecChOffset = (u1Byte *)pValue;
+ pDM_Odm->pSecChOffset = (u8 *)pValue;
break;
case ODM_CMNINFO_SEC_MODE:
- pDM_Odm->pSecurity = (u1Byte *)pValue;
+ pDM_Odm->pSecurity = (u8 *)pValue;
break;
case ODM_CMNINFO_BW:
- pDM_Odm->pBandWidth = (u1Byte *)pValue;
+ pDM_Odm->pBandWidth = (u8 *)pValue;
break;
case ODM_CMNINFO_CHNL:
- pDM_Odm->pChannel = (u1Byte *)pValue;
+ pDM_Odm->pChannel = (u8 *)pValue;
break;
case ODM_CMNINFO_DMSP_GET_VALUE:
break;
case ODM_CMNINFO_ONE_PATH_CCA:
- pDM_Odm->pOnePathCCA = (u1Byte *)pValue;
+ pDM_Odm->pOnePathCCA = (u8 *)pValue;
break;
case ODM_CMNINFO_DRV_STOP:
break;
case ODM_CMNINFO_ANT_TEST:
- pDM_Odm->pAntennaTest = (u1Byte *)pValue;
+ pDM_Odm->pAntennaTest = (u8 *)pValue;
break;
case ODM_CMNINFO_NET_CLOSED:
break;
case ODM_CMNINFO_RF_TYPE:
- pDM_Odm->RFType = (u1Byte)Value;
+ pDM_Odm->RFType = (u8)Value;
break;
case ODM_CMNINFO_WIFI_DIRECT:
break;
case ODM_CMNINFO_RSSI_MIN:
- pDM_Odm->RSSI_Min= (u1Byte)Value;
+ pDM_Odm->RSSI_Min= (u8)Value;
break;
case ODM_CMNINFO_DBG_COMP:
pDM_Odm->DebugLevel = (u4Byte)Value;
break;
case ODM_CMNINFO_RA_THRESHOLD_HIGH:
- pDM_Odm->RateAdaptive.HighRSSIThresh = (u1Byte)Value;
+ pDM_Odm->RateAdaptive.HighRSSIThresh = (u8)Value;
break;
case ODM_CMNINFO_RA_THRESHOLD_LOW:
- pDM_Odm->RateAdaptive.LowRSSIThresh = (u1Byte)Value;
+ pDM_Odm->RateAdaptive.LowRSSIThresh = (u8)Value;
break;
#if(BT_30_SUPPORT == 1)
// The following is for BT HS mode and BT coexist mechanism.
break;
case ODM_CMNINFO_BT_DIG:
- pDM_Odm->btHsDigVal = (u1Byte)Value;
+ pDM_Odm->btHsDigVal = (u8)Value;
break;
case ODM_CMNINFO_BT_BUSY:
)
{
pDM_Odm->bCckHighPower = (bool) ODM_GetBBReg(pDM_Odm, 0x824, BIT9);
- pDM_Odm->RFPathRxEnable = (u1Byte) ODM_GetBBReg(pDM_Odm, 0xc04, 0x0F);
+ pDM_Odm->RFPathRxEnable = (u8) ODM_GetBBReg(pDM_Odm, 0xc04, 0x0F);
if(pDM_Odm->SupportICType & (ODM_RTL8192C|ODM_RTL8192D))
{
#if(defined(CONFIG_HW_ANTENNA_DIVERSITY))
PDM_ODM_T pDM_Odm
)
{
- u1Byte EntryCnt=0;
- u1Byte i;
+ u8 EntryCnt=0;
+ u8 i;
PSTA_INFO_T pEntry;
if(*(pDM_Odm->pBandWidth) == ODM_BW40M)
)
{
u4Byte i;
- u1Byte RSSI_Min = 0xFF;
+ u8 RSSI_Min = 0xFF;
for(i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++)
{
{
if(DM_Value > 30)
DM_Value = 30;
- pDM_DigTable->BackoffVal = (u1Byte)DM_Value;
+ pDM_DigTable->BackoffVal = (u8)DM_Value;
}
else if(DM_Type == DIG_TYPE_RX_GAIN_MIN)
{
if(DM_Value == 0)
DM_Value = 0x1;
- pDM_DigTable->rx_gain_range_min = (u1Byte)DM_Value;
+ pDM_DigTable->rx_gain_range_min = (u8)DM_Value;
}
else if(DM_Type == DIG_TYPE_RX_GAIN_MAX)
{
if(DM_Value > 0x50)
DM_Value = 0x50;
- pDM_DigTable->rx_gain_range_max = (u1Byte)DM_Value;
+ pDM_DigTable->rx_gain_range_max = (u8)DM_Value;
}
} /* DM_ChangeDynamicInitGainThresh */
void
ODM_Write_DIG(
PDM_ODM_T pDM_Odm,
- u1Byte CurrentIGI
+ u8 CurrentIGI
)
{
pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable;
PADAPTER pAdapter =pDM_Odm->Adapter;
pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable;
PFALSE_ALARM_STATISTICS pFalseAlmCnt = &pDM_Odm->FalseAlmCnt;
- u1Byte RSSI_Lower=DM_DIG_MIN_NIC; //0x1E or 0x1C
- u1Byte bFwCurrentInPSMode = FALSE;
- u1Byte CurrentIGI=pDM_Odm->RSSI_Min;
+ u8 RSSI_Lower=DM_DIG_MIN_NIC; //0x1E or 0x1C
+ u8 bFwCurrentInPSMode = FALSE;
+ u8 CurrentIGI=pDM_Odm->RSSI_Min;
if(! (pDM_Odm->SupportICType & (ODM_RTL8723A |ODM_RTL8188E)))
return;
//pDM_DigTable->Dig_Enable_Flag = TRUE;
//pDM_DigTable->Dig_Ext_Port_Stage = DIG_EXT_PORT_STAGE_MAX;
- pDM_DigTable->CurIGValue = (u1Byte) ODM_GetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm));
+ pDM_DigTable->CurIGValue = (u8) ODM_GetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm));
//pDM_DigTable->PreIGValue = 0x0;
//pDM_DigTable->CurSTAConnectState = pDM_DigTable->PreSTAConnectState = DIG_STA_DISCONNECT;
//pDM_DigTable->CurMultiSTAConnectState = DIG_MultiSTA_DISCONNECT;
pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable;
PFALSE_ALARM_STATISTICS pFalseAlmCnt = &pDM_Odm->FalseAlmCnt;
pRXHP_T pRX_HP_Table = &pDM_Odm->DM_RXHP_Table;
- u1Byte DIG_Dynamic_MIN;
- u1Byte DIG_MaxOfMin;
+ u8 DIG_Dynamic_MIN;
+ u8 DIG_MaxOfMin;
bool FirstConnect, FirstDisConnect;
- u1Byte dm_dig_max, dm_dig_min;
- u1Byte CurrentIGI = pDM_DigTable->CurIGValue;
+ u8 dm_dig_max, dm_dig_min;
+ u8 CurrentIGI = pDM_DigTable->CurIGValue;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG()==>\n"));
{
if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)
{
- DIG_Dynamic_MIN = (u1Byte) pDM_DigTable->AntDiv_RSSI_max;
+ DIG_Dynamic_MIN = (u8) pDM_DigTable->AntDiv_RSSI_max;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_DIG(): pDM_DigTable->AntDiv_RSSI_max=%d \n",pDM_DigTable->AntDiv_RSSI_max));
}
}
{
pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable;
- u1Byte CurCCK_CCAThres;
+ u8 CurCCK_CCAThres;
PFALSE_ALARM_STATISTICS FalseAlmCnt = &(pDM_Odm->FalseAlmCnt);
if(!(pDM_Odm->SupportAbility & (ODM_BB_CCK_PD|ODM_BB_FA_CNT)))
void
ODM_Write_CCK_CCA_Thres(
PDM_ODM_T pDM_Odm,
- u1Byte CurCCK_CCAThres
+ u8 CurCCK_CCAThres
)
{
pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable;
void
ODM_RF_Saving(
PDM_ODM_T pDM_Odm,
- u1Byte bForceInNormal
+ u8 bForceInNormal
)
{
pPS_T pDM_PSTable = &pDM_Odm->DM_PSTable;
- u1Byte Rssi_Up_bound = 30 ;
- u1Byte Rssi_Low_bound = 25;
+ u8 Rssi_Up_bound = 30 ;
+ u8 Rssi_Low_bound = 25;
if(pDM_Odm->PatchID == 40 ) //RT_CID_819x_FUNAI_TV
{
Rssi_Up_bound = 50 ;
PDM_ODM_T pDM_Odm,
u4Byte macid,
u4Byte ra_mask,
- u1Byte rssi_level)
+ u8 rssi_level)
{
PSTA_INFO_T pEntry;
u4Byte rate_bitmap = 0x0fffffff;
- u1Byte WirelessMode;
- //u1Byte WirelessMode =*(pDM_Odm->pWirelessMode);
+ u8 WirelessMode;
+ //u8 WirelessMode =*(pDM_Odm->pWirelessMode);
pEntry = pDM_Odm->pODM_StaInfo[macid];
PDM_ODM_T pDM_Odm
)
{
- u1Byte i;
+ u8 i;
PADAPTER pAdapter = pDM_Odm->Adapter;
if(pAdapter->bDriverStopped)
)
{
PODM_RATE_ADAPTIVE pRA = &pDM_Odm->RateAdaptive;
- const u1Byte GoUpGap = 5;
- u1Byte HighRSSIThreshForRA = pRA->HighRSSIThresh;
- u1Byte LowRSSIThreshForRA = pRA->LowRSSIThresh;
- u1Byte RATRState;
+ const u8 GoUpGap = 5;
+ u8 HighRSSIThreshForRA = pRA->HighRSSIThresh;
+ u8 LowRSSIThreshForRA = pRA->LowRSSIThresh;
+ u8 RATRState;
// Threshold Adjustment:
// when RSSI state trends to go up one or two levels, make sure RSSI is high enough.
PDM_ODM_T pDM_Odm
)
{
- u1Byte index;
+ u8 index;
u4Byte Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a};
PADAPTER Adapter = pDM_Odm->Adapter;
PDM_ODM_T pDM_Odm
)
{
- u1Byte index;
+ u8 index;
PADAPTER Adapter = pDM_Odm->Adapter;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
void
odm_DynamicTxPowerWritePowerIndex(
PDM_ODM_T pDM_Odm,
- u1Byte Value)
+ u8 Value)
{
- u1Byte index;
+ u8 index;
u4Byte Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a};
for(index = 0; index< 6; index++)
{
pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
PADAPTER Adapter = pDM_Odm->Adapter;
- u1Byte btAntNum=BT_GetPGAntNum(Adapter);
+ u8 btAntNum=BT_GetPGAntNum(Adapter);
pDM_SWAT_Table->ANTA_ON =TRUE;
void
ODM_SwAntDivChkPerPktRssi(
PDM_ODM_T pDM_Odm,
- u1Byte StationID,
+ u8 StationID,
PODM_PHY_INFO_T pPhyInfo
)
{
void
odm_SwAntDivChkAntSwitch(
PDM_ODM_T pDM_Odm,
- u1Byte Step
+ u8 Step
)
{
//
void
ODM_SetAntenna(
PDM_ODM_T pDM_Odm,
- u1Byte Antenna)
+ u8 Antenna)
{
ODM_SetBBReg(pDM_Odm, 0x860, BIT8|BIT9, Antenna);
}
void
odm_SwAntDivChkAntSwitchNIC(
PDM_ODM_T pDM_Odm,
- u1Byte Step
+ u8 Step
)
{
#if ((RTL8192C_SUPPORT==1)||(RTL8723A_SUPPORT==1))
//HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
s4Byte curRSSI=100, RSSI_A, RSSI_B;
- u1Byte nextAntenna=Antenna_B;
+ u8 nextAntenna=Antenna_B;
//static u8Byte lastTxOkCnt=0, lastRxOkCnt=0;
u8Byte curTxOkCnt, curRxOkCnt;
//static u8Byte TXByteCnt_A=0, TXByteCnt_B=0, RXByteCnt_A=0, RXByteCnt_B=0;
u8Byte CurByteCnt=0, PreByteCnt=0;
- //static u1Byte TrafficLoad = TRAFFIC_LOW;
- u1Byte Score_A=0, Score_B=0;
- u1Byte i;
+ //static u8 TrafficLoad = TRAFFIC_LOW;
+ u8 Score_A=0, Score_B=0;
+ u8 i;
if(!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV))
return;
pDM_SWAT_Table->RSSI_target = 0xff;
{
- u1Byte index = 0;
+ u8 index = 0;
PSTA_INFO_T pEntry = NULL;
void odm_SwAntDivInit( PDM_ODM_T pDM_Odm ) {}
void ODM_SwAntDivChkPerPktRssi(
PDM_ODM_T pDM_Odm,
- u1Byte StationID,
+ u8 StationID,
PODM_PHY_INFO_T pPhyInfo
) {}
void odm_SwAntDivChkAntSwitch(
PDM_ODM_T pDM_Odm,
- u1Byte Step
+ u8 Step
) {}
void ODM_SwAntDivResetBeforeLink( PDM_ODM_T pDM_Odm ){}
void ODM_SwAntDivRestAfterLink( PDM_ODM_T pDM_Odm ){}
{
SWAT_T *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
- u1Byte bTxPathSel=0; //0:Path-A 1:Path-B
- u1Byte i;
+ u8 bTxPathSel=0; //0:Path-A 1:Path-B
+ u8 i;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("odm_InitHybridAntDiv==============>\n"));
u4Byte OFDM_Ant2_Cnt,
u4Byte CCK_Ant1_Cnt,
u4Byte CCK_Ant2_Cnt,
- u1Byte *pDefAnt
+ u8 *pDefAnt
)
{
#endif
//u4Byte antsel = ODM_GetBBReg(pDM_Odm, 0xc88, bMaskByte0);
- //(*pDefAnt)= (u1Byte) antsel;
+ //(*pDefAnt)= (u8) antsel;
void
odm_SetRxIdleAnt(
PDM_ODM_T pDM_Odm,
- u1Byte Ant,
+ u8 Ant,
bool bDualPath
)
{
void
ODM_AntselStatistics_88C(
PDM_ODM_T pDM_Odm,
- u1Byte MacId,
+ u8 MacId,
u4Byte PWDBAll,
bool isCCKrate
)
{
SWAT_T *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
u4Byte RSSI_Min=0xFF, RSSI, RSSI_Ant1, RSSI_Ant2;
- u1Byte RxIdleAnt, i;
+ u8 RxIdleAnt, i;
bool bRet=FALSE;
PSTA_INFO_T pEntry;
GetPSDData(
PDM_ODM_T pDM_Odm,
unsigned int point,
- u1Byte initial_gain_psd)
+ u8 initial_gain_psd)
{
//unsigned int val, rfval;
//int psd_report;
ConvertTo_dB(
u4Byte Value)
{
- u1Byte i;
- u1Byte j;
+ u8 i;
+ u8 j;
u4Byte dB;
Value = Value & 0xFFFF;
bool
ODM_SingleDualAntennaDetection(
PDM_ODM_T pDM_Odm,
- u1Byte mode
+ u8 mode
)
{
//PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc;
pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
u4Byte CurrentChannel,RfLoopReg;
- u1Byte n;
+ u8 n;
u4Byte Reg88c, Regc08, Reg874, Regc50;
- u1Byte initial_gain = 0x5a;
+ u8 initial_gain = 0x5a;
u4Byte PSD_report_tmp;
u4Byte AntA_report = 0x0, AntB_report = 0x0,AntO_report=0x0;
bool bResult = TRUE;
#define READ_AND_CONFIG_MP(ic, txt) (ODM_ReadAndConfig##txt##ic(pDM_Odm))
#define READ_AND_CONFIG_TC(ic, txt) (ODM_ReadAndConfig_TC##txt##ic(pDM_Odm))
-u1Byte
+u8
odm_QueryRxPwrPercentage(
s1Byte AntPower
)
#endif
//pMgntInfo->CustomerID == RT_CID_819x_Lenovo
-static u1Byte odm_SQ_process_patch_RT_CID_819x_Lenovo(
+static u8 odm_SQ_process_patch_RT_CID_819x_Lenovo(
PDM_ODM_T pDM_Odm,
- u1Byte isCCKrate,
- u1Byte PWDB_ALL,
- u1Byte path,
- u1Byte RSSI
+ u8 isCCKrate,
+ u8 PWDB_ALL,
+ u8 path,
+ u8 RSSI
)
{
- u1Byte SQ;
+ u8 SQ;
#if (DM_ODM_SUPPORT_TYPE & ODM_MP)
// mapping to 5 bars for vista signal strength
// signal quality in driver will be displayed to signal strength
return SQ;
}
-static u1Byte
+static u8
odm_EVMdbToPercentage(
s1Byte Value
)
)
{
SWAT_T *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
- u1Byte i, Max_spatial_stream;
+ u8 i, Max_spatial_stream;
s1Byte rx_pwr[4], rx_pwr_all=0;
- u1Byte EVM, PWDB_ALL = 0, PWDB_ALL_BT;
- u1Byte RSSI, total_rssi=0;
- u1Byte isCCKrate=0;
- u1Byte rf_rx_num = 0;
- u1Byte cck_highpwr = 0;
- u1Byte LNA_idx, VGA_idx;
+ u8 EVM, PWDB_ALL = 0, PWDB_ALL_BT;
+ u8 RSSI, total_rssi=0;
+ u8 isCCKrate=0;
+ u8 rf_rx_num = 0;
+ u8 cck_highpwr = 0;
+ u8 LNA_idx, VGA_idx;
PPHY_STATUS_RPT_8192CD_T pPhyStaRpt = (PPHY_STATUS_RPT_8192CD_T)pPhyStatus;
if(isCCKrate) {
- u1Byte report;
- u1Byte cck_agc_rpt;
+ u8 report;
+ u8 cck_agc_rpt;
pDM_Odm->PhyDbgInfo.NumQryPhyStatusCCK++;
//
//
if(pPktinfo->bPacketMatchBSSID)
{
- u1Byte SQ,SQ_rpt;
+ u8 SQ,SQ_rpt;
if((pDM_Odm->SupportPlatform == ODM_MP) &&(pDM_Odm->PatchID==19)){//pMgntInfo->CustomerID == RT_CID_819x_Lenovo
SQ = odm_SQ_process_patch_RT_CID_819x_Lenovo(pDM_Odm,isCCKrate,PWDB_ALL,0,0);
RSSI -= 4;
}
- pPhyInfo->RxMIMOSignalStrength[i] =(u1Byte) RSSI;
+ pPhyInfo->RxMIMOSignalStrength[i] =(u8) RSSI;
#if (DM_ODM_SUPPORT_TYPE & (/*ODM_MP|*/ODM_CE|ODM_AP|ODM_ADSL))
//Get Rx snr value in DB
{
if(i==ODM_RF_PATH_A) // Fill value in RFD, Get the first spatial stream only
{
- pPhyInfo->SignalQuality = (u1Byte)(EVM & 0xff);
+ pPhyInfo->SignalQuality = (u8)(EVM & 0xff);
}
- pPhyInfo->RxMIMOSignalQuality[i] = (u1Byte)(EVM & 0xff);
+ pPhyInfo->RxMIMOSignalQuality[i] = (u8)(EVM & 0xff);
}
}
}
{
#if (DM_ODM_SUPPORT_TYPE == ODM_MP)
// 2012/01/12 MH Use customeris signal strength from HalComRxdDesc.c/
- pPhyInfo->SignalStrength = (u1Byte)(SignalScaleMapping(pDM_Odm->Adapter, PWDB_ALL));//PWDB_ALL;
+ pPhyInfo->SignalStrength = (u8)(SignalScaleMapping(pDM_Odm->Adapter, PWDB_ALL));//PWDB_ALL;
#else
- pPhyInfo->SignalStrength = (u1Byte)(odm_SignalScaleMapping(pDM_Odm, PWDB_ALL));//PWDB_ALL;
+ pPhyInfo->SignalStrength = (u8)(odm_SignalScaleMapping(pDM_Odm, PWDB_ALL));//PWDB_ALL;
#endif
}
else
{
#if (DM_ODM_SUPPORT_TYPE == ODM_MP)
// 2012/01/12 MH Use customeris signal strength from HalComRxdDesc.c/
- pPhyInfo->SignalStrength = (u1Byte)(SignalScaleMapping(pDM_Odm->Adapter, total_rssi/=rf_rx_num));//PWDB_ALL;
+ pPhyInfo->SignalStrength = (u8)(SignalScaleMapping(pDM_Odm->Adapter, total_rssi/=rf_rx_num));//PWDB_ALL;
#else
- pPhyInfo->SignalStrength = (u1Byte)(odm_SignalScaleMapping(pDM_Odm, total_rssi/=rf_rx_num));
+ pPhyInfo->SignalStrength = (u8)(odm_SignalScaleMapping(pDM_Odm, total_rssi/=rf_rx_num));
#endif
}
}
{
s4Byte UndecoratedSmoothedPWDB, UndecoratedSmoothedCCK, UndecoratedSmoothedOFDM, RSSI_Ave;
- u1Byte isCCKrate=0;
- u1Byte RSSI_max, RSSI_min, i;
+ u8 isCCKrate=0;
+ u8 RSSI_max, RSSI_min, i;
u4Byte OFDM_pkt=0;
u4Byte Weighting=0;
PSTA_INFO_T pEntry;
#if (RTL8188E_SUPPORT == 1)
if(pDM_Odm->SupportICType == ODM_RTL8188E)
{
- u1Byte antsel_tr_mux;
+ u8 antsel_tr_mux;
pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
if(pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV)
pEntry->rssi_stat.ValidBit++;
for(i=0; i<pEntry->rssi_stat.ValidBit; i++)
- OFDM_pkt += (u1Byte)(pEntry->rssi_stat.PacketMap>>i)&BIT0;
+ OFDM_pkt += (u8)(pEntry->rssi_stat.PacketMap>>i)&BIT0;
if(pEntry->rssi_stat.ValidBit == 64)
{
ODM_MacStatusQuery(
PDM_ODM_T pDM_Odm,
u8 * pMacStatus,
- u1Byte MacID,
+ u8 MacID,
bool bPacketMatchBSSID,
bool bPacketToSelf,
bool bPacketBeacon
PDM_ODM_T pDM_Odm
)
{
- u1Byte result = HAL_STATUS_SUCCESS;
+ u8 result = HAL_STATUS_SUCCESS;
#if (RTL8723A_SUPPORT == 1)
if (pDM_Odm->SupportICType == ODM_RTL8723A)
{
odm_ConfigMAC_8723A(
PDM_ODM_T pDM_Odm,
u4Byte Addr,
- u1Byte Data
+ u8 Data
)
{
ODM_Write1Byte(pDM_Odm, Addr, Data);
// ODM IO Relative API.
//
-u1Byte
+u8
ODM_Read1Byte(
PDM_ODM_T pDM_Odm,
u4Byte RegAddr
ODM_Write1Byte(
PDM_ODM_T pDM_Odm,
u4Byte RegAddr,
- u1Byte Data
+ u8 Data
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
void
ODM_FillH2CCmd(
PADAPTER Adapter,
- u1Byte ElementID,
+ u8 ElementID,
u4Byte CmdLen,
u8 * pCmdBuffer
)
void btdm_SetFwDacSwingLevel(PADAPTER padapter, u8 dacSwingLvl)
{
- u1Byte H2C_Parameter[1] ={0};
+ u8 H2C_Parameter[1] ={0};
H2C_Parameter[0] = dacSwingLvl;
if(pBtdm8723->bPreLowPenaltyRa == pBtdm8723->bCurLowPenaltyRa)
return;
- BTDM_SetSwPenaltyTxRateAdaptive(padapter, (u1Byte)pBtdm8723->bCurLowPenaltyRa);
+ BTDM_SetSwPenaltyTxRateAdaptive(padapter, (u8)pBtdm8723->bCurLowPenaltyRa);
pBtdm8723->bPreLowPenaltyRa = pBtdm8723->bCurLowPenaltyRa;
}
PBT_MGNT pBtMgnt = &pBTInfo->BtMgnt;
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter);
PBTDM_8723A_2ANT pBtdm8723 = &pHalData->bt_coexist.halCoex8723.btdm2Ant;
- u1Byte btInfo=0;
+ u8 btInfo=0;
u8 algorithm=BT_2ANT_COEX_ALGO_UNDEFINED;
u8 bScoExist=_FALSE, bBtLinkExist=_FALSE, bBtHsModeExist=_FALSE;
btInfo = pHalData->bt_coexist.halCoex8723.c2hBtInfoOriginal;
// Pointer reference
//
//ODM_CMNINFO_MAC_PHY_MODE pHalData->MacPhyMode92D
- // ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_MAC_PHY_MODE,&(pDM_Odm->u1Byte_temp));
+ // ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_MAC_PHY_MODE,&(pDM_Odm->u8_temp));
#ifdef CONFIG_ANTENNA_DIVERSITY
//================= only for 8192D =================
/*
//pHalData->CurrentBandType92D
- ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_BAND,&(pDM_Odm->u1Byte_temp));
- ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_DMSP_GET_VALUE,&(pDM_Odm->u1Byte_temp));
+ ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_BAND,&(pDM_Odm->u8_temp));
+ ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_DMSP_GET_VALUE,&(pDM_Odm->u8_temp));
ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_BUDDY_ADAPTOR,&(pDM_Odm->PADAPTER_temp));
- ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_DMSP_IS_MASTER,&(pDM_Odm->u1Byte_temp));
+ ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_DMSP_IS_MASTER,&(pDM_Odm->u8_temp));
//================= only for 8192D =================
// driver havn't those variable now
- ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_BT_OPERATION,&(pDM_Odm->u1Byte_temp));
- ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_BT_DISABLE_EDCA,&(pDM_Odm->u1Byte_temp));
+ ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_BT_OPERATION,&(pDM_Odm->u8_temp));
+ ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_BT_DISABLE_EDCA,&(pDM_Odm->u8_temp));
*/
ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_SCAN,&(pmlmepriv->bScanInProcess));
{
//HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
- //u1Byte RFWaitCounter = 0;
+ //u8 RFWaitCounter = 0;
u32 Original_Value, BitShift;
//_irqL irqL;
* Read/Write
*
* Input: PADAPTER Adapter
- * u1Byte ConfigType 0 => PHY_CONFIG
+ * u8 ConfigType 0 => PHY_CONFIG
* 1 =>AGC_TAB
*
* Output: NONE
* We must consider RF path later!!!!!!!
*
* Input: PADAPTER Adapter
- * u1Byte channel
+ * u8 channel
*
* Output: NONE
*
if (AutoLoadFail)
{
-// sMacAddr[5] = (u1Byte)GetRandomNumber(1, 254);
+// sMacAddr[5] = (u8)GetRandomNumber(1, 254);
for (i=0; i<6; i++)
pEEPROM->mac_addr[i] = sMacAddr[i];
}
void
ODM_ReadFirmware_8723A_rtl8723fw_B(
PDM_ODM_T pDM_Odm,
- u1Byte *pFirmware,
+ u8 *pFirmware,
u4Byte *pFirmwareSize
);
EF1Byte( \
LE_BITS_CLEARED_TO_1BYTE_8BIT(__pStart, __BitOffset, __BitLen) \
| \
- ((u1Byte)__Value) \
+ ((u8)__Value) \
); \
}
// We need to remove to other position???
//
typedef struct rtl8192cd_priv {
- u1Byte temp;
+ u8 temp;
}rtl8192cd_priv, *prtl8192cd_priv;
typedef struct _Dynamic_Initial_Gain_Threshold_
{
- u1Byte Dig_Enable_Flag;
- u1Byte Dig_Ext_Port_Stage;
+ u8 Dig_Enable_Flag;
+ u8 Dig_Ext_Port_Stage;
int RssiLowThresh;
int RssiHighThresh;
u4Byte FALowThresh;
u4Byte FAHighThresh;
- u1Byte CurSTAConnectState;
- u1Byte PreSTAConnectState;
- u1Byte CurMultiSTAConnectState;
+ u8 CurSTAConnectState;
+ u8 PreSTAConnectState;
+ u8 CurMultiSTAConnectState;
- u1Byte PreIGValue;
- u1Byte CurIGValue;
- u1Byte BackupIGValue;
+ u8 PreIGValue;
+ u8 CurIGValue;
+ u8 BackupIGValue;
s1Byte BackoffVal;
s1Byte BackoffVal_range_max;
s1Byte BackoffVal_range_min;
- u1Byte rx_gain_range_max;
- u1Byte rx_gain_range_min;
- u1Byte Rssi_val_min;
+ u8 rx_gain_range_max;
+ u8 rx_gain_range_min;
+ u8 Rssi_val_min;
- u1Byte PreCCK_CCAThres;
- u1Byte CurCCK_CCAThres;
- u1Byte PreCCKPDState;
- u1Byte CurCCKPDState;
+ u8 PreCCK_CCAThres;
+ u8 CurCCK_CCAThres;
+ u8 PreCCKPDState;
+ u8 CurCCKPDState;
- u1Byte LargeFAHit;
- u1Byte ForbiddenIGI;
+ u8 LargeFAHit;
+ u8 ForbiddenIGI;
u4Byte Recover_cnt;
- u1Byte DIG_Dynamic_MIN_0;
- u1Byte DIG_Dynamic_MIN_1;
+ u8 DIG_Dynamic_MIN_0;
+ u8 DIG_Dynamic_MIN_1;
bool bMediaConnect_0;
bool bMediaConnect_1;
typedef struct _Dynamic_Power_Saving_
{
- u1Byte PreCCAState;
- u1Byte CurCCAState;
+ u8 PreCCAState;
+ u8 CurCCAState;
- u1Byte PreRFState;
- u1Byte CurRFState;
+ u8 PreRFState;
+ u8 CurRFState;
int Rssi_val_min;
- u1Byte initialize;
+ u8 initialize;
u4Byte Reg874,RegC70,Reg85C,RegA74;
}PS_T,*pPS_T;
}FALSE_ALARM_STATISTICS, *PFALSE_ALARM_STATISTICS;
typedef struct _Dynamic_Primary_CCA{
- u1Byte PriCCA_flag;
- u1Byte intf_flag;
- u1Byte intf_type;
- u1Byte DupRTS_flag;
- u1Byte Monitor_flag;
+ u8 PriCCA_flag;
+ u8 intf_flag;
+ u8 intf_type;
+ u8 DupRTS_flag;
+ u8 Monitor_flag;
}Pri_CCA_T, *pPri_CCA_T;
typedef struct _RX_High_Power_
{
- u1Byte RXHP_flag;
- u1Byte PSD_func_trigger;
- u1Byte PSD_bitmap_RXHP[80];
- u1Byte Pre_IGI;
- u1Byte Cur_IGI;
- u1Byte Pre_pw_th;
- u1Byte Cur_pw_th;
+ u8 RXHP_flag;
+ u8 PSD_func_trigger;
+ u8 PSD_bitmap_RXHP[80];
+ u8 Pre_IGI;
+ u8 Cur_IGI;
+ u8 Pre_pw_th;
+ u8 Cur_pw_th;
bool First_time_enter;
bool RXHP_enable;
- u1Byte TP_Mode;
+ u8 TP_Mode;
RT_TIMER PSDTimer;
}RXHP_T, *pRXHP_T;
typedef struct _SW_Antenna_Switch_
{
- u1Byte try_flag;
+ u8 try_flag;
s4Byte PreRSSI;
- u1Byte CurAntenna;
- u1Byte PreAntenna;
- u1Byte RSSI_Trying;
- u1Byte TestMode;
- u1Byte bTriggerAntennaSwitch;
- u1Byte SelectAntennaMap;
- u1Byte RSSI_target;
+ u8 CurAntenna;
+ u8 PreAntenna;
+ u8 RSSI_Trying;
+ u8 TestMode;
+ u8 bTriggerAntennaSwitch;
+ u8 SelectAntennaMap;
+ u8 RSSI_target;
// Before link Antenna Switch check
- u1Byte SWAS_NoLink_State;
+ u8 SWAS_NoLink_State;
u4Byte SWAS_NoLink_BK_Reg860;
bool ANTA_ON; //To indicate Ant A is or not
bool ANTB_ON; //To indicate Ant B is on or not
u8Byte TXByteCnt_B;
u8Byte RXByteCnt_A;
u8Byte RXByteCnt_B;
- u1Byte TrafficLoad;
+ u8 TrafficLoad;
RT_TIMER SwAntennaSwitchTimer;
/* CE Platform use
#ifdef CONFIG_SW_ANTENNA_DIVERSITY
u8Byte TXByteCnt_B;
u8Byte RXByteCnt_A;
u8Byte RXByteCnt_B;
- u1Byte DoubleComfirm;
- u1Byte TrafficLoad;
+ u8 DoubleComfirm;
+ u8 TrafficLoad;
//SW Antenna Switch
u4Byte OFDM_Ant2_Cnt[ASSOCIATE_ENTRY_NUM];
u4Byte RSSI_Ant1_Sum[ASSOCIATE_ENTRY_NUM];
u4Byte RSSI_Ant2_Sum[ASSOCIATE_ENTRY_NUM];
- u1Byte TxAnt[ASSOCIATE_ENTRY_NUM];
- u1Byte TargetSTA;
- u1Byte antsel;
- u1Byte RxIdleAnt;
+ u8 TxAnt[ASSOCIATE_ENTRY_NUM];
+ u8 TargetSTA;
+ u8 antsel;
+ u8 RxIdleAnt;
#endif
typedef struct _ODM_RATE_ADAPTIVE
{
- u1Byte Type; // DM_Type_ByFW/DM_Type_ByDriver
- u1Byte HighRSSIThresh; // if RSSI > HighRSSIThresh => RATRState is DM_RATR_STA_HIGH
- u1Byte LowRSSIThresh; // if RSSI <= LowRSSIThresh => RATRState is DM_RATR_STA_LOW
- u1Byte RATRState; // Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW
+ u8 Type; // DM_Type_ByFW/DM_Type_ByDriver
+ u8 HighRSSIThresh; // if RSSI > HighRSSIThresh => RATRState is DM_RATR_STA_HIGH
+ u8 LowRSSIThresh; // if RSSI <= LowRSSIThresh => RATRState is DM_RATR_STA_LOW
+ u8 RATRState; // Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW
u4Byte LastRATR; // RATR Register Content
} ODM_RATE_ADAPTIVE, *PODM_RATE_ADAPTIVE;
typedef struct _ODM_Phy_Status_Info_
{
- u1Byte RxPWDBAll;
- u1Byte SignalQuality; // in 0-100 index.
- u1Byte RxMIMOSignalQuality[MAX_PATH_NUM_92CS]; //EVM
- u1Byte RxMIMOSignalStrength[MAX_PATH_NUM_92CS];// in 0~100 index
+ u8 RxPWDBAll;
+ u8 SignalQuality; // in 0-100 index.
+ u8 RxMIMOSignalQuality[MAX_PATH_NUM_92CS]; //EVM
+ u8 RxMIMOSignalStrength[MAX_PATH_NUM_92CS];// in 0~100 index
s1Byte RxPower; // in dBm Translate from PWdB
s1Byte RecvSignalPower;// Real power in dBm for this packet, no beautification and aggregation. Keep this raw info to be used for the other procedures.
- u1Byte BTRxRSSIPercentage;
- u1Byte SignalStrength; // in 0-100 index.
- u1Byte RxPwr[MAX_PATH_NUM_92CS];//per-path's pwdb
- u1Byte RxSNR[MAX_PATH_NUM_92CS];//per-path's SNR
+ u8 BTRxRSSIPercentage;
+ u8 SignalStrength; // in 0-100 index.
+ u8 RxPwr[MAX_PATH_NUM_92CS];//per-path's pwdb
+ u8 RxSNR[MAX_PATH_NUM_92CS];//per-path's SNR
}ODM_PHY_INFO_T,*PODM_PHY_INFO_T;
typedef struct _ODM_Per_Pkt_Info_
{
- u1Byte Rate;
- u1Byte StationID;
+ u8 Rate;
+ u8 StationID;
bool bPacketMatchBSSID;
bool bPacketToSelf;
bool bPacketBeacon;
typedef struct _ODM_Mac_Status_Info_
{
- u1Byte test;
+ u8 test;
}ODM_MAC_INFO;
typedef struct _ODM_STA_INFO{
// Driver Write
bool bUsed; // record the sta status link or not?
- //u1Byte WirelessMode; //
- u1Byte IOTPeer; // Enum value. HT_IOT_PEER_E
+ //u8 WirelessMode; //
+ u8 IOTPeer; // Enum value. HT_IOT_PEER_E
// ODM Write
//1 PHY_STATUS_INFO
- u1Byte RSSI_Path[4]; //
- u1Byte RSSI_Ave;
- u1Byte RXEVM[4];
- u1Byte RXSNR[4];
+ u8 RSSI_Path[4]; //
+ u8 RSSI_Ave;
+ u8 RXEVM[4];
+ u8 RXSNR[4];
// ODM Write
//1 TX_INFO (may changed by IC)
ODM_CMNINFO_RSSI_MIN,
ODM_CMNINFO_DBG_COMP, // u8Byte
ODM_CMNINFO_DBG_LEVEL, // u4Byte
- ODM_CMNINFO_RA_THRESHOLD_HIGH, // u1Byte
- ODM_CMNINFO_RA_THRESHOLD_LOW, // u1Byte
- ODM_CMNINFO_RF_ANTENNA_TYPE, // u1Byte
+ ODM_CMNINFO_RA_THRESHOLD_HIGH, // u8
+ ODM_CMNINFO_RA_THRESHOLD_LOW, // u8
+ ODM_CMNINFO_RF_ANTENNA_TYPE, // u8
ODM_CMNINFO_BT_DISABLED,
ODM_CMNINFO_BT_OPERATION,
ODM_CMNINFO_BT_DIG,
typedef struct _ODM_RA_Info_
{
- u1Byte RateID;
+ u8 RateID;
u4Byte RateMask;
u4Byte RAUseRate;
- u1Byte RateSGI;
- u1Byte RssiStaRA;
- u1Byte PreRssiStaRA;
- u1Byte SGIEnable;
- u1Byte DecisionRate;
- u1Byte PreRate;
- u1Byte HighestRate;
- u1Byte LowestRate;
+ u8 RateSGI;
+ u8 RssiStaRA;
+ u8 PreRssiStaRA;
+ u8 SGIEnable;
+ u8 DecisionRate;
+ u8 PreRate;
+ u8 HighestRate;
+ u8 LowestRate;
u4Byte NscUp;
u4Byte NscDown;
u2Byte RTY[5];
u4Byte TOTAL;
u2Byte DROP;
- u1Byte Active;
+ u8 Active;
u2Byte RptTime;
- u1Byte RAWaitingCounter;
- u1Byte RAPendingCounter;
+ u8 RAWaitingCounter;
+ u8 RAPendingCounter;
#if 1 //POWER_TRAINING_ACTIVE == 1 // For compile pass only~!
- u1Byte PTActive; // on or off
- u1Byte PTTryState; // 0 trying state, 1 for decision state
- u1Byte PTStage; // 0~6
- u1Byte PTStopCount; //Stop PT counter
- u1Byte PTPreRate; // if rate change do PT
- u1Byte PTPreRssi; // if RSSI change 5% do PT
- u1Byte PTModeSS; // decide whitch rate should do PT
- u1Byte RAstage; // StageRA, decide how many times RA will be done between PT
- u1Byte PTSmoothFactor;
+ u8 PTActive; // on or off
+ u8 PTTryState; // 0 trying state, 1 for decision state
+ u8 PTStage; // 0~6
+ u8 PTStopCount; //Stop PT counter
+ u8 PTPreRate; // if rate change do PT
+ u8 PTPreRssi; // if RSSI change 5% do PT
+ u8 PTModeSS; // decide whitch rate should do PT
+ u8 RAstage; // StageRA, decide how many times RA will be done between PT
+ u8 PTSmoothFactor;
#endif
} ODM_RA_INFO_T,*PODM_RA_INFO_T;
s4Byte RegEB4;
s4Byte RegEBC;
- //u1Byte bTXPowerTracking;
- u1Byte TXPowercount;
+ //u8 bTXPowerTracking;
+ u8 TXPowercount;
bool bTXPowerTrackingInit;
bool bTXPowerTracking;
- u1Byte TxPowerTrackControl; //for mp mode, turn off txpwrtracking as default
- u1Byte TM_Trigger;
- u1Byte InternalPA5G[2]; //pathA / pathB
-
- u1Byte ThermalMeter[2]; // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1
- u1Byte ThermalValue;
- u1Byte ThermalValue_LCK;
- u1Byte ThermalValue_IQK;
- u1Byte ThermalValue_DPK;
- u1Byte ThermalValue_AVG[AVG_THERMAL_NUM];
- u1Byte ThermalValue_AVG_index;
- u1Byte ThermalValue_RxGain;
- u1Byte ThermalValue_Crystal;
- u1Byte ThermalValue_DPKstore;
- u1Byte ThermalValue_DPKtrack;
+ u8 TxPowerTrackControl; //for mp mode, turn off txpwrtracking as default
+ u8 TM_Trigger;
+ u8 InternalPA5G[2]; //pathA / pathB
+
+ u8 ThermalMeter[2]; // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1
+ u8 ThermalValue;
+ u8 ThermalValue_LCK;
+ u8 ThermalValue_IQK;
+ u8 ThermalValue_DPK;
+ u8 ThermalValue_AVG[AVG_THERMAL_NUM];
+ u8 ThermalValue_AVG_index;
+ u8 ThermalValue_RxGain;
+ u8 ThermalValue_Crystal;
+ u8 ThermalValue_DPKstore;
+ u8 ThermalValue_DPKtrack;
bool TxPowerTrackingInProgress;
bool bDPKenable;
bool bReloadtxpowerindex;
- u1Byte bRfPiEnable;
+ u8 bRfPiEnable;
u4Byte TXPowerTrackingCallbackCnt; //cosa add for debug
- u1Byte bCCKinCH14;
- u1Byte CCK_index;
- u1Byte OFDM_index[2];
+ u8 bCCKinCH14;
+ u8 CCK_index;
+ u8 OFDM_index[2];
bool bDoneTxpower;
- u1Byte ThermalValue_HP[HP_THERMAL_NUM];
- u1Byte ThermalValue_HP_index;
+ u8 ThermalValue_HP[HP_THERMAL_NUM];
+ u8 ThermalValue_HP_index;
IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM];
- u1Byte Delta_IQK;
- u1Byte Delta_LCK;
+ u8 Delta_IQK;
+ u8 Delta_LCK;
//for IQK
u4Byte RegC04;
//for APK
u4Byte APKoutput[2][2]; //path A/B; output1_1a/output1_2a
- u1Byte bAPKdone;
- u1Byte bAPKThermalMeterIgnore;
- u1Byte bDPdone;
- u1Byte bDPPathAOK;
- u1Byte bDPPathBOK;
+ u8 bAPKdone;
+ u8 bAPKThermalMeterIgnore;
+ u8 bDPdone;
+ u8 bDPPathAOK;
+ u8 bDPPathBOK;
}ODM_RF_CAL_T,*PODM_RF_CAL_T;
//
// ODM Dynamic common info value definition
typedef struct _FAST_ANTENNA_TRAINNING_
{
- u1Byte Bssid[6];
- u1Byte antsel_rx_keep_0;
- u1Byte antsel_rx_keep_1;
- u1Byte antsel_rx_keep_2;
+ u8 Bssid[6];
+ u8 antsel_rx_keep_0;
+ u8 antsel_rx_keep_1;
+ u8 antsel_rx_keep_2;
u4Byte antSumRSSI[7];
u4Byte antRSSIcnt[7];
u4Byte antAveRSSI[7];
- u1Byte FAT_State;
+ u8 FAT_State;
u4Byte TrainIdx;
- u1Byte antsel_a[ODM_ASSOCIATE_ENTRY_NUM];
- u1Byte antsel_b[ODM_ASSOCIATE_ENTRY_NUM];
- u1Byte antsel_c[ODM_ASSOCIATE_ENTRY_NUM];
+ u8 antsel_a[ODM_ASSOCIATE_ENTRY_NUM];
+ u8 antsel_b[ODM_ASSOCIATE_ENTRY_NUM];
+ u8 antsel_c[ODM_ASSOCIATE_ENTRY_NUM];
u4Byte MainAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
u4Byte AuxAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
u4Byte MainAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
u4Byte AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
- u1Byte RxIdleAnt;
+ u8 RxIdleAnt;
bool bBecomeLinked;
}FAT_T,*pFAT_T;
//------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------//
bool bCckHighPower;
- u1Byte RFPathRxEnable; // ODM_CMNINFO_RFPATH_ENABLE
- u1Byte ControlChannel;
+ u8 RFPathRxEnable; // ODM_CMNINFO_RFPATH_ENABLE
+ u8 ControlChannel;
//------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------//
//--------REMOVED COMMON INFO----------//
- //u1Byte PseudoMacPhyMode;
+ //u8 PseudoMacPhyMode;
//bool *BTCoexist;
//bool PseudoBtCoexist;
- //u1Byte OPMode;
+ //u8 OPMode;
//bool bAPMode;
//bool bClientMode;
//bool bAdHocMode;
//
//-----------HOOK BEFORE REG INIT-----------//
// ODM Platform info AP/ADSL/CE/MP = 1/2/3/4
- u1Byte SupportPlatform;
+ u8 SupportPlatform;
// ODM Support Ability DIG/RATR/TX_PWR_TRACK/ ¡K¡K = 1/2/3/¡K
u4Byte SupportAbility;
// ODM PCIE/USB/SDIO/GSPI = 0/1/2/3
- u1Byte SupportInterface;
+ u8 SupportInterface;
// ODM composite or independent. Bit oriented/ 92C+92D+ .... or any other type = 1/2/3/...
u4Byte SupportICType;
// Cut Version TestChip/A-cut/B-cut... = 0/1/2/3/...
- u1Byte CutVersion;
+ u8 CutVersion;
// Fab Version TSMC/UMC = 0/1
- u1Byte FabVersion;
+ u8 FabVersion;
// RF Type 4T4R/3T3R/2T2R/1T2R/1T1R/...
- u1Byte RFType;
+ u8 RFType;
// Board Type Normal/HighPower/MiniCard/SLIM/Combo/... = 0/1/2/3/4/...
- u1Byte BoardType;
+ u8 BoardType;
// with external LNA NO/Yes = 0/1
- u1Byte ExtLNA;
+ u8 ExtLNA;
// with external PA NO/Yes = 0/1
- u1Byte ExtPA;
+ u8 ExtPA;
// with external TRSW NO/Yes = 0/1
- u1Byte ExtTRSW;
- u1Byte PatchID; //Customer ID
+ u8 ExtTRSW;
+ u8 PatchID; //Customer ID
bool bInHctTest;
bool bWIFITest;
bool bDualMacSmartConcurrent;
u4Byte BK_SupportAbility;
- u1Byte AntDivType;
+ u8 AntDivType;
//-----------HOOK BEFORE REG INIT-----------//
//
//
//--------- POINTER REFERENCE-----------//
- u1Byte u1Byte_temp;
+ u8 u8_temp;
bool bool_temp;
PADAPTER PADAPTER_temp;
// MAC PHY Mode SMSP/DMSP/DMDP = 0/1/2
- u1Byte *pMacPhyMode;
+ u8 *pMacPhyMode;
//TX Unicast byte count
u8Byte *pNumTxBytesUnicast;
//RX Unicast byte count
u8Byte *pNumRxBytesUnicast;
// Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3
- u1Byte *pWirelessMode; //ODM_WIRELESS_MODE_E
+ u8 *pWirelessMode; //ODM_WIRELESS_MODE_E
// Frequence band 2.4G/5G = 0/1
- u1Byte *pBandType;
+ u8 *pBandType;
// Secondary channel offset don't_care/below/above = 0/1/2
- u1Byte *pSecChOffset;
+ u8 *pSecChOffset;
// Security mode Open/WEP/AES/TKIP = 0/1/2/3
- u1Byte *pSecurity;
+ u8 *pSecurity;
// BW info 20M/40M/80M = 0/1/2
- u1Byte *pBandWidth;
+ u8 *pBandWidth;
// Central channel location Ch1/Ch2/....
- u1Byte *pChannel; //central channel number
+ u8 *pChannel; //central channel number
// Common info for 92D DMSP
bool *pbGetValueFromOtherMac;
bool *pbScanInProcess;
bool *pbPowerSaving;
// CCA Path 2-path/path-A/path-B = 0/1/2; using ODM_CCA_PATH_E.
- u1Byte *pOnePathCCA;
+ u8 *pOnePathCCA;
//pMgntInfo->AntennaTest
- u1Byte *pAntennaTest;
+ u8 *pAntennaTest;
bool *pbNet_closed;
//--------- POINTER REFERENCE-----------//
//
bool bWIFI_Direct;
bool bWIFI_Display;
bool bLinked;
- u1Byte RSSI_Min;
- u1Byte InterfaceIndex; // Add for 92D dual MAC: 0--Mac0 1--Mac1
+ u8 RSSI_Min;
+ u8 InterfaceIndex; // Add for 92D dual MAC: 0--Mac0 1--Mac1
bool bIsMPChip;
bool bOneEntryOnly;
// Common info for BTDM
bool bBtDisabled; // BT is disabled
bool bBtHsOperation; // BT HS mode is under progress
- u1Byte btHsDigVal; // use BT rssi to decide the DIG value
+ u8 btHsDigVal; // use BT rssi to decide the DIG value
bool bBtDisableEdcaTurbo; // Under some condition, don't enable the EDCA Turbo
bool bBtBusy; // BT is busy.
//------------CALL BY VALUE-------------//
//
//common
- //u1Byte DM_Type;
- //u1Byte PSD_Report_RXHP[80]; // Add By Gary
- //u1Byte PSD_func_flag; // Add By Gary
+ //u8 DM_Type;
+ //u8 PSD_Report_RXHP[80]; // Add By Gary
+ //u8 PSD_func_flag; // Add By Gary
//for DIG
- //u1Byte bDMInitialGainEnable;
- //u1Byte binitialized; // for dm_initial_gain_Multi_STA use.
+ //u8 bDMInitialGainEnable;
+ //u8 binitialized; // for dm_initial_gain_Multi_STA use.
//for Antenna diversity
//u8 AntDivCfg;// 0:OFF , 1:ON, 2:by efuse
//PSTA_INFO_T RSSI_target;
//PSD
bool bUserAssignLevel;
RT_TIMER PSDTimer;
- u1Byte RSSI_BT; //come from BT
+ u8 RSSI_BT; //come from BT
bool bPSDinProcess;
bool bDMInitialGainEnable;
//for rate adaptive, in fact, 88c/92c fw will handle this
- u1Byte bUseRAMask;
+ u8 bUseRAMask;
ODM_RATE_ADAPTIVE RateAdaptive;
//
// TX power tracking
//
- u1Byte BbSwingIdxOfdm;
- u1Byte BbSwingIdxOfdmCurrent;
- u1Byte BbSwingIdxOfdmBase;
+ u8 BbSwingIdxOfdm;
+ u8 BbSwingIdxOfdmCurrent;
+ u8 BbSwingIdxOfdmBase;
bool BbSwingFlagOfdm;
- u1Byte BbSwingIdxCck;
- u1Byte BbSwingIdxCckCurrent;
- u1Byte BbSwingIdxCckBase;
+ u8 BbSwingIdxCck;
+ u8 BbSwingIdxCckCurrent;
+ u8 BbSwingIdxCckBase;
bool BbSwingFlagCck;
//
// ODM system resource.
#define CCK_TABLE_SIZE 33
extern u4Byte OFDMSwingTable[OFDM_TABLE_SIZE_92D];
-extern u1Byte CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8];
-extern u1Byte CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8];
+extern u8 CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8];
+extern u8 CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8];
#define SWAW_STEP_PEAK 0
#define SWAW_STEP_DETERMINE 1
-void ODM_Write_DIG(PDM_ODM_T pDM_Odm, u1Byte CurrentIGI);
-void ODM_Write_CCK_CCA_Thres(PDM_ODM_T pDM_Odm, u1Byte CurCCK_CCAThres);
+void ODM_Write_DIG(PDM_ODM_T pDM_Odm, u8 CurrentIGI);
+void ODM_Write_CCK_CCA_Thres(PDM_ODM_T pDM_Odm, u8 CurCCK_CCAThres);
void
ODM_SetAntenna(
PDM_ODM_T pDM_Odm,
- u1Byte Antenna);
+ u8 Antenna);
#define dm_RF_Saving ODM_RF_Saving
void ODM_RF_Saving( PDM_ODM_T pDM_Odm,
- u1Byte bForceInNormal );
+ u8 bForceInNormal );
#define SwAntDivRestAfterLink ODM_SwAntDivRestAfterLink
void ODM_SwAntDivRestAfterLink( PDM_ODM_T pDM_Odm);
#define dm_SWAW_RSSI_Check ODM_SwAntDivChkPerPktRssi
void ODM_SwAntDivChkPerPktRssi(
PDM_ODM_T pDM_Odm,
- u1Byte StationID,
+ u8 StationID,
PODM_PHY_INFO_T pPhyInfo
);
GetPSDData(
PDM_ODM_T pDM_Odm,
unsigned int point,
- u1Byte initial_gain_psd);
+ u8 initial_gain_psd);
void
odm_DIGbyRSSI_LPS(
PDM_ODM_T pDM_Odm,
u4Byte macid,
u4Byte ra_mask,
- u1Byte rssi_level);
+ u8 rssi_level);
void ODM_DMInit(PDM_ODM_T pDM_Odm);
void
ODM_AntselStatistics_88C(
PDM_ODM_T pDM_Odm,
- u1Byte MacId,
+ u8 MacId,
u4Byte PWDBAll,
bool isCCKrate
);
bool
ODM_SingleDualAntennaDetection(
PDM_ODM_T pDM_Odm,
- u1Byte mode
+ u8 mode
);
void odm_dtc(PDM_ODM_T pDM_Odm);
typedef struct _Phy_Rx_AGC_Info
{
#ifdef __LITTLE_ENDIAN
- u1Byte gain:7,trsw:1;
+ u8 gain:7,trsw:1;
#else
- u1Byte trsw:1,gain:7;
+ u8 trsw:1,gain:7;
#endif
} PHY_RX_AGC_INFO_T,*pPHY_RX_AGC_INFO_T;
typedef struct _Phy_Status_Rpt_8192cd
{
PHY_RX_AGC_INFO_T path_agc[2];
- u1Byte ch_corr[2];
- u1Byte cck_sig_qual_ofdm_pwdb_all;
- u1Byte cck_agc_rpt_ofdm_cfosho_a;
- u1Byte cck_rpt_b_ofdm_cfosho_b;
- u1Byte rsvd_1;//ch_corr_msb;
- u1Byte noise_power_db_msb;
- u1Byte path_cfotail[2];
- u1Byte pcts_mask[2];
+ u8 ch_corr[2];
+ u8 cck_sig_qual_ofdm_pwdb_all;
+ u8 cck_agc_rpt_ofdm_cfosho_a;
+ u8 cck_rpt_b_ofdm_cfosho_b;
+ u8 rsvd_1;//ch_corr_msb;
+ u8 noise_power_db_msb;
+ u8 path_cfotail[2];
+ u8 pcts_mask[2];
s1Byte stream_rxevm[2];
- u1Byte path_rxsnr[2];
- u1Byte noise_power_db_lsb;
- u1Byte rsvd_2[3];
- u1Byte stream_csi[2];
- u1Byte stream_target_csi[2];
+ u8 path_rxsnr[2];
+ u8 noise_power_db_lsb;
+ u8 rsvd_2[3];
+ u8 stream_csi[2];
+ u8 stream_target_csi[2];
s1Byte sig_evm;
- u1Byte rsvd_3;
+ u8 rsvd_3;
#ifdef __LITTLE_ENDIAN
- u1Byte antsel_rx_keep_2:1; //ex_intf_flg:1;
- u1Byte sgi_en:1;
- u1Byte rxsc:2;
- u1Byte idle_long:1;
- u1Byte r_ant_train_en:1;
- u1Byte ant_sel_b:1;
- u1Byte ant_sel:1;
+ u8 antsel_rx_keep_2:1; //ex_intf_flg:1;
+ u8 sgi_en:1;
+ u8 rxsc:2;
+ u8 idle_long:1;
+ u8 r_ant_train_en:1;
+ u8 ant_sel_b:1;
+ u8 ant_sel:1;
#else // _BIG_ENDIAN_
- u1Byte ant_sel:1;
- u1Byte ant_sel_b:1;
- u1Byte r_ant_train_en:1;
- u1Byte idle_long:1;
- u1Byte rxsc:2;
- u1Byte sgi_en:1;
- u1Byte antsel_rx_keep_2:1; //ex_intf_flg:1;
+ u8 ant_sel:1;
+ u8 ant_sel_b:1;
+ u8 r_ant_train_en:1;
+ u8 idle_long:1;
+ u8 rxsc:2;
+ u8 sgi_en:1;
+ u8 antsel_rx_keep_2:1; //ex_intf_flg:1;
#endif
} PHY_STATUS_RPT_8192CD_T,*PPHY_STATUS_RPT_8192CD_T;
typedef struct _Phy_Status_Rpt_8195
{
PHY_RX_AGC_INFO_T path_agc[2];
- u1Byte ch_num[2];
- u1Byte cck_sig_qual_ofdm_pwdb_all;
- u1Byte cck_agc_rpt_ofdm_cfosho_a;
- u1Byte cck_bb_pwr_ofdm_cfosho_b;
- u1Byte cck_rx_path; //CCK_RX_PATH [3:0] (with regA07[3:0] definition)
- u1Byte rsvd_1;
- u1Byte path_cfotail[2];
- u1Byte pcts_mask[2];
+ u8 ch_num[2];
+ u8 cck_sig_qual_ofdm_pwdb_all;
+ u8 cck_agc_rpt_ofdm_cfosho_a;
+ u8 cck_bb_pwr_ofdm_cfosho_b;
+ u8 cck_rx_path; //CCK_RX_PATH [3:0] (with regA07[3:0] definition)
+ u8 rsvd_1;
+ u8 path_cfotail[2];
+ u8 pcts_mask[2];
s1Byte stream_rxevm[2];
- u1Byte path_rxsnr[2];
- u1Byte rsvd_2[2];
- u1Byte stream_snr[2];
- u1Byte stream_csi[2];
- u1Byte rsvd_3[2];
+ u8 path_rxsnr[2];
+ u8 rsvd_2[2];
+ u8 stream_snr[2];
+ u8 stream_csi[2];
+ u8 rsvd_3[2];
s1Byte sig_evm;
- u1Byte rsvd_4;
+ u8 rsvd_4;
#ifdef __LITTLE_ENDIAN
- u1Byte antidx_anta:3;
- u1Byte antidx_antb:3;
- u1Byte rsvd_5:2;
+ u8 antidx_anta:3;
+ u8 antidx_antb:3;
+ u8 rsvd_5:2;
#else // _BIG_ENDIAN_
- u1Byte rsvd_5:2;
- u1Byte antidx_antb:3;
- u1Byte antidx_anta:3;
+ u8 rsvd_5:2;
+ u8 antidx_antb:3;
+ u8 antidx_anta:3;
#endif
} PHY_STATUS_RPT_8195_T,*pPHY_STATUS_RPT_8195_T;
ODM_MacStatusQuery(
PDM_ODM_T pDM_Odm,
u8 * pMacStatus,
- u1Byte MacID,
+ u8 MacID,
bool bPacketMatchBSSID,
bool bPacketToSelf,
bool bPacketBeacon
odm_ConfigMAC_8723A(
PDM_ODM_T pDM_Odm,
u4Byte Addr,
- u1Byte Data
+ u8 Data
);
void
//
-u1Byte
+u8
ODM_Read1Byte(
PDM_ODM_T pDM_Odm,
u4Byte RegAddr
ODM_Write1Byte(
PDM_ODM_T pDM_Odm,
u4Byte RegAddr,
- u1Byte Data
+ u8 Data
);
void
void
ODM_FillH2CCmd(
PADAPTER Adapter,
- u1Byte ElementID,
+ u8 ElementID,
u4Byte CmdLen,
u8 * pCmdBuffer
);
#include <basic_types.h>
- #define u1Byte u8
#define u2Byte u16
#define pu2Byte u16*
OSDN Git Service
