src/i965_avc_encoder_common.h

   1 /*
   2  * Copyright @ 2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWAR OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *     Pengfei Qu <Pengfei.Qu@intel.com>
  26  *
  27  */
  28
  29 #ifndef _I965_AVC_ENCODER_COMMON_H
  30 #define _I965_AVC_ENCODER_COMMON_H
  31
  32 #include <stdio.h>
  33 #include <stdlib.h>
  34 #include <math.h>
  35 #include <stdint.h>
  36 #include <assert.h>
  37 #include "intel_driver.h"
  38 #include "gen9_avc_encoder.h"
  39
  40 // SubMbPartMask defined in CURBE for AVC ENC
  41 #define INTEL_AVC_DISABLE_4X4_SUB_MB_PARTITION    0x40
  42 #define INTEL_AVC_DISABLE_4X8_SUB_MB_PARTITION    0x20
  43 #define INTEL_AVC_DISABLE_8X4_SUB_MB_PARTITION    0x10
  44 #define INTEL_AVC_MAX_BWD_REF_NUM    2
  45 #define INTEL_AVC_MAX_FWD_REF_NUM    8
  46
  47 #define MAX_MFC_AVC_REFERENCE_SURFACES      16
  48 #define NUM_MFC_AVC_DMV_BUFFERS             34
  49 #define MAX_HCP_REFERENCE_SURFACES      8
  50 #define NUM_HCP_CURRENT_COLLOCATED_MV_TEMPORAL_BUFFERS             9
  51
  52 #define INTEL_AVC_IMAGE_STATE_CMD_SIZE    128
  53 #define INTEL_AVC_MIN_QP    1
  54 #define INTEL_AVC_MAX_QP    51
  55
  56 #define INTEL_AVC_WP_MODE_DEFAULT 0
  57 #define INTEL_AVC_WP_MODE_EXPLICIT 1
  58 #define INTEL_AVC_WP_MODE_IMPLICIT 2
  59
  60 struct avc_param {
  61
  62     // original width/height
  63     uint32_t frame_width_in_pixel;
  64     uint32_t frame_height_in_pixel;
  65     uint32_t frame_width_in_mbs;
  66     uint32_t frame_height_in_mbs;
  67     uint32_t frames_per_100s;
  68     uint32_t vbv_buffer_size_in_bit;
  69     uint32_t target_bit_rate;
  70 };
  71
  72 typedef enum
  73 {
  74     INTEL_AVC_BASE_PROFILE               = 66,
  75     INTEL_AVC_MAIN_PROFILE               = 77,
  76     INTEL_AVC_EXTENDED_PROFILE           = 88,
  77     INTEL_AVC_HIGH_PROFILE               = 100,
  78     INTEL_AVC_HIGH10_PROFILE             = 110
  79 } INTEL_AVC_PROFILE_IDC;
  80
  81 typedef enum
  82 {
  83     INTEL_AVC_LEVEL_1                    = 10,
  84     INTEL_AVC_LEVEL_11                   = 11,
  85     INTEL_AVC_LEVEL_12                   = 12,
  86     INTEL_AVC_LEVEL_13                   = 13,
  87     INTEL_AVC_LEVEL_2                    = 20,
  88     INTEL_AVC_LEVEL_21                   = 21,
  89     INTEL_AVC_LEVEL_22                   = 22,
  90     INTEL_AVC_LEVEL_3                    = 30,
  91     INTEL_AVC_LEVEL_31                   = 31,
  92     INTEL_AVC_LEVEL_32                   = 32,
  93     INTEL_AVC_LEVEL_4                    = 40,
  94     INTEL_AVC_LEVEL_41                   = 41,
  95     INTEL_AVC_LEVEL_42                   = 42,
  96     INTEL_AVC_LEVEL_5                    = 50,
  97     INTEL_AVC_LEVEL_51                   = 51,
  98     INTEL_AVC_LEVEL_52                   = 52
  99 } INTEL_AVC_LEVEL_IDC;
 100
 101 /*
 102 common structure and define
 103 */
 104 struct i965_avc_encoder_context {
 105
 106     VADriverContextP ctx;
 107
 108     /* VME resource */
 109     //mbbrc/brc:init/reset/update
 110     struct i965_gpe_resource res_brc_history_buffer;
 111     struct i965_gpe_resource res_brc_dist_data_surface;
 112     //brc:update
 113     struct i965_gpe_resource res_brc_pre_pak_statistics_output_buffer;
 114     struct i965_gpe_resource res_brc_image_state_read_buffer;
 115     struct i965_gpe_resource res_brc_image_state_write_buffer;
 116     struct i965_gpe_resource res_brc_mbenc_curbe_read_buffer;
 117     struct i965_gpe_resource res_brc_mbenc_curbe_write_buffer;
 118     struct i965_gpe_resource res_brc_const_data_buffer;
 119     //brc and mbbrc
 120     struct i965_gpe_resource res_mb_status_buffer;
 121     //mbbrc
 122     struct i965_gpe_resource res_mbbrc_mb_qp_data_surface;
 123     struct i965_gpe_resource res_mbbrc_roi_surface;
 124     struct i965_gpe_resource res_mbbrc_const_data_buffer;
 125
 126     //mbenc
 127     struct i965_gpe_resource res_mbenc_slice_map_surface;
 128     struct i965_gpe_resource res_mbenc_brc_buffer;//gen95
 129
 130     //scaling flatness check surface
 131     struct i965_gpe_resource res_flatness_check_surface;
 132     //me
 133     struct i965_gpe_resource s4x_memv_min_distortion_brc_buffer;
 134     struct i965_gpe_resource s4x_memv_distortion_buffer;
 135     struct i965_gpe_resource s4x_memv_data_buffer;
 136     struct i965_gpe_resource s16x_memv_data_buffer;
 137     struct i965_gpe_resource s32x_memv_data_buffer;
 138
 139
 140     struct i965_gpe_resource res_image_state_batch_buffer_2nd_level;
 141     struct intel_batchbuffer *pres_slice_batch_buffer_2nd_level;
 142     // mb code/data or indrirect mv data, define in private avc surface
 143
 144     //sfd
 145     struct i965_gpe_resource res_sfd_output_buffer;
 146     struct i965_gpe_resource res_sfd_cost_table_p_frame_buffer;
 147     struct i965_gpe_resource res_sfd_cost_table_b_frame_buffer;
 148
 149     //external mb qp data,application input
 150     struct i965_gpe_resource res_mb_qp_data_surface;
 151
 152     struct i965_gpe_resource res_mad_data_buffer;
 153
 154     //wp
 155     VASurfaceID wp_output_pic_select_surface_id[2];
 156     struct object_surface *wp_output_pic_select_surface_obj[2];
 157     struct i965_gpe_resource res_wp_output_pic_select_surface_list[2];
 158
 159     //mb disable skip
 160     struct i965_gpe_resource res_mb_disable_skip_map_surface;
 161
 162     /* PAK resource */
 163     //internal
 164     struct i965_gpe_resource res_intra_row_store_scratch_buffer;
 165     struct i965_gpe_resource res_deblocking_filter_row_store_scratch_buffer;
 166     struct i965_gpe_resource res_deblocking_filter_tile_col_buffer;
 167     struct i965_gpe_resource res_bsd_mpc_row_store_scratch_buffer;
 168     struct i965_gpe_resource res_mfc_indirect_bse_object;
 169     struct i965_gpe_resource res_pak_mb_status_buffer;
 170     struct i965_gpe_resource res_direct_mv_buffersr[NUM_MFC_AVC_DMV_BUFFERS];//INTERNAL: 0-31 as input,32 and 33 as output
 171
 172     //output
 173     struct i965_gpe_resource res_post_deblocking_output;
 174     struct i965_gpe_resource res_pre_deblocking_output;
 175
 176     //ref list
 177     struct i965_gpe_resource list_reference_res[MAX_MFC_AVC_REFERENCE_SURFACES];
 178
 179     // kernel context
 180     struct gen_avc_scaling_context  context_scaling;
 181     struct gen_avc_me_context  context_me;
 182     struct gen_avc_brc_context  context_brc;
 183     struct gen_avc_mbenc_context  context_mbenc;
 184     struct gen_avc_wp_context  context_wp;
 185     struct gen_avc_sfd_context  context_sfd;
 186
 187     struct encoder_status_buffer_internal status_buffer;
 188
 189 };
 190
 191 #define MAX_AVC_SLICE_NUM 256
 192 struct avc_enc_state {
 193
 194     VAEncSequenceParameterBufferH264 *seq_param;
 195     VAEncPictureParameterBufferH264  *pic_param;
 196     VAEncSliceParameterBufferH264    *slice_param[MAX_AVC_SLICE_NUM];
 197     VAEncMacroblockParameterBufferH264 *mb_param;
 198
 199     uint32_t mad_enable:1;
 200     //mb skip
 201     uint32_t mb_disable_skip_map_enable:1;
 202     //static frame detection
 203     uint32_t sfd_enable:1;
 204     uint32_t sfd_mb_enable:1;
 205     uint32_t adaptive_search_window_enable:1;
 206     //external mb qp
 207     uint32_t mb_qp_data_enable:1;
 208     //rolling intra refresh
 209     uint32_t intra_refresh_i_enable:1;
 210     uint32_t min_max_qp_enable:1;
 211     uint32_t skip_bias_adjustment_enable:1;
 212
 213     uint32_t non_ftq_skip_threshold_lut_input_enable:1;
 214     uint32_t ftq_skip_threshold_lut_input_enable:1;
 215     uint32_t ftq_override:1;
 216     uint32_t direct_bias_adjustment_enable:1;
 217     uint32_t global_motion_bias_adjustment_enable:1;
 218     uint32_t disable_sub_mb_partion:1;
 219     uint32_t arbitrary_num_mbs_in_slice:1;
 220     uint32_t adaptive_transform_decision_enable:1;
 221     uint32_t skip_check_disable:1;
 222     uint32_t tq_enable:1;
 223     uint32_t enable_avc_ildb:1;
 224     uint32_t suppress_recon_enable:1;
 225     uint32_t flatness_check_supported:1;
 226     uint32_t transform_8x8_mode_enable:1;
 227     uint32_t caf_supported:1;
 228     uint32_t mb_status_enable:1;
 229     uint32_t mbaff_flag:1;
 230     uint32_t enable_force_skip:1;
 231     uint32_t rc_panic_enable:1;
 232     uint32_t reserved0:7;
 233
 234     //generic begin
 235     uint32_t ref_pic_select_list_supported:1;
 236     uint32_t mb_brc_supported:1;
 237     uint32_t multi_pre_enable:1;
 238     uint32_t ftq_enable:1;
 239     uint32_t caf_enable:1;
 240     uint32_t caf_disable_hd:1;
 241     uint32_t skip_bias_adjustment_supported:1;
 242
 243     uint32_t adaptive_intra_scaling_enable:1;
 244     uint32_t old_mode_cost_enable:1;
 245     uint32_t multi_ref_qp_enable:1;
 246     uint32_t weighted_ref_l0_enable:1;
 247     uint32_t weighted_ref_l1_enable:1;
 248     uint32_t weighted_prediction_supported:1;
 249     uint32_t brc_split_enable:1;
 250     uint32_t slice_level_report_supported:1;
 251
 252     uint32_t fbr_bypass_enable:1;
 253     //mb status output in scaling kernel
 254     uint32_t field_scaling_output_interleaved:1;
 255     uint32_t mb_variance_output_enable:1;
 256     uint32_t mb_pixel_average_output_enable:1;
 257     uint32_t rolling_intra_refresh_enable:1;
 258     uint32_t mbenc_curbe_set_in_brc_update:1;
 259     //rounding
 260     uint32_t rounding_inter_enable:1;
 261     uint32_t adaptive_rounding_inter_enable:1;
 262
 263     uint32_t mbenc_i_frame_dist_in_use:1;
 264     uint32_t mb_status_supported:1;
 265     uint32_t mb_vproc_stats_enable:1;
 266     uint32_t flatness_check_enable:1;
 267     uint32_t block_based_skip_enable:1;
 268     uint32_t use_widi_mbenc_kernel:1;
 269     uint32_t kernel_trellis_enable:1;
 270     uint32_t generic_reserved:1;
 271     //generic end
 272
 273     //rounding
 274     uint32_t rounding_value;
 275     uint32_t rounding_inter_p;
 276     uint32_t rounding_inter_b;
 277     uint32_t rounding_inter_b_ref;
 278
 279     //min,max qp
 280     uint8_t  min_qp_i;
 281     uint8_t  max_qp_i;
 282     uint8_t  min_qp_p;
 283     uint8_t  max_qp_p;
 284     uint8_t  min_qp_b;
 285     uint8_t  max_qp_b;
 286
 287     uint8_t  non_ftq_skip_threshold_lut[52];
 288     uint8_t  ftq_skip_threshold_lut[52];
 289     uint32_t  lamda_value_lut[52][2];
 290
 291
 292     uint32_t intra_refresh_qp_threshold;
 293     uint32_t trellis_flag;
 294     uint32_t hme_mv_cost_scaling_factor;
 295     uint32_t slice_height;//default 1
 296     uint32_t slice_num;//default 1
 297     uint32_t dist_scale_factor_list0[32];
 298     uint32_t bi_weight;
 299     uint32_t brc_const_data_surface_width;
 300     uint32_t brc_const_data_surface_height;
 301
 302     uint32_t num_refs[2];
 303     uint32_t list_ref_idx[2][32];
 304     int32_t top_field_poc[NUM_MFC_AVC_DMV_BUFFERS];
 305
 306     uint32_t tq_rounding;
 307
 308     uint32_t zero_mv_threshold; //sfd
 309
 310     uint32_t slice_second_levle_batch_buffer_in_use;
 311     uint32_t slice_batch_offset[MAX_AVC_SLICE_NUM];
 312
 313     //gen95
 314     uint32_t decouple_mbenc_curbe_from_brc_enable :1;
 315     uint32_t extended_mv_cost_range_enable :1;
 316     uint32_t lambda_table_enable :1;
 317     uint32_t reserved_g95 :30;
 318     uint32_t mbenc_brc_buffer_size;
 319
 320 };
 321
 322 extern int i965_avc_get_max_mbps(int level_idc);
 323 extern int i965_avc_calculate_initial_qp(struct avc_param * param);
 324 extern unsigned int i965_avc_get_profile_level_max_frame(struct avc_param * param,int level_idc);
 325 extern int i965_avc_get_max_v_mv_r(int level_idc);
 326 extern int i965_avc_get_max_mv_len(int level_idc);
 327 extern int i965_avc_get_max_mv_per_2mb(int level_idc);
 328 extern unsigned short i965_avc_calc_skip_value(unsigned int enc_block_based_sip_en, unsigned int transform_8x8_flag, unsigned short skip_value);
 329 #endif // _I965_AVC_ENCODER_COMMON_H