2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * Zhou chang <chang.zhou@intel.com>
29 #ifndef _I965_ENCODER_H_
30 #define _I965_ENCODER_H_
34 #include <intel_bufmgr.h>
36 #include "i965_structs.h"
37 #include "i965_drv_video.h"
39 #define I965_BRC_NONE 0
40 #define I965_BRC_CBR 1
41 #define I965_BRC_VBR 2
42 #define I965_BRC_CQP 3
44 #define WIDTH_IN_MACROBLOCKS(width) (ALIGN(width, 16) >> 4)
45 #define HEIGHT_IN_MACROBLOCKS(height) (ALIGN(height, 16) >> 4)
46 #define MAX_TEMPORAL_LAYERS 4
64 struct intel_encoder_context
66 struct hw_context base;
68 VASurfaceID input_yuv_surface;
69 unsigned int rate_control_mode;
70 unsigned int quality_level;
71 unsigned int quality_range;
72 unsigned int num_frames_in_sequence;
73 unsigned int frame_width_in_pixel;
74 unsigned int frame_height_in_pixel;
75 unsigned int max_slice_or_seg_num;
78 unsigned int num_layers;
79 unsigned int size_frame_layer_ids;
80 unsigned int frame_layer_ids[32];
81 unsigned int curr_frame_layer_id;
85 unsigned short gop_size;
86 unsigned short num_iframes_in_gop;
87 unsigned short num_pframes_in_gop;
88 unsigned short num_bframes_in_gop;
89 unsigned int bits_per_second[MAX_TEMPORAL_LAYERS];
90 struct intel_fraction framerate[MAX_TEMPORAL_LAYERS];
91 unsigned int mb_rate_control[MAX_TEMPORAL_LAYERS];
92 unsigned int target_percentage[MAX_TEMPORAL_LAYERS];
93 unsigned int hrd_buffer_size;
94 unsigned int hrd_initial_buffer_fullness;
95 unsigned int window_size;
96 unsigned int initial_qp;
98 unsigned int need_reset;
100 unsigned int num_roi;
101 unsigned int roi_max_delta_qp;
102 unsigned int roi_min_delta_qp;
103 unsigned int roi_value_is_qp_delta;
104 struct intel_roi roi[I965_MAX_NUM_ROI_REGIONS];
109 void *enc_priv_state;
111 unsigned int is_tmp_id:1;
112 unsigned int low_power_mode:1;
113 unsigned int soft_batch_force:1;
114 unsigned int context_roi:1;
115 unsigned int is_new_sequence:1; /* Currently only valid for H.264, TODO for other codecs */
117 void (*vme_context_destroy)(void *vme_context);
118 VAStatus (*vme_pipeline)(VADriverContextP ctx,
120 struct encode_state *encode_state,
121 struct intel_encoder_context *encoder_context);
122 void (*mfc_context_destroy)(void *mfc_context);
123 VAStatus (*mfc_pipeline)(VADriverContextP ctx,
125 struct encode_state *encode_state,
126 struct intel_encoder_context *encoder_context);
127 void (*mfc_brc_prepare)(struct encode_state *encode_state,
128 struct intel_encoder_context *encoder_context);
130 VAStatus (*get_status)(VADriverContextP ctx,
131 struct intel_encoder_context *encoder_context,
132 struct i965_coded_buffer_segment *coded_buffer_segment);
135 extern struct hw_context *
136 gen75_enc_hw_context_init(VADriverContextP ctx, struct object_config *obj_config);
138 extern struct hw_context *
139 gen8_enc_hw_context_init(VADriverContextP ctx, struct object_config *obj_config);
141 extern struct hw_context *
142 gen9_enc_hw_context_init(VADriverContextP ctx, struct object_config *obj_config);
143 #endif /* _I965_ENCODER_H_ */