2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * Xiang Haihao <haihao.xiang@intel.com>
29 #ifndef __I965_POST_PROCESSING_H__
30 #define __I965_POST_PROCESSING_H__
32 #include "i965_vpp_avs.h"
35 #include <intel_bufmgr.h>
36 #include "i965_gpe_utils.h"
38 #define MAX_PP_SURFACES 48
40 struct i965_gpe_context;
44 PP_NV12_LOAD_SAVE_N12,
45 PP_NV12_LOAD_SAVE_PL3,
57 PP_RGBX_LOAD_SAVE_NV12,
58 PP_NV12_LOAD_SAVE_RGBX,
62 struct i965_post_processing_context;
64 struct pp_load_save_context {
71 struct pp_scaling_context {
72 int dest_x; /* in pixel */
73 int dest_y; /* in pixel */
76 float src_normalized_x;
77 float src_normalized_y;
80 struct pp_avs_context {
82 int dest_x; /* in pixel */
83 int dest_y; /* in pixel */
86 float src_normalized_x;
87 float src_normalized_y;
94 DNDI_FRAME_IN_CURRENT = 0,
95 DNDI_FRAME_IN_PREVIOUS,
98 DNDI_FRAME_OUT_CURRENT,
99 DNDI_FRAME_OUT_PREVIOUS,
100 DNDI_FRAME_STORE_COUNT
103 typedef struct dndi_frame_store {
104 struct object_surface *obj_surface;
105 VASurfaceID surface_id; /* always relative to the input surface */
106 unsigned int is_scratch_surface : 1;
109 struct pp_dndi_context {
112 DNDIFrameStore frame_store[DNDI_FRAME_STORE_COUNT];
114 /* Temporary flags live until the current picture is processed */
115 unsigned int is_di_enabled : 1;
116 unsigned int is_di_adv_enabled : 1;
117 unsigned int is_first_frame : 1;
118 unsigned int is_second_field : 1;
121 struct pp_dn_context {
127 struct i965_post_processing_context;
130 struct i965_kernel kernel;
133 VAStatus(*initialize)(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
134 const struct i965_surface *src_surface,
135 const VARectangle *src_rect,
136 struct i965_surface *dst_surface,
137 const VARectangle *dst_rect,
141 struct pp_static_parameter {
144 float procamp_constant_c0;
146 /* Load and Same r1.1 */
147 unsigned int source_packed_y_offset: 8;
148 unsigned int source_packed_u_offset: 8;
149 unsigned int source_packed_v_offset: 8;
150 unsigned int source_rgb_layout: 8; // 1 for |R|G|B|X| layout, 0 for |B|G|R|X| layout
153 /* Load and Save r1.2 */
155 unsigned int destination_packed_y_offset: 8;
156 unsigned int destination_packed_u_offset: 8;
157 unsigned int destination_packed_v_offset: 8;
158 unsigned int pad0: 8;
163 unsigned int pad0: 24;
164 unsigned int destination_rgb_layout: 8; // 1 for |R|G|B|X| layout, 0 for |B|G|R|X| layout
169 float procamp_constant_c1;
172 float procamp_constant_c2;
175 unsigned int statistics_surface_picth: 16; /* Devided by 2 */
176 unsigned int pad1: 16;
181 unsigned int pad0: 24;
182 unsigned int top_field_first: 8;
185 /* AVS/Scaling r1.6 */
186 float normalized_video_y_scaling_step;
190 float procamp_constant_c5;
195 float procamp_constant_c3;
201 float wg_csc_constant_c4;
204 float wg_csc_constant_c8;
207 float procamp_constant_c4;
216 float wg_csc_constant_c9;
221 float wg_csc_constant_c0;
224 float scaling_step_ratio;
227 float normalized_alpha_y_scaling;
230 float wg_csc_constant_c4;
233 float wg_csc_constant_c1;
236 int horizontal_origin_offset: 16;
237 int vertical_origin_offset: 16;
242 unsigned int color_pixel;
245 float wg_csc_constant_c2;
249 float wg_csc_constant_c3;
254 float wg_csc_constant_c6;
256 /* ALL r4.1 MBZ ???*/
263 unsigned int pad1: 15;
264 unsigned int nlas: 1;
265 unsigned int pad2: 16;
270 unsigned int motion_history_coefficient_m2: 8;
271 unsigned int motion_history_coefficient_m1: 8;
272 unsigned int pad0: 16;
277 float wg_csc_constant_c7;
280 float wg_csc_constant_c10;
283 float source_video_frame_normalized_horizontal_origin;
289 float wg_csc_constant_c11;
293 struct pp_inline_parameter {
296 int destination_block_horizontal_origin: 16;
297 int destination_block_vertical_origin: 16;
302 float source_surface_block_normalized_horizontal_origin;
306 unsigned int variance_surface_vertical_origin: 16;
307 unsigned int pad0: 16;
311 /* AVS/Scaling r5.2 */
312 float source_surface_block_normalized_vertical_origin;
315 float alpha_surface_block_normalized_horizontal_origin;
318 float alpha_surface_block_normalized_vertical_origin;
321 unsigned int alpha_mask_x: 16;
322 unsigned int alpha_mask_y: 8;
323 unsigned int block_count_x: 8;
326 /* we only support M*1 or 1*N block partitation now.
327 * -- it means asm code only need update this mask from grf6 for the last block
329 unsigned int block_horizontal_mask: 16;
330 unsigned int block_vertical_mask: 8;
331 unsigned int number_blocks: 8;
333 /* AVS/Scaling r5.7 */
334 float normalized_video_x_scaling_step;
339 float video_step_delta;
341 /* r6.1 */ // sizeof(int) == 4?
342 unsigned int block_horizontal_mask_right: 16;
343 unsigned int block_vertical_mask_bottom: 8;
344 unsigned int pad1: 8;
347 unsigned int block_horizontal_mask_middle: 16;
348 unsigned int pad2: 16;
351 unsigned int padx[5];
355 struct gen7_pp_static_parameter {
358 unsigned int padx[6];
360 unsigned int di_statistics_surface_pitch_div2: 16;
361 unsigned int di_statistics_surface_height_div4: 16;
363 unsigned int di_top_field_first: 8;
364 unsigned int pad0: 16;
365 unsigned int pointer_to_inline_parameter: 8; /* value: 7 */
370 /* Indicates whether the rgb is swapped for the src surface
371 * 0: RGBX(MSB. X-B-G-R). 1: BGRX(MSB: X-R-G-B)
373 unsigned int src_avs_rgb_swap: 1;
374 unsigned int pad3: 31;
377 unsigned int pad2: 16;
378 unsigned int save_avs_rgb_swap: 1; /* 0: RGB, 1: BGR */
379 unsigned int avs_wa_enable: 1; /* must enabled for GEN7 */
380 unsigned int ief_enable: 1;
381 unsigned int avs_wa_width: 13;
384 float avs_wa_one_div_256_width;
387 float avs_wa_five_div_256_width;
390 unsigned int padx[3];
393 unsigned int di_destination_packed_y_component_offset: 8;
394 unsigned int di_destination_packed_u_component_offset: 8;
395 unsigned int di_destination_packed_v_component_offset: 8;
396 unsigned int alpha: 8;
400 float sampler_load_horizontal_scaling_step_ratio;
401 unsigned int padx[7];
405 float sampler_load_vertical_scaling_step;
407 unsigned int di_hoffset_svf_from_dvf: 16;
408 unsigned int di_voffset_svf_from_dvf: 16;
409 unsigned int padx[5];
413 float sampler_load_vertical_frame_origin;
414 unsigned int padx[7];
418 float sampler_load_horizontal_frame_origin;
419 unsigned int padx[7];
444 unsigned int padx[4];
448 struct gen7_pp_inline_parameter {
451 unsigned int destination_block_horizontal_origin: 16;
452 unsigned int destination_block_vertical_origin: 16;
453 /* r9.1: 0xffffffff */
454 unsigned int constant_0;
460 float sampler_load_main_video_x_scaling_step;
463 /* r9.6: must be zero */
464 unsigned int avs_vertical_block_number;
466 unsigned int group_id_number;
470 unsigned int padx[8];
474 struct i965_post_processing_context {
476 struct pp_module pp_modules[NUM_PP_MODULES];
477 void *pp_static_parameter;
478 void *pp_inline_parameter;
482 } surface_state_binding_table;
490 int num_interface_descriptors;
501 } sampler_state_table;
506 unsigned int vfe_start;
507 unsigned int cs_start;
509 unsigned int num_vfe_entries;
510 unsigned int num_cs_entries;
512 unsigned int size_vfe_entry;
513 unsigned int size_cs_entry;
517 unsigned int gpgpu_mode : 1;
518 unsigned int pad0 : 7;
519 unsigned int max_num_threads : 16;
520 unsigned int num_urb_entries : 8;
521 unsigned int urb_entry_size : 16;
522 unsigned int curbe_allocation_size : 16;
525 struct intel_vebox_context *vebox_proc_ctx;
527 struct pp_load_save_context pp_load_save_context;
528 struct pp_scaling_context pp_scaling_context;
529 struct pp_avs_context pp_avs_context;
530 struct pp_dndi_context pp_dndi_context;
531 struct pp_dn_context pp_dn_context;
532 void *private_context; /* pointer to the current private context */
533 void *pipeline_param; /* pointer to the pipeline parameter */
535 * \ref Extra filter flags used as a fast path.
537 * This corresponds to vaPutSurface() flags, for direct rendering,
538 * or to VAProcPipelineParameterBuffer.filter_flags when the VPP
539 * interfaces are used. In the latter case, this is just a copy of
542 unsigned int filter_flags;
544 int (*pp_x_steps)(void *private_context);
545 int (*pp_y_steps)(void *private_context);
546 int (*pp_set_block_parameter)(struct i965_post_processing_context *pp_context, int x, int y);
548 struct intel_batchbuffer *batch;
550 unsigned int block_horizontal_mask_left: 16;
551 unsigned int block_horizontal_mask_right: 16;
552 unsigned int block_vertical_mask_bottom: 8;
557 unsigned int end_offset;
567 unsigned int end_offset;
570 unsigned int sampler_offset;
572 unsigned int idrt_offset;
574 unsigned int curbe_offset;
577 VAStatus(*intel_post_processing)(VADriverContextP ctx,
578 struct i965_post_processing_context *pp_context,
579 const struct i965_surface *src_surface,
580 const VARectangle *src_rect,
581 struct i965_surface *dst_surface,
582 const VARectangle *dst_rect,
584 void * filter_param);
585 void (*finalize)(VADriverContextP ctx,
586 struct i965_post_processing_context *pp_context);
589 struct i965_gpe_context scaling_10bit_context;
590 int scaling_context_initialized;
591 struct i965_gpe_context scaling_yuv420p8_context;
592 #define VPPGPE_8BIT_420 (1 << 0)
593 #define VPPGPE_8BIT_422 (1 << 1)
594 #define VPPGPE_8BIT_444 (1 << 2)
595 unsigned int scaling_8bit_initialized;
598 struct i965_proc_context {
599 struct hw_context base;
600 void *driver_context;
601 struct i965_post_processing_context pp_context;
605 i965_post_processing(
606 VADriverContextP ctx,
607 struct object_surface *obj_surface,
608 const VARectangle *src_rect,
609 const VARectangle *dst_rect,
610 unsigned int va_flags,
611 int *has_done_scaling,
612 VARectangle *calibrated_rect
616 i965_scaling_processing(
617 VADriverContextP ctx,
618 struct object_surface *src_surface_obj,
619 const VARectangle *src_rect,
620 struct object_surface *dst_surface_obj,
621 const VARectangle *dst_rect,
622 unsigned int va_flags
626 i965_image_processing(VADriverContextP ctx,
627 const struct i965_surface *src_surface,
628 const VARectangle *src_rect,
629 struct i965_surface *dst_surface,
630 const VARectangle *dst_rect);
633 i965_post_processing_terminate(VADriverContextP ctx);
635 i965_post_processing_init(VADriverContextP ctx);
639 i965_proc_picture(VADriverContextP ctx,
641 union codec_state *codec_state,
642 struct hw_context *hw_context);
644 #endif /* __I965_POST_PROCESSING_H__ */