2 * Copyright © 2018 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * Xiang Haihao <haihao.xiang@intel.com>
32 * g1-g3 static parameters (constant)
33 * g16-g24 payload for write message
35 define(`ORIG', `g0.4<2,2,1>UW')
36 define(`ORIGX', `g0.4<0,1,0>UW')
37 define(`ORIGY', `g0.6<0,1,0>UW')
39 define(`ALPHA', `g1.3<0,1,0>UB')
41 define(`R', `g1.2<0,1,0>UB')
43 define(`G', `g1.1<0,1,0>UB')
45 define(`B', `g1.0<0,1,0>UB')
47 define(`BGRX_BTI', `1')
50 mov(8) g16.0<1>UD g0.0<8,8,1>UD {align1};
53 shl(1) g16.0<1>UD ORIGX 6:w {align1};
54 shl(1) g16.4<1>UD ORIGY 4:w {align1};
57 mov(1) g16.8<1>UD 0x000f000fUD {align1};
59 mov(1) g17.3<1>UB ALPHA {align1};
60 mov(1) g17.2<1>UB B {align1};
61 mov(1) g17.1<1>UB G {align1};
62 mov(1) g17.0<1>UB R {align1};
63 mov(16) g17.0<1>UD g17.0<0,1,0>UD {align1 compr};
64 mov(16) g19.0<1>UD g17.0<0,1,0>UD {align1 compr};
65 mov(16) g21.0<1>UD g17.0<0,1,0>UD {align1 compr};
66 mov(16) g23.0<1>UD g17.0<0,1,0>UD {align1 compr};
68 * write(p0, p1, p2, p3)
69 * p0: binding table index
70 * p1: message control, default is 0,
71 * p2: message type, 10 is media_block_write
72 * p3: cache type, 12 is data cache data port 1
74 send(16) 16 acc0<1>UW null write(BGRX_BTI, 0, 10, 12) mlen 9 rlen 0 {align1};
76 add(1) g16.0<1>UD g16.0<0,1,0>UD 16:w {align1};
77 send(16) 16 acc0<1>UW null write(BGRX_BTI, 0, 10, 12) mlen 9 rlen 0 {align1};
79 add(1) g16.0<1>UD g16.0<0,1,0>UD 16:w {align1};
80 send(16) 16 acc0<1>UW null write(BGRX_BTI, 0, 10, 12) mlen 9 rlen 0 {align1};
82 add(1) g16.0<1>UD g16.0<0,1,0>UD 16:w {align1};
83 send(16) 16 acc0<1>UW null write(BGRX_BTI, 0, 10, 12) mlen 9 rlen 0 {align1};
86 mov(8) g112.0<1>UD g0.0<8,8,1>UD {align1};
87 send(16) 112 null<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT};