Change the sequence of reading MMIO registers

Signed-off-by: Haihao Xiang <haihao.xiang@intel.com>

diff --git a/src/i965_encoder_vp8.c b/src/i965_encoder_vp8.c
index 0d6a2c8..7f940f8 100644 (file)
--- a/src/i965_encoder_vp8.c
+++ b/src/i965_encoder_vp8.c
@@ -1367,12 +1367,6 @@ i965_encoder_vp8_read_pak_statistics(VADriverContextP ctx,
     mi_store_register_mem_param.mmio_offset = vp8_context->vdbox_mmio_base + VP8_MFC_BITSTREAM_BYTECOUNT_FRAME_REG_OFFSET;
     gpe->mi_store_register_mem(ctx, batch, &mi_store_register_mem_param);
 
-    if (ipass == 0) {
-        mi_store_register_mem_param.offset = sizeof(unsigned int) * 4;
-        mi_store_register_mem_param.mmio_offset = vp8_context->vdbox_mmio_base + VP8_MFX_BRC_CUMULATIVE_DQ_INDEX01_REG_OFFSET;
-        gpe->mi_store_register_mem(ctx, batch, &mi_store_register_mem_param);
-    }
-
     mi_store_register_mem_param.offset = sizeof(unsigned int) * 5;
     mi_store_register_mem_param.mmio_offset = vp8_context->vdbox_mmio_base + VP8_MFX_BRC_DQ_INDEX_REG_OFFSET;
     gpe->mi_store_register_mem(ctx, batch, &mi_store_register_mem_param);
@@ -1381,6 +1375,12 @@ i965_encoder_vp8_read_pak_statistics(VADriverContextP ctx,
     mi_store_register_mem_param.mmio_offset = vp8_context->vdbox_mmio_base + VP8_MFX_BRC_D_LOOP_FILTER_REG_OFFSET;
     gpe->mi_store_register_mem(ctx, batch, &mi_store_register_mem_param);
 
+    if (ipass == 0) {
+        mi_store_register_mem_param.offset = sizeof(unsigned int) * 4;
+        mi_store_register_mem_param.mmio_offset = vp8_context->vdbox_mmio_base + VP8_MFX_BRC_CUMULATIVE_DQ_INDEX01_REG_OFFSET;
+        gpe->mi_store_register_mem(ctx, batch, &mi_store_register_mem_param);
+    }
+
     mi_store_register_mem_param.offset = sizeof(unsigned int) * 9;
     mi_store_register_mem_param.mmio_offset = vp8_context->vdbox_mmio_base + VP8_MFX_BRC_CUMULATIVE_DQ_INDEX01_REG_OFFSET;
     gpe->mi_store_register_mem(ctx, batch, &mi_store_register_mem_param);