1 /**************************************************************************
2 * Copyright (c) 2007, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
19 * develop this driver.
21 **************************************************************************/
28 #if defined(__linux__) && !defined(__KERNEL__)
33 * Intel Poulsbo driver package version.
36 /* #define PSB_PACKAGE_VERSION "ED"__DATE__*/
37 #define PSB_PACKAGE_VERSION "5.0.1.0046"
39 #define DRM_PSB_SAREA_MAJOR 0
40 #define DRM_PSB_SAREA_MINOR 1
41 #define PSB_FIXED_SHIFT 16
44 * Public memory types.
47 #define DRM_PSB_MEM_MMU DRM_BO_MEM_PRIV1
48 #define DRM_PSB_FLAG_MEM_MMU DRM_BO_FLAG_MEM_PRIV1
49 #define DRM_PSB_MEM_PDS DRM_BO_MEM_PRIV2
50 #define DRM_PSB_FLAG_MEM_PDS DRM_BO_FLAG_MEM_PRIV2
51 #define DRM_PSB_MEM_APER DRM_BO_MEM_PRIV3
52 #define DRM_PSB_FLAG_MEM_APER DRM_BO_FLAG_MEM_PRIV3
53 #define DRM_PSB_MEM_RASTGEOM DRM_BO_MEM_PRIV4
54 #define DRM_PSB_FLAG_MEM_RASTGEOM DRM_BO_FLAG_MEM_PRIV4
55 #define PSB_MEM_RASTGEOM_START 0x30000000
57 typedef int32_t psb_fixed;
58 typedef uint32_t psb_ufixed;
60 static inline psb_fixed psb_int_to_fixed(int a)
62 return a * (1 << PSB_FIXED_SHIFT);
65 static inline psb_ufixed psb_unsigned_to_ufixed(unsigned int a)
67 return a << PSB_FIXED_SHIFT;
70 /*Status of the command sent to the gfx device.*/
77 struct drm_psb_scanout {
78 uint32_t buffer_id; /* DRM buffer object ID */
79 uint32_t rotation; /* Rotation as in RR_rotation definitions */
80 uint32_t stride; /* Buffer stride in bytes */
81 uint32_t depth; /* Buffer depth in bits (NOT) bpp */
82 uint32_t width; /* Buffer width in pixels */
83 uint32_t height; /* Buffer height in lines */
84 psb_fixed transform[3][3]; /* Buffer composite transform */
85 /* (scaling, rot, reflect) */
88 #define DRM_PSB_SAREA_OWNERS 16
89 #define DRM_PSB_SAREA_OWNER_2D 0
90 #define DRM_PSB_SAREA_OWNER_3D 1
92 #define DRM_PSB_SAREA_SCANOUTS 3
94 struct drm_psb_sarea {
95 /* Track changes of this data structure */
100 /* Last context to touch part of hw */
101 uint32_t ctx_owners[DRM_PSB_SAREA_OWNERS];
103 /* Definition of front- and rotated buffers */
104 uint32_t num_scanouts;
105 struct drm_psb_scanout scanouts[DRM_PSB_SAREA_SCANOUTS];
115 uint32_t msvdx_state;
116 uint32_t msvdx_context;
119 #define PSB_RELOC_MAGIC 0x67676767
120 #define PSB_RELOC_SHIFT_MASK 0x0000FFFF
121 #define PSB_RELOC_SHIFT_SHIFT 0
122 #define PSB_RELOC_ALSHIFT_MASK 0xFFFF0000
123 #define PSB_RELOC_ALSHIFT_SHIFT 16
125 #define PSB_RELOC_OP_OFFSET 0 /* Offset of the indicated
128 #define PSB_RELOC_OP_2D_OFFSET 1 /* Offset of the indicated
129 * buffer, relative to 2D
132 #define PSB_RELOC_OP_PDS_OFFSET 2 /* Offset of the indicated buffer,
133 * relative to PDS base address
135 #define PSB_RELOC_OP_STRIDE 3 /* Stride of the indicated
136 * buffer (for tiling)
138 #define PSB_RELOC_OP_USE_OFFSET 4 /* Offset of USE buffer
139 * relative to base reg
141 #define PSB_RELOC_OP_USE_REG 5 /* Base reg of USE buffer */
143 struct drm_psb_reloc {
145 uint32_t where; /* offset in destination buffer */
146 uint32_t buffer; /* Buffer reloc applies to */
147 uint32_t mask; /* Destination format: */
148 uint32_t shift; /* Destination format: */
149 uint32_t pre_add; /* Destination format: */
150 uint32_t background; /* Destination add */
151 uint32_t dst_buffer; /* Destination buffer. Index into buffer_list */
152 uint32_t arg0; /* Reloc-op dependant */
156 #define PSB_BO_FLAG_TA (1ULL << 48)
157 #define PSB_BO_FLAG_SCENE (1ULL << 49)
158 #define PSB_BO_FLAG_FEEDBACK (1ULL << 50)
159 #define PSB_BO_FLAG_USSE (1ULL << 51)
161 #define PSB_ENGINE_2D 0
162 #define PSB_ENGINE_VIDEO 1
163 #define PSB_ENGINE_RASTERIZER 2
164 #define PSB_ENGINE_TA 3
165 #define PSB_ENGINE_HPRAST 4
168 * For this fence class we have a couple of
172 #define _PSB_FENCE_EXE_SHIFT 0
173 #define _PSB_FENCE_TA_DONE_SHIFT 1
174 #define _PSB_FENCE_RASTER_DONE_SHIFT 2
175 #define _PSB_FENCE_SCENE_DONE_SHIFT 3
176 #define _PSB_FENCE_FEEDBACK_SHIFT 4
178 #define _PSB_ENGINE_TA_FENCE_TYPES 5
179 #define _PSB_FENCE_TYPE_TA_DONE (1 << _PSB_FENCE_TA_DONE_SHIFT)
180 #define _PSB_FENCE_TYPE_RASTER_DONE (1 << _PSB_FENCE_RASTER_DONE_SHIFT)
181 #define _PSB_FENCE_TYPE_SCENE_DONE (1 << _PSB_FENCE_SCENE_DONE_SHIFT)
182 #define _PSB_FENCE_TYPE_FEEDBACK (1 << _PSB_FENCE_FEEDBACK_SHIFT)
184 #define PSB_ENGINE_HPRAST 4
185 #define PSB_NUM_ENGINES 5
187 #define PSB_TA_FLAG_FIRSTPASS (1 << 0)
188 #define PSB_TA_FLAG_LASTPASS (1 << 1)
190 #define PSB_FEEDBACK_OP_VISTEST (1 << 0)
192 /* to eliminate video playback tearing */
195 #define PSB_VIDEO_BLIT 0x0001
196 #define PSB_DELAYED_2D_BLIT 0x0002
197 typedef struct video_info
201 uint32_t pFBBOHandle;
204 #endif /* PSB_DETEAR */
206 struct drm_psb_scene {
211 uint32_t num_buffers;
214 struct drm_psb_hw_info
221 typedef struct drm_psb_cmdbuf_arg {
222 uint64_t buffer_list; /* List of buffers to validate */
223 uint64_t clip_rects; /* See i915 counterpart */
229 uint32_t ta_handle; /* TA reg-value pairs */
237 uint32_t cmdbuf_handle; /* 2D Command buffer object or, */
238 uint32_t cmdbuf_offset; /* rasterizer reg-value pairs */
239 uint32_t cmdbuf_size;
241 uint32_t reloc_handle; /* Reloc buffer object */
242 uint32_t reloc_offset;
245 int32_t damage; /* Damage front buffer with cliprects */
246 /* Not implemented yet */
247 uint32_t fence_flags;
254 uint32_t feedback_ops;
255 uint32_t feedback_handle;
256 uint32_t feedback_offset;
257 uint32_t feedback_breakpoints;
258 uint32_t feedback_size;
261 video_info sVideoInfo;
263 } drm_psb_cmdbuf_arg_t;
265 struct drm_psb_xhw_init_arg {
267 uint32_t buffer_handle;
269 uint32_t tmpBOHandle;
276 * Feedback components:
280 * Vistest component. The number of these in the feedback buffer
281 * equals the number of vistest breakpoints + 1.
282 * This is currently the only feedback component.
285 struct drm_psb_vistest {
289 #define PSB_HW_COOKIE_SIZE 16
290 #define PSB_HW_FEEDBACK_SIZE 8
291 #define PSB_HW_OOM_CMD_SIZE 6
293 struct drm_psb_xhw_arg {
298 uint32_t cookie[PSB_HW_COOKIE_SIZE];
304 uint32_t clear_p_start;
305 uint32_t clear_num_pages;
314 uint32_t num_oom_cmds;
315 uint32_t oom_cmds[PSB_HW_OOM_CMD_SIZE];
328 uint32_t param_offset;
334 uint32_t feedback[PSB_HW_FEEDBACK_SIZE];
338 #define DRM_PSB_CMDBUF 0x00
339 #define DRM_PSB_XHW_INIT 0x01
340 #define DRM_PSB_XHW 0x02
341 #define DRM_PSB_SCENE_UNREF 0x03
342 /* Controlling the kernel modesetting buffers */
343 #define DRM_PSB_KMS_OFF 0x04
344 #define DRM_PSB_KMS_ON 0x05
345 #define DRM_PSB_HW_INFO 0x06
347 #define PSB_XHW_INIT 0x00
348 #define PSB_XHW_TAKEDOWN 0x01
350 #define PSB_XHW_FIRE_RASTER 0x00
351 #define PSB_XHW_SCENE_INFO 0x01
352 #define PSB_XHW_SCENE_BIND_FIRE 0x02
353 #define PSB_XHW_TA_MEM_INFO 0x03
354 #define PSB_XHW_RESET_DPM 0x04
355 #define PSB_XHW_OOM 0x05
356 #define PSB_XHW_TERMINATE 0x06
357 #define PSB_XHW_VISTEST 0x07
358 #define PSB_XHW_RESUME 0x08
359 #define PSB_XHW_TA_MEM_LOAD 0x09
360 #define PSB_XHW_CHECK_LOCKUP 0x0a
361 #define PSB_XHW_HOTPLUG 0x0b
363 #define PSB_SCENE_FLAG_DIRTY (1 << 0)
364 #define PSB_SCENE_FLAG_COMPLETE (1 << 1)
365 #define PSB_SCENE_FLAG_SETUP (1 << 2)
366 #define PSB_SCENE_FLAG_SETUP_ONLY (1 << 3)
367 #define PSB_SCENE_FLAG_CLEARED (1 << 4)
369 #define PSB_TA_MEM_FLAG_TA (1 << 0)
370 #define PSB_TA_MEM_FLAG_RASTER (1 << 1)
371 #define PSB_TA_MEM_FLAG_HOSTA (1 << 2)
372 #define PSB_TA_MEM_FLAG_HOSTD (1 << 3)
373 #define PSB_TA_MEM_FLAG_INIT (1 << 4)
374 #define PSB_TA_MEM_FLAG_NEW_PT_OFFSET (1 << 5)
376 /*Raster fire will deallocate memory */
377 #define PSB_FIRE_FLAG_RASTER_DEALLOC (1 << 0)
378 /*Isp reset needed due to change in ZLS format */
379 #define PSB_FIRE_FLAG_NEEDS_ISP_RESET (1 << 1)
380 /*These are set by Xpsb. */
381 #define PSB_FIRE_FLAG_XHW_MASK 0xff000000
382 /*The task has had at least one OOM and Xpsb will
383 send back messages on each fire. */
384 #define PSB_FIRE_FLAG_XHW_OOM (1 << 24)
386 #define PSB_SCENE_ENGINE_TA 0
387 #define PSB_SCENE_ENGINE_RASTER 1
388 #define PSB_SCENE_NUM_ENGINES 2
390 struct drm_psb_dev_info_arg {
391 uint32_t num_use_attribute_registers;
393 #define DRM_PSB_DEVINFO 0x01