arch/arm/boot/dts/exynos4x12.dtsi

   1 /*
   2  * Samsung's Exynos4x12 SoCs device tree source
   3  *
   4  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * Samsung's Exynos4x12 SoCs device nodes are listed in this file. Exynos4x12
   8  * based board files can include this file and provide values for board specfic
   9  * bindings.
  10  *
  11  * Note: This file does not include device nodes for all the controllers in
  12  * Exynos4x12 SoC. As device tree coverage for Exynos4x12 increases, additional
  13  * nodes can be added to this file.
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License version 2 as
  17  * published by the Free Software Foundation.
  18 */
  19
  20 #include "exynos4.dtsi"
  21 #include "exynos4x12-pinctrl.dtsi"
  22
  23 / {
  24         aliases {
  25                 pinctrl0 = &pinctrl_0;
  26                 pinctrl1 = &pinctrl_1;
  27                 pinctrl2 = &pinctrl_2;
  28                 pinctrl3 = &pinctrl_3;
  29                 fimc-lite0 = &fimc_lite_0;
  30                 fimc-lite1 = &fimc_lite_1;
  31                 mshc0 = &mshc_0;
  32         };
  33
  34         sysram@02020000 {
  35                 compatible = "mmio-sram";
  36                 reg = <0x02020000 0x40000>;
  37                 #address-cells = <1>;
  38                 #size-cells = <1>;
  39                 ranges = <0 0x02020000 0x40000>;
  40
  41                 smp-sysram@0 {
  42                         compatible = "samsung,exynos4210-sysram";
  43                         reg = <0x0 0x1000>;
  44                 };
  45
  46                 smp-sysram@2f000 {
  47                         compatible = "samsung,exynos4210-sysram-ns";
  48                         reg = <0x2f000 0x1000>;
  49                 };
  50         };
  51
  52         pd_isp: isp-power-domain@10023CA0 {
  53                 compatible = "samsung,exynos4210-pd";
  54                 reg = <0x10023CA0 0x20>;
  55         };
  56
  57         l2c: l2-cache-controller@10502000 {
  58                 compatible = "arm,pl310-cache";
  59                 reg = <0x10502000 0x1000>;
  60                 cache-unified;
  61                 cache-level = <2>;
  62                 arm,tag-latency = <2 2 1>;
  63                 arm,data-latency = <3 2 1>;
  64                 arm,double-linefill = <1>;
  65                 arm,double-linefill-incr = <0>;
  66                 arm,double-linefill-wrap = <1>;
  67                 arm,prefetch-drop = <1>;
  68                 arm,prefetch-offset = <7>;
  69         };
  70
  71         clock: clock-controller@10030000 {
  72                 compatible = "samsung,exynos4412-clock";
  73                 reg = <0x10030000 0x20000>;
  74                 #clock-cells = <1>;
  75         };
  76
  77         mct@10050000 {
  78                 compatible = "samsung,exynos4412-mct";
  79                 reg = <0x10050000 0x800>;
  80                 interrupt-parent = <&mct_map>;
  81                 interrupts = <0>, <1>, <2>, <3>, <4>;
  82                 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
  83                 clock-names = "fin_pll", "mct";
  84
  85                 mct_map: mct-map {
  86                         #interrupt-cells = <1>;
  87                         #address-cells = <0>;
  88                         #size-cells = <0>;
  89                         interrupt-map = <0 &gic 0 57 0>,
  90                                         <1 &combiner 12 5>,
  91                                         <2 &combiner 12 6>,
  92                                         <3 &combiner 12 7>,
  93                                         <4 &gic 1 12 0>;
  94                 };
  95         };
  96
  97         combiner: interrupt-controller@10440000 {
  98                 interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
  99                              <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
 100                              <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
 101                              <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
 102                              <0 107 0>, <0 108 0>, <0 48 0>, <0 42 0>;
 103         };
 104
 105         pinctrl_0: pinctrl@11400000 {
 106                 compatible = "samsung,exynos4x12-pinctrl";
 107                 reg = <0x11400000 0x1000>;
 108                 interrupts = <0 47 0>;
 109         };
 110
 111         pinctrl_1: pinctrl@11000000 {
 112                 compatible = "samsung,exynos4x12-pinctrl";
 113                 reg = <0x11000000 0x1000>;
 114                 interrupts = <0 46 0>;
 115
 116                 wakup_eint: wakeup-interrupt-controller {
 117                         compatible = "samsung,exynos4210-wakeup-eint";
 118                         interrupt-parent = <&gic>;
 119                         interrupts = <0 32 0>;
 120                 };
 121         };
 122
 123         adc: adc@126C0000 {
 124                 compatible = "samsung,exynos-adc-v1";
 125                 reg = <0x126C0000 0x100>;
 126                 interrupt-parent = <&combiner>;
 127                 interrupts = <10 3>;
 128                 clocks = <&clock CLK_TSADC>;
 129                 clock-names = "adc";
 130                 #io-channel-cells = <1>;
 131                 io-channel-ranges;
 132                 samsung,syscon-phandle = <&pmu_system_controller>;
 133                 status = "disabled";
 134         };
 135
 136         pinctrl_2: pinctrl@03860000 {
 137                 compatible = "samsung,exynos4x12-pinctrl";
 138                 reg = <0x03860000 0x1000>;
 139                 interrupt-parent = <&combiner>;
 140                 interrupts = <10 0>;
 141         };
 142
 143         pinctrl_3: pinctrl@106E0000 {
 144                 compatible = "samsung,exynos4x12-pinctrl";
 145                 reg = <0x106E0000 0x1000>;
 146                 interrupts = <0 72 0>;
 147         };
 148
 149         pmu_system_controller: system-controller@10020000 {
 150                 compatible = "samsung,exynos4212-pmu", "syscon";
 151                 clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
 152                                 "clkout4", "clkout8", "clkout9";
 153                 clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
 154                         <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
 155                         <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>,
 156                         <&clock CLK_XUSBXTI>;
 157                 #clock-cells = <1>;
 158         };
 159
 160         g2d@10800000 {
 161                 compatible = "samsung,exynos4212-g2d";
 162                 reg = <0x10800000 0x1000>;
 163                 interrupts = <0 89 0>;
 164                 clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
 165                 clock-names = "sclk_fimg2d", "fimg2d";
 166                 status = "disabled";
 167         };
 168
 169         camera {
 170                 clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
 171                          <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
 172                 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
 173
 174                 fimc_0: fimc@11800000 {
 175                         compatible = "samsung,exynos4212-fimc";
 176                         samsung,pix-limits = <4224 8192 1920 4224>;
 177                         samsung,mainscaler-ext;
 178                         samsung,isp-wb;
 179                         samsung,cam-if;
 180                 };
 181
 182                 fimc_1: fimc@11810000 {
 183                         compatible = "samsung,exynos4212-fimc";
 184                         samsung,pix-limits = <4224 8192 1920 4224>;
 185                         samsung,mainscaler-ext;
 186                         samsung,isp-wb;
 187                         samsung,cam-if;
 188                 };
 189
 190                 fimc_2: fimc@11820000 {
 191                         compatible = "samsung,exynos4212-fimc";
 192                         samsung,pix-limits = <4224 8192 1920 4224>;
 193                         samsung,mainscaler-ext;
 194                         samsung,isp-wb;
 195                         samsung,lcd-wb;
 196                         samsung,cam-if;
 197                 };
 198
 199                 fimc_3: fimc@11830000 {
 200                         compatible = "samsung,exynos4212-fimc";
 201                         samsung,pix-limits = <1920 8192 1366 1920>;
 202                         samsung,rotators = <0>;
 203                         samsung,mainscaler-ext;
 204                         samsung,isp-wb;
 205                         samsung,lcd-wb;
 206                 };
 207
 208                 fimc_lite_0: fimc-lite@12390000 {
 209                         compatible = "samsung,exynos4212-fimc-lite";
 210                         reg = <0x12390000 0x1000>;
 211                         interrupts = <0 105 0>;
 212                         samsung,power-domain = <&pd_isp>;
 213                         clocks = <&clock CLK_FIMC_LITE0>;
 214                         clock-names = "flite";
 215                         status = "disabled";
 216                 };
 217
 218                 fimc_lite_1: fimc-lite@123A0000 {
 219                         compatible = "samsung,exynos4212-fimc-lite";
 220                         reg = <0x123A0000 0x1000>;
 221                         interrupts = <0 106 0>;
 222                         samsung,power-domain = <&pd_isp>;
 223                         clocks = <&clock CLK_FIMC_LITE1>;
 224                         clock-names = "flite";
 225                         status = "disabled";
 226                 };
 227
 228                 fimc_is: fimc-is@12000000 {
 229                         compatible = "samsung,exynos4212-fimc-is", "simple-bus";
 230                         reg = <0x12000000 0x260000>;
 231                         interrupts = <0 90 0>, <0 95 0>;
 232                         samsung,power-domain = <&pd_isp>;
 233                         clocks = <&clock CLK_FIMC_LITE0>,
 234                                  <&clock CLK_FIMC_LITE1>, <&clock CLK_PPMUISPX>,
 235                                  <&clock CLK_PPMUISPMX>,
 236                                  <&clock CLK_MOUT_MPLL_USER_T>,
 237                                  <&clock CLK_FIMC_ISP>, <&clock CLK_FIMC_DRC>,
 238                                  <&clock CLK_FIMC_FD>, <&clock CLK_MCUISP>,
 239                                  <&clock CLK_DIV_ISP0>,<&clock CLK_DIV_ISP1>,
 240                                  <&clock CLK_DIV_MCUISP0>,
 241                                  <&clock CLK_DIV_MCUISP1>,
 242                                  <&clock CLK_SCLK_UART_ISP>,
 243                                  <&clock CLK_ACLK200>, <&clock CLK_DIV_ACLK200>,
 244                                  <&clock CLK_ACLK400_MCUISP>,
 245                                  <&clock CLK_DIV_ACLK400_MCUISP>;
 246                         clock-names = "lite0", "lite1", "ppmuispx",
 247                                       "ppmuispmx", "mpll", "isp",
 248                                       "drc", "fd", "mcuisp",
 249                                       "ispdiv0", "ispdiv1", "mcuispdiv0",
 250                                       "mcuispdiv1", "uart", "aclk200",
 251                                       "div_aclk200", "aclk400mcuisp",
 252                                       "div_aclk400mcuisp";
 253                         #address-cells = <1>;
 254                         #size-cells = <1>;
 255                         ranges;
 256                         status = "disabled";
 257
 258                         pmu {
 259                                 reg = <0x10020000 0x3000>;
 260                         };
 261
 262                         i2c1_isp: i2c-isp@12140000 {
 263                                 compatible = "samsung,exynos4212-i2c-isp";
 264                                 reg = <0x12140000 0x100>;
 265                                 clocks = <&clock CLK_I2C1_ISP>;
 266                                 clock-names = "i2c_isp";
 267                                 #address-cells = <1>;
 268                                 #size-cells = <0>;
 269                         };
 270                 };
 271         };
 272
 273         mshc_0: mmc@12550000 {
 274                 compatible = "samsung,exynos4412-dw-mshc";
 275                 reg = <0x12550000 0x1000>;
 276                 interrupts = <0 77 0>;
 277                 #address-cells = <1>;
 278                 #size-cells = <0>;
 279                 fifo-depth = <0x80>;
 280                 clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>;
 281                 clock-names = "biu", "ciu";
 282                 status = "disabled";
 283         };
 284
 285         exynos-usbphy@125B0000 {
 286                 compatible = "samsung,exynos4x12-usb2-phy";
 287                 samsung,sysreg-phandle = <&sys_reg>;
 288         };
 289
 290         tmu@100C0000 {
 291                 compatible = "samsung,exynos4412-tmu";
 292                 interrupt-parent = <&combiner>;
 293                 interrupts = <2 4>;
 294                 reg = <0x100C0000 0x100>;
 295                 clocks = <&clock 383>;
 296                 clock-names = "tmu_apbif";
 297                 status = "disabled";
 298         };
 299 };