3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
6 select ACPI_MCFG if ACPI
7 select ACPI_SPCR_TABLE if ACPI
8 select ARCH_CLOCKSOURCE_DATA
9 select ARCH_HAS_DEVMEM_IS_ALLOWED
10 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
11 select ARCH_HAS_ELF_RANDOMIZE
12 select ARCH_HAS_GCOV_PROFILE_ALL
13 select ARCH_HAS_GIGANTIC_PAGE
15 select ARCH_HAS_SG_CHAIN
16 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
17 select ARCH_USE_CMPXCHG_LOCKREF
18 select ARCH_SUPPORTS_ATOMIC_RMW
19 select ARCH_SUPPORTS_NUMA_BALANCING
20 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
21 select ARCH_WANT_FRAME_POINTERS
22 select ARCH_HAS_UBSAN_SANITIZE_ALL
26 select AUDIT_ARCH_COMPAT_GENERIC
27 select ARM_GIC_V2M if PCI
29 select ARM_GIC_V3_ITS if PCI
31 select BUILDTIME_EXTABLE_SORT
32 select CLONE_BACKWARDS
34 select CPU_PM if (SUSPEND || CPU_IDLE)
35 select DCACHE_WORD_ACCESS
38 select GENERIC_ALLOCATOR
39 select GENERIC_CLOCKEVENTS
40 select GENERIC_CLOCKEVENTS_BROADCAST
41 select GENERIC_CPU_AUTOPROBE
42 select GENERIC_EARLY_IOREMAP
43 select GENERIC_IDLE_POLL_SETUP
44 select GENERIC_IRQ_PROBE
45 select GENERIC_IRQ_SHOW
46 select GENERIC_IRQ_SHOW_LEVEL
47 select GENERIC_PCI_IOMAP
48 select GENERIC_SCHED_CLOCK
49 select GENERIC_SMP_IDLE_THREAD
50 select GENERIC_STRNCPY_FROM_USER
51 select GENERIC_STRNLEN_USER
52 select GENERIC_TIME_VSYSCALL
53 select HANDLE_DOMAIN_IRQ
54 select HARDIRQS_SW_RESEND
55 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
56 select HAVE_ARCH_AUDITSYSCALL
57 select HAVE_ARCH_BITREVERSE
58 select HAVE_ARCH_HARDENED_USERCOPY
59 select HAVE_ARCH_HUGE_VMAP
60 select HAVE_ARCH_JUMP_LABEL
61 select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
63 select HAVE_ARCH_MMAP_RND_BITS
64 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
65 select HAVE_ARCH_SECCOMP_FILTER
66 select HAVE_ARCH_TRACEHOOK
67 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
70 select HAVE_C_RECORDMCOUNT
71 select HAVE_CC_STACKPROTECTOR
72 select HAVE_CMPXCHG_DOUBLE
73 select HAVE_CMPXCHG_LOCAL
74 select HAVE_CONTEXT_TRACKING
75 select HAVE_DEBUG_BUGVERBOSE
76 select HAVE_DEBUG_KMEMLEAK
77 select HAVE_DMA_API_DEBUG
78 select HAVE_DMA_CONTIGUOUS
79 select HAVE_DYNAMIC_FTRACE
80 select HAVE_EFFICIENT_UNALIGNED_ACCESS
81 select HAVE_FTRACE_MCOUNT_RECORD
82 select HAVE_FUNCTION_TRACER
83 select HAVE_FUNCTION_GRAPH_TRACER
84 select HAVE_GCC_PLUGINS
85 select HAVE_GENERIC_DMA_COHERENT
86 select HAVE_HW_BREAKPOINT if PERF_EVENTS
87 select HAVE_IRQ_TIME_ACCOUNTING
89 select HAVE_MEMBLOCK_NODE_MAP if NUMA
90 select HAVE_PATA_PLATFORM
91 select HAVE_PERF_EVENTS
93 select HAVE_PERF_USER_STACK_DUMP
94 select HAVE_REGS_AND_STACK_ACCESS_API
95 select HAVE_RCU_TABLE_FREE
96 select HAVE_SYSCALL_TRACEPOINTS
98 select HAVE_KRETPROBES if HAVE_KPROBES
99 select IOMMU_DMA if IOMMU_SUPPORT
101 select IRQ_FORCED_THREADING
102 select MODULES_USE_ELF_RELA
105 select OF_EARLY_FLATTREE
106 select OF_RESERVED_MEM
107 select PCI_ECAM if ACPI
111 select SYSCTL_EXCEPTION_TRACE
113 ARM 64-bit (AArch64) Linux support.
118 config ARCH_PHYS_ADDR_T_64BIT
127 config ARM64_PAGE_SHIFT
129 default 16 if ARM64_64K_PAGES
130 default 14 if ARM64_16K_PAGES
133 config ARM64_CONT_SHIFT
135 default 5 if ARM64_64K_PAGES
136 default 7 if ARM64_16K_PAGES
139 config ARCH_MMAP_RND_BITS_MIN
140 default 14 if ARM64_64K_PAGES
141 default 16 if ARM64_16K_PAGES
144 # max bits determined by the following formula:
145 # VA_BITS - PAGE_SHIFT - 3
146 config ARCH_MMAP_RND_BITS_MAX
147 default 19 if ARM64_VA_BITS=36
148 default 24 if ARM64_VA_BITS=39
149 default 27 if ARM64_VA_BITS=42
150 default 30 if ARM64_VA_BITS=47
151 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
152 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
153 default 33 if ARM64_VA_BITS=48
154 default 14 if ARM64_64K_PAGES
155 default 16 if ARM64_16K_PAGES
158 config ARCH_MMAP_RND_COMPAT_BITS_MIN
159 default 7 if ARM64_64K_PAGES
160 default 9 if ARM64_16K_PAGES
163 config ARCH_MMAP_RND_COMPAT_BITS_MAX
169 config STACKTRACE_SUPPORT
172 config ILLEGAL_POINTER_VALUE
174 default 0xdead000000000000
176 config LOCKDEP_SUPPORT
179 config TRACE_IRQFLAGS_SUPPORT
182 config RWSEM_XCHGADD_ALGORITHM
189 config GENERIC_BUG_RELATIVE_POINTERS
191 depends on GENERIC_BUG
193 config GENERIC_HWEIGHT
199 config GENERIC_CALIBRATE_DELAY
205 config HAVE_GENERIC_RCU_GUP
208 config ARCH_DMA_ADDR_T_64BIT
211 config NEED_DMA_MAP_STATE
214 config NEED_SG_DMA_LENGTH
226 config KERNEL_MODE_NEON
229 config FIX_EARLYCON_MEM
232 config PGTABLE_LEVELS
234 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
235 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
236 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
237 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
238 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
239 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
241 source "init/Kconfig"
243 source "kernel/Kconfig.freezer"
245 source "arch/arm64/Kconfig.platforms"
252 This feature enables support for PCI bus system. If you say Y
253 here, the kernel will include drivers and infrastructure code
254 to support PCI bus devices.
259 config PCI_DOMAINS_GENERIC
265 source "drivers/pci/Kconfig"
269 menu "Kernel Features"
271 menu "ARM errata workarounds via the alternatives framework"
273 config ARM64_ERRATUM_826319
274 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
277 This option adds an alternative code sequence to work around ARM
278 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
279 AXI master interface and an L2 cache.
281 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
282 and is unable to accept a certain write via this interface, it will
283 not progress on read data presented on the read data channel and the
286 The workaround promotes data cache clean instructions to
287 data cache clean-and-invalidate.
288 Please note that this does not necessarily enable the workaround,
289 as it depends on the alternative framework, which will only patch
290 the kernel if an affected CPU is detected.
294 config ARM64_ERRATUM_827319
295 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
298 This option adds an alternative code sequence to work around ARM
299 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
300 master interface and an L2 cache.
302 Under certain conditions this erratum can cause a clean line eviction
303 to occur at the same time as another transaction to the same address
304 on the AMBA 5 CHI interface, which can cause data corruption if the
305 interconnect reorders the two transactions.
307 The workaround promotes data cache clean instructions to
308 data cache clean-and-invalidate.
309 Please note that this does not necessarily enable the workaround,
310 as it depends on the alternative framework, which will only patch
311 the kernel if an affected CPU is detected.
315 config ARM64_ERRATUM_824069
316 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
319 This option adds an alternative code sequence to work around ARM
320 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
321 to a coherent interconnect.
323 If a Cortex-A53 processor is executing a store or prefetch for
324 write instruction at the same time as a processor in another
325 cluster is executing a cache maintenance operation to the same
326 address, then this erratum might cause a clean cache line to be
327 incorrectly marked as dirty.
329 The workaround promotes data cache clean instructions to
330 data cache clean-and-invalidate.
331 Please note that this option does not necessarily enable the
332 workaround, as it depends on the alternative framework, which will
333 only patch the kernel if an affected CPU is detected.
337 config ARM64_ERRATUM_819472
338 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
341 This option adds an alternative code sequence to work around ARM
342 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
343 present when it is connected to a coherent interconnect.
345 If the processor is executing a load and store exclusive sequence at
346 the same time as a processor in another cluster is executing a cache
347 maintenance operation to the same address, then this erratum might
348 cause data corruption.
350 The workaround promotes data cache clean instructions to
351 data cache clean-and-invalidate.
352 Please note that this does not necessarily enable the workaround,
353 as it depends on the alternative framework, which will only patch
354 the kernel if an affected CPU is detected.
358 config ARM64_ERRATUM_832075
359 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
362 This option adds an alternative code sequence to work around ARM
363 erratum 832075 on Cortex-A57 parts up to r1p2.
365 Affected Cortex-A57 parts might deadlock when exclusive load/store
366 instructions to Write-Back memory are mixed with Device loads.
368 The workaround is to promote device loads to use Load-Acquire
370 Please note that this does not necessarily enable the workaround,
371 as it depends on the alternative framework, which will only patch
372 the kernel if an affected CPU is detected.
376 config ARM64_ERRATUM_834220
377 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
381 This option adds an alternative code sequence to work around ARM
382 erratum 834220 on Cortex-A57 parts up to r1p2.
384 Affected Cortex-A57 parts might report a Stage 2 translation
385 fault as the result of a Stage 1 fault for load crossing a
386 page boundary when there is a permission or device memory
387 alignment fault at Stage 1 and a translation fault at Stage 2.
389 The workaround is to verify that the Stage 1 translation
390 doesn't generate a fault before handling the Stage 2 fault.
391 Please note that this does not necessarily enable the workaround,
392 as it depends on the alternative framework, which will only patch
393 the kernel if an affected CPU is detected.
397 config ARM64_ERRATUM_845719
398 bool "Cortex-A53: 845719: a load might read incorrect data"
402 This option adds an alternative code sequence to work around ARM
403 erratum 845719 on Cortex-A53 parts up to r0p4.
405 When running a compat (AArch32) userspace on an affected Cortex-A53
406 part, a load at EL0 from a virtual address that matches the bottom 32
407 bits of the virtual address used by a recent load at (AArch64) EL1
408 might return incorrect data.
410 The workaround is to write the contextidr_el1 register on exception
411 return to a 32-bit task.
412 Please note that this does not necessarily enable the workaround,
413 as it depends on the alternative framework, which will only patch
414 the kernel if an affected CPU is detected.
418 config ARM64_ERRATUM_843419
419 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
421 select ARM64_MODULE_CMODEL_LARGE if MODULES
423 This option links the kernel with '--fix-cortex-a53-843419' and
424 builds modules using the large memory model in order to avoid the use
425 of the ADRP instruction, which can cause a subsequent memory access
426 to use an incorrect address on Cortex-A53 parts up to r0p4.
430 config CAVIUM_ERRATUM_22375
431 bool "Cavium erratum 22375, 24313"
434 Enable workaround for erratum 22375, 24313.
436 This implements two gicv3-its errata workarounds for ThunderX. Both
437 with small impact affecting only ITS table allocation.
439 erratum 22375: only alloc 8MB table size
440 erratum 24313: ignore memory access type
442 The fixes are in ITS initialization and basically ignore memory access
443 type and table size provided by the TYPER and BASER registers.
447 config CAVIUM_ERRATUM_23144
448 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
452 ITS SYNC command hang for cross node io and collections/cpu mapping.
456 config CAVIUM_ERRATUM_23154
457 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
460 The gicv3 of ThunderX requires a modified version for
461 reading the IAR status to ensure data synchronization
462 (access to icc_iar1_el1 is not sync'ed before and after).
466 config CAVIUM_ERRATUM_27456
467 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
470 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
471 instructions may cause the icache to become corrupted if it
472 contains data for a non-current ASID. The fix is to
473 invalidate the icache when changing the mm context.
477 config QCOM_QDF2400_ERRATUM_0065
478 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
481 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
482 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
483 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
492 default ARM64_4K_PAGES
494 Page size (translation granule) configuration.
496 config ARM64_4K_PAGES
499 This feature enables 4KB pages support.
501 config ARM64_16K_PAGES
504 The system will use 16KB pages support. AArch32 emulation
505 requires applications compiled with 16K (or a multiple of 16K)
508 config ARM64_64K_PAGES
511 This feature enables 64KB pages support (4KB by default)
512 allowing only two levels of page tables and faster TLB
513 look-up. AArch32 emulation requires applications compiled
514 with 64K aligned segments.
519 prompt "Virtual address space size"
520 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
521 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
522 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
524 Allows choosing one of multiple possible virtual address
525 space sizes. The level of translation table is determined by
526 a combination of page size and virtual address space size.
528 config ARM64_VA_BITS_36
529 bool "36-bit" if EXPERT
530 depends on ARM64_16K_PAGES
532 config ARM64_VA_BITS_39
534 depends on ARM64_4K_PAGES
536 config ARM64_VA_BITS_42
538 depends on ARM64_64K_PAGES
540 config ARM64_VA_BITS_47
542 depends on ARM64_16K_PAGES
544 config ARM64_VA_BITS_48
551 default 36 if ARM64_VA_BITS_36
552 default 39 if ARM64_VA_BITS_39
553 default 42 if ARM64_VA_BITS_42
554 default 47 if ARM64_VA_BITS_47
555 default 48 if ARM64_VA_BITS_48
557 config CPU_BIG_ENDIAN
558 bool "Build big-endian kernel"
560 Say Y if you plan on running a kernel in big-endian mode.
563 bool "Multi-core scheduler support"
565 Multi-core scheduler support improves the CPU scheduler's decision
566 making when dealing with multi-core CPU chips at a cost of slightly
567 increased overhead in some places. If unsure say N here.
570 bool "SMT scheduler support"
572 Improves the CPU scheduler's decision making when dealing with
573 MultiThreading at a cost of slightly increased overhead in some
574 places. If unsure say N here.
577 int "Maximum number of CPUs (2-4096)"
579 # These have to remain sorted largest to smallest
583 bool "Support for hot-pluggable CPUs"
584 select GENERIC_IRQ_MIGRATION
586 Say Y here to experiment with turning CPUs off and on. CPUs
587 can be controlled through /sys/devices/system/cpu.
589 # Common NUMA Features
591 bool "Numa Memory Allocation and Scheduler Support"
592 select ACPI_NUMA if ACPI
595 Enable NUMA (Non Uniform Memory Access) support.
597 The kernel will try to allocate memory used by a CPU on the
598 local memory of the CPU and add some more
599 NUMA awareness to the kernel.
602 int "Maximum NUMA Nodes (as a power of 2)"
605 depends on NEED_MULTIPLE_NODES
607 Specify the maximum number of NUMA Nodes available on the target
608 system. Increases memory reserved to accommodate various tables.
610 config USE_PERCPU_NUMA_NODE_ID
614 config HAVE_SETUP_PER_CPU_AREA
618 config NEED_PER_CPU_EMBED_FIRST_CHUNK
622 source kernel/Kconfig.preempt
623 source kernel/Kconfig.hz
625 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
628 config ARCH_HAS_HOLES_MEMORYMODEL
629 def_bool y if SPARSEMEM
631 config ARCH_SPARSEMEM_ENABLE
633 select SPARSEMEM_VMEMMAP_ENABLE
635 config ARCH_SPARSEMEM_DEFAULT
636 def_bool ARCH_SPARSEMEM_ENABLE
638 config ARCH_SELECT_MEMORY_MODEL
639 def_bool ARCH_SPARSEMEM_ENABLE
641 config HAVE_ARCH_PFN_VALID
642 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
644 config HW_PERF_EVENTS
648 config SYS_SUPPORTS_HUGETLBFS
651 config ARCH_WANT_HUGE_PMD_SHARE
652 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
654 config ARCH_HAS_CACHE_LINE_SIZE
660 bool "Enable seccomp to safely compute untrusted bytecode"
662 This kernel feature is useful for number crunching applications
663 that may need to compute untrusted bytecode during their
664 execution. By using pipes or other transports made available to
665 the process as file descriptors supporting the read/write
666 syscalls, it's possible to isolate those applications in
667 their own address space using seccomp. Once seccomp is
668 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
669 and the task is only allowed to execute a few safe syscalls
670 defined by each seccomp mode.
673 bool "Enable paravirtualization code"
675 This changes the kernel so it can modify itself when it is run
676 under a hypervisor, potentially improving performance significantly
677 over full virtualization.
679 config PARAVIRT_TIME_ACCOUNTING
680 bool "Paravirtual steal time accounting"
684 Select this option to enable fine granularity task steal time
685 accounting. Time spent executing other tasks in parallel with
686 the current vCPU is discounted from the vCPU power. To account for
687 that, there can be a small performance impact.
689 If in doubt, say N here.
692 depends on PM_SLEEP_SMP
694 bool "kexec system call"
696 kexec is a system call that implements the ability to shutdown your
697 current kernel, and to start another kernel. It is like a reboot
698 but it is independent of the system firmware. And like a reboot
699 you can start any kernel with it, not just Linux.
706 bool "Xen guest support on ARM64"
707 depends on ARM64 && OF
711 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
713 config FORCE_MAX_ZONEORDER
715 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
716 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
719 The kernel memory allocator divides physically contiguous memory
720 blocks into "zones", where each zone is a power of two number of
721 pages. This option selects the largest power of two that the kernel
722 keeps in the memory allocator. If you need to allocate very large
723 blocks of physically contiguous memory, then you may need to
726 This config option is actually maximum order plus one. For example,
727 a value of 11 means that the largest free memory block is 2^10 pages.
729 We make sure that we can allocate upto a HugePage size for each configuration.
731 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
733 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
734 4M allocations matching the default size used by generic code.
736 config UNMAP_KERNEL_AT_EL0
737 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
740 Speculation attacks against some high-performance processors can
741 be used to bypass MMU permission checks and leak kernel data to
742 userspace. This can be defended against by unmapping the kernel
743 when running in userspace, mapping it back in on exception entry
744 via a trampoline page in the vector table.
748 config HARDEN_BRANCH_PREDICTOR
749 bool "Harden the branch predictor against aliasing attacks" if EXPERT
752 Speculation attacks against some high-performance processors rely on
753 being able to manipulate the branch predictor for a victim context by
754 executing aliasing branches in the attacker context. Such attacks
755 can be partially mitigated against by clearing internal branch
756 predictor state and limiting the prediction logic in some situations.
758 This config option will take CPU-specific actions to harden the
759 branch predictor against aliasing attacks and may rely on specific
760 instruction sequences or control bits being set by the system
765 menuconfig ARMV8_DEPRECATED
766 bool "Emulate deprecated/obsolete ARMv8 instructions"
769 Legacy software support may require certain instructions
770 that have been deprecated or obsoleted in the architecture.
772 Enable this config to enable selective emulation of these
780 bool "Emulate SWP/SWPB instructions"
782 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
783 they are always undefined. Say Y here to enable software
784 emulation of these instructions for userspace using LDXR/STXR.
786 In some older versions of glibc [<=2.8] SWP is used during futex
787 trylock() operations with the assumption that the code will not
788 be preempted. This invalid assumption may be more likely to fail
789 with SWP emulation enabled, leading to deadlock of the user
792 NOTE: when accessing uncached shared regions, LDXR/STXR rely
793 on an external transaction monitoring block called a global
794 monitor to maintain update atomicity. If your system does not
795 implement a global monitor, this option can cause programs that
796 perform SWP operations to uncached memory to deadlock.
800 config CP15_BARRIER_EMULATION
801 bool "Emulate CP15 Barrier instructions"
803 The CP15 barrier instructions - CP15ISB, CP15DSB, and
804 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
805 strongly recommended to use the ISB, DSB, and DMB
806 instructions instead.
808 Say Y here to enable software emulation of these
809 instructions for AArch32 userspace code. When this option is
810 enabled, CP15 barrier usage is traced which can help
811 identify software that needs updating.
815 config SETEND_EMULATION
816 bool "Emulate SETEND instruction"
818 The SETEND instruction alters the data-endianness of the
819 AArch32 EL0, and is deprecated in ARMv8.
821 Say Y here to enable software emulation of the instruction
822 for AArch32 userspace code.
824 Note: All the cpus on the system must have mixed endian support at EL0
825 for this feature to be enabled. If a new CPU - which doesn't support mixed
826 endian - is hotplugged in after this feature has been enabled, there could
827 be unexpected results in the applications.
832 menu "ARMv8.1 architectural features"
834 config ARM64_HW_AFDBM
835 bool "Support for hardware updates of the Access and Dirty page flags"
838 The ARMv8.1 architecture extensions introduce support for
839 hardware updates of the access and dirty information in page
840 table entries. When enabled in TCR_EL1 (HA and HD bits) on
841 capable processors, accesses to pages with PTE_AF cleared will
842 set this bit instead of raising an access flag fault.
843 Similarly, writes to read-only pages with the DBM bit set will
844 clear the read-only bit (AP[2]) instead of raising a
847 Kernels built with this configuration option enabled continue
848 to work on pre-ARMv8.1 hardware and the performance impact is
849 minimal. If unsure, say Y.
852 bool "Enable support for Privileged Access Never (PAN)"
855 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
856 prevents the kernel or hypervisor from accessing user-space (EL0)
859 Choosing this option will cause any unprotected (not using
860 copy_to_user et al) memory access to fail with a permission fault.
862 The feature is detected at runtime, and will remain as a 'nop'
863 instruction if the cpu does not implement the feature.
865 config ARM64_LSE_ATOMICS
866 bool "Atomic instructions"
868 As part of the Large System Extensions, ARMv8.1 introduces new
869 atomic instructions that are designed specifically to scale in
872 Say Y here to make use of these instructions for the in-kernel
873 atomic routines. This incurs a small overhead on CPUs that do
874 not support these instructions and requires the kernel to be
875 built with binutils >= 2.25.
878 bool "Enable support for Virtualization Host Extensions (VHE)"
881 Virtualization Host Extensions (VHE) allow the kernel to run
882 directly at EL2 (instead of EL1) on processors that support
883 it. This leads to better performance for KVM, as they reduce
884 the cost of the world switch.
886 Selecting this option allows the VHE feature to be detected
887 at runtime, and does not affect processors that do not
888 implement this feature.
892 menu "ARMv8.2 architectural features"
895 bool "Enable support for User Access Override (UAO)"
898 User Access Override (UAO; part of the ARMv8.2 Extensions)
899 causes the 'unprivileged' variant of the load/store instructions to
900 be overriden to be privileged.
902 This option changes get_user() and friends to use the 'unprivileged'
903 variant of the load/store instructions. This ensures that user-space
904 really did have access to the supplied memory. When addr_limit is
905 set to kernel memory the UAO bit will be set, allowing privileged
906 access to kernel memory.
908 Choosing this option will cause copy_to_user() et al to use user-space
911 The feature is detected at runtime, the kernel will use the
912 regular load/store instructions if the cpu does not implement the
917 config ARM64_MODULE_CMODEL_LARGE
920 config ARM64_MODULE_PLTS
922 select ARM64_MODULE_CMODEL_LARGE
923 select HAVE_MOD_ARCH_SPECIFIC
928 This builds the kernel as a Position Independent Executable (PIE),
929 which retains all relocation metadata required to relocate the
930 kernel binary at runtime to a different virtual address than the
931 address it was linked at.
932 Since AArch64 uses the RELA relocation format, this requires a
933 relocation pass at runtime even if the kernel is loaded at the
934 same address it was linked at.
936 config RANDOMIZE_BASE
937 bool "Randomize the address of the kernel image"
938 select ARM64_MODULE_PLTS if MODULES
941 Randomizes the virtual address at which the kernel image is
942 loaded, as a security feature that deters exploit attempts
943 relying on knowledge of the location of kernel internals.
945 It is the bootloader's job to provide entropy, by passing a
946 random u64 value in /chosen/kaslr-seed at kernel entry.
948 When booting via the UEFI stub, it will invoke the firmware's
949 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
950 to the kernel proper. In addition, it will randomise the physical
951 location of the kernel Image as well.
955 config RANDOMIZE_MODULE_REGION_FULL
956 bool "Randomize the module region independently from the core kernel"
957 depends on RANDOMIZE_BASE && !DYNAMIC_FTRACE
960 Randomizes the location of the module region without considering the
961 location of the core kernel. This way, it is impossible for modules
962 to leak information about the location of core kernel data structures
963 but it does imply that function calls between modules and the core
964 kernel will need to be resolved via veneers in the module PLT.
966 When this option is not set, the module region will be randomized over
967 a limited range that contains the [_stext, _etext] interval of the
968 core kernel, so branch relocations are always in range.
974 config ARM64_ACPI_PARKING_PROTOCOL
975 bool "Enable support for the ARM64 ACPI parking protocol"
978 Enable support for the ARM64 ACPI parking protocol. If disabled
979 the kernel will not allow booting through the ARM64 ACPI parking
980 protocol even if the corresponding data is present in the ACPI
984 string "Default kernel command string"
987 Provide a set of default command-line options at build time by
988 entering them here. As a minimum, you should specify the the
989 root device (e.g. root=/dev/nfs).
992 bool "Always use the default kernel command string"
994 Always use the default kernel command string, even if the boot
995 loader passes other arguments to the kernel.
996 This is useful if you cannot or don't want to change the
997 command-line options your boot loader passes to the kernel.
1003 bool "UEFI runtime support"
1004 depends on OF && !CPU_BIG_ENDIAN
1007 select EFI_PARAMS_FROM_FDT
1008 select EFI_RUNTIME_WRAPPERS
1013 This option provides support for runtime services provided
1014 by UEFI firmware (such as non-volatile variables, realtime
1015 clock, and platform reset). A UEFI stub is also provided to
1016 allow the kernel to be booted as an EFI application. This
1017 is only useful on systems that have UEFI firmware.
1020 bool "Enable support for SMBIOS (DMI) tables"
1024 This enables SMBIOS/DMI feature for systems.
1026 This option is only useful on systems that have UEFI firmware.
1027 However, even with this option, the resultant kernel should
1028 continue to boot on existing non-UEFI platforms.
1032 menu "Userspace binary formats"
1034 source "fs/Kconfig.binfmt"
1037 bool "Kernel support for 32-bit EL0"
1038 depends on ARM64_4K_PAGES || EXPERT
1039 select COMPAT_BINFMT_ELF if BINFMT_ELF
1041 select OLD_SIGSUSPEND3
1042 select COMPAT_OLD_SIGACTION
1044 This option enables support for a 32-bit EL0 running under a 64-bit
1045 kernel at EL1. AArch32-specific components such as system calls,
1046 the user helper functions, VFP support and the ptrace interface are
1047 handled appropriately by the kernel.
1049 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1050 that you will only be able to execute AArch32 binaries that were compiled
1051 with page size aligned segments.
1053 If you want to execute 32-bit userspace applications, say Y.
1055 config SYSVIPC_COMPAT
1057 depends on COMPAT && SYSVIPC
1061 menu "Power management options"
1063 source "kernel/power/Kconfig"
1065 config ARCH_HIBERNATION_POSSIBLE
1069 config ARCH_HIBERNATION_HEADER
1071 depends on HIBERNATION
1073 config ARCH_SUSPEND_POSSIBLE
1078 menu "CPU Power Management"
1080 source "drivers/cpuidle/Kconfig"
1082 source "drivers/cpufreq/Kconfig"
1086 source "net/Kconfig"
1088 source "drivers/Kconfig"
1090 source "drivers/firmware/Kconfig"
1092 source "drivers/acpi/Kconfig"
1096 source "arch/arm64/kvm/Kconfig"
1098 source "arch/arm64/Kconfig.debug"
1100 source "security/Kconfig"
1102 source "crypto/Kconfig"
1104 source "arch/arm64/crypto/Kconfig"
1107 source "lib/Kconfig"