drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include <linux/sysrq.h>
  32 #include <linux/slab.h>
  33 #include <linux/circ_buf.h>
  34 #include <drm/drmP.h>
  35 #include <drm/i915_drm.h>
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include "intel_drv.h"
  39
  40 /**
  41  * DOC: interrupt handling
  42  *
  43  * These functions provide the basic support for enabling and disabling the
  44  * interrupt handling support. There's a lot more functionality in i915_irq.c
  45  * and related files, but that will be described in separate chapters.
  46  */
  47
  48 static const u32 hpd_ilk[HPD_NUM_PINS] = {
  49         [HPD_PORT_A] = DE_DP_A_HOTPLUG,
  50 };
  51
  52 static const u32 hpd_ivb[HPD_NUM_PINS] = {
  53         [HPD_PORT_A] = DE_DP_A_HOTPLUG_IVB,
  54 };
  55
  56 static const u32 hpd_bdw[HPD_NUM_PINS] = {
  57         [HPD_PORT_A] = GEN8_PORT_DP_A_HOTPLUG,
  58 };
  59
  60 static const u32 hpd_ibx[HPD_NUM_PINS] = {
  61         [HPD_CRT] = SDE_CRT_HOTPLUG,
  62         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
  63         [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
  64         [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
  65         [HPD_PORT_D] = SDE_PORTD_HOTPLUG
  66 };
  67
  68 static const u32 hpd_cpt[HPD_NUM_PINS] = {
  69         [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
  70         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
  71         [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
  72         [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
  73         [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
  74 };
  75
  76 static const u32 hpd_spt[HPD_NUM_PINS] = {
  77         [HPD_PORT_A] = SDE_PORTA_HOTPLUG_SPT,
  78         [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
  79         [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
  80         [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
  81         [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT
  82 };
  83
  84 static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
  85         [HPD_CRT] = CRT_HOTPLUG_INT_EN,
  86         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
  87         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
  88         [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
  89         [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
  90         [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
  91 };
  92
  93 static const u32 hpd_status_g4x[HPD_NUM_PINS] = {
  94         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  95         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
  96         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
  97         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  98         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  99         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
 100 };
 101
 102 static const u32 hpd_status_i915[HPD_NUM_PINS] = {
 103         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
 104         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
 105         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
 106         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
 107         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
 108         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
 109 };
 110
 111 /* BXT hpd list */
 112 static const u32 hpd_bxt[HPD_NUM_PINS] = {
 113         [HPD_PORT_A] = BXT_DE_PORT_HP_DDIA,
 114         [HPD_PORT_B] = BXT_DE_PORT_HP_DDIB,
 115         [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC
 116 };
 117
 118 /* IIR can theoretically queue up two events. Be paranoid. */
 119 #define GEN8_IRQ_RESET_NDX(type, which) do { \
 120         I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
 121         POSTING_READ(GEN8_##type##_IMR(which)); \
 122         I915_WRITE(GEN8_##type##_IER(which), 0); \
 123         I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
 124         POSTING_READ(GEN8_##type##_IIR(which)); \
 125         I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
 126         POSTING_READ(GEN8_##type##_IIR(which)); \
 127 } while (0)
 128
 129 #define GEN5_IRQ_RESET(type) do { \
 130         I915_WRITE(type##IMR, 0xffffffff); \
 131         POSTING_READ(type##IMR); \
 132         I915_WRITE(type##IER, 0); \
 133         I915_WRITE(type##IIR, 0xffffffff); \
 134         POSTING_READ(type##IIR); \
 135         I915_WRITE(type##IIR, 0xffffffff); \
 136         POSTING_READ(type##IIR); \
 137 } while (0)
 138
 139 /*
 140  * We should clear IMR at preinstall/uninstall, and just check at postinstall.
 141  */
 142 static void gen5_assert_iir_is_zero(struct drm_i915_private *dev_priv,
 143                                     i915_reg_t reg)
 144 {
 145         u32 val = I915_READ(reg);
 146
 147         if (val == 0)
 148                 return;
 149
 150         WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
 151              i915_mmio_reg_offset(reg), val);
 152         I915_WRITE(reg, 0xffffffff);
 153         POSTING_READ(reg);
 154         I915_WRITE(reg, 0xffffffff);
 155         POSTING_READ(reg);
 156 }
 157
 158 #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
 159         gen5_assert_iir_is_zero(dev_priv, GEN8_##type##_IIR(which)); \
 160         I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
 161         I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
 162         POSTING_READ(GEN8_##type##_IMR(which)); \
 163 } while (0)
 164
 165 #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
 166         gen5_assert_iir_is_zero(dev_priv, type##IIR); \
 167         I915_WRITE(type##IER, (ier_val)); \
 168         I915_WRITE(type##IMR, (imr_val)); \
 169         POSTING_READ(type##IMR); \
 170 } while (0)
 171
 172 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
 173 static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
 174
 175 /* For display hotplug interrupt */
 176 static inline void
 177 i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv,
 178                                      uint32_t mask,
 179                                      uint32_t bits)
 180 {
 181         uint32_t val;
 182
 183         lockdep_assert_held(&dev_priv->irq_lock);
 184         WARN_ON(bits & ~mask);
 185
 186         val = I915_READ(PORT_HOTPLUG_EN);
 187         val &= ~mask;
 188         val |= bits;
 189         I915_WRITE(PORT_HOTPLUG_EN, val);
 190 }
 191
 192 /**
 193  * i915_hotplug_interrupt_update - update hotplug interrupt enable
 194  * @dev_priv: driver private
 195  * @mask: bits to update
 196  * @bits: bits to enable
 197  * NOTE: the HPD enable bits are modified both inside and outside
 198  * of an interrupt context. To avoid that read-modify-write cycles
 199  * interfer, these bits are protected by a spinlock. Since this
 200  * function is usually not called from a context where the lock is
 201  * held already, this function acquires the lock itself. A non-locking
 202  * version is also available.
 203  */
 204 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
 205                                    uint32_t mask,
 206                                    uint32_t bits)
 207 {
 208         spin_lock_irq(&dev_priv->irq_lock);
 209         i915_hotplug_interrupt_update_locked(dev_priv, mask, bits);
 210         spin_unlock_irq(&dev_priv->irq_lock);
 211 }
 212
 213 /**
 214  * ilk_update_display_irq - update DEIMR
 215  * @dev_priv: driver private
 216  * @interrupt_mask: mask of interrupt bits to update
 217  * @enabled_irq_mask: mask of interrupt bits to enable
 218  */
 219 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
 220                             uint32_t interrupt_mask,
 221                             uint32_t enabled_irq_mask)
 222 {
 223         uint32_t new_val;
 224
 225         lockdep_assert_held(&dev_priv->irq_lock);
 226
 227         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 228
 229         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 230                 return;
 231
 232         new_val = dev_priv->irq_mask;
 233         new_val &= ~interrupt_mask;
 234         new_val |= (~enabled_irq_mask & interrupt_mask);
 235
 236         if (new_val != dev_priv->irq_mask) {
 237                 dev_priv->irq_mask = new_val;
 238                 I915_WRITE(DEIMR, dev_priv->irq_mask);
 239                 POSTING_READ(DEIMR);
 240         }
 241 }
 242
 243 /**
 244  * ilk_update_gt_irq - update GTIMR
 245  * @dev_priv: driver private
 246  * @interrupt_mask: mask of interrupt bits to update
 247  * @enabled_irq_mask: mask of interrupt bits to enable
 248  */
 249 static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
 250                               uint32_t interrupt_mask,
 251                               uint32_t enabled_irq_mask)
 252 {
 253         lockdep_assert_held(&dev_priv->irq_lock);
 254
 255         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 256
 257         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 258                 return;
 259
 260         dev_priv->gt_irq_mask &= ~interrupt_mask;
 261         dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
 262         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 263 }
 264
 265 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 266 {
 267         ilk_update_gt_irq(dev_priv, mask, mask);
 268         POSTING_READ_FW(GTIMR);
 269 }
 270
 271 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 272 {
 273         ilk_update_gt_irq(dev_priv, mask, 0);
 274 }
 275
 276 static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv)
 277 {
 278         return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
 279 }
 280
 281 static i915_reg_t gen6_pm_imr(struct drm_i915_private *dev_priv)
 282 {
 283         return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;
 284 }
 285
 286 static i915_reg_t gen6_pm_ier(struct drm_i915_private *dev_priv)
 287 {
 288         return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;
 289 }
 290
 291 /**
 292  * snb_update_pm_irq - update GEN6_PMIMR
 293  * @dev_priv: driver private
 294  * @interrupt_mask: mask of interrupt bits to update
 295  * @enabled_irq_mask: mask of interrupt bits to enable
 296  */
 297 static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
 298                               uint32_t interrupt_mask,
 299                               uint32_t enabled_irq_mask)
 300 {
 301         uint32_t new_val;
 302
 303         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 304
 305         lockdep_assert_held(&dev_priv->irq_lock);
 306
 307         new_val = dev_priv->pm_imr;
 308         new_val &= ~interrupt_mask;
 309         new_val |= (~enabled_irq_mask & interrupt_mask);
 310
 311         if (new_val != dev_priv->pm_imr) {
 312                 dev_priv->pm_imr = new_val;
 313                 I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_imr);
 314                 POSTING_READ(gen6_pm_imr(dev_priv));
 315         }
 316 }
 317
 318 void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask)
 319 {
 320         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 321                 return;
 322
 323         snb_update_pm_irq(dev_priv, mask, mask);
 324 }
 325
 326 static void __gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask)
 327 {
 328         snb_update_pm_irq(dev_priv, mask, 0);
 329 }
 330
 331 void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask)
 332 {
 333         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 334                 return;
 335
 336         __gen6_mask_pm_irq(dev_priv, mask);
 337 }
 338
 339 void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 reset_mask)
 340 {
 341         i915_reg_t reg = gen6_pm_iir(dev_priv);
 342
 343         lockdep_assert_held(&dev_priv->irq_lock);
 344
 345         I915_WRITE(reg, reset_mask);
 346         I915_WRITE(reg, reset_mask);
 347         POSTING_READ(reg);
 348 }
 349
 350 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, u32 enable_mask)
 351 {
 352         lockdep_assert_held(&dev_priv->irq_lock);
 353
 354         dev_priv->pm_ier |= enable_mask;
 355         I915_WRITE(gen6_pm_ier(dev_priv), dev_priv->pm_ier);
 356         gen6_unmask_pm_irq(dev_priv, enable_mask);
 357         /* unmask_pm_irq provides an implicit barrier (POSTING_READ) */
 358 }
 359
 360 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, u32 disable_mask)
 361 {
 362         lockdep_assert_held(&dev_priv->irq_lock);
 363
 364         dev_priv->pm_ier &= ~disable_mask;
 365         __gen6_mask_pm_irq(dev_priv, disable_mask);
 366         I915_WRITE(gen6_pm_ier(dev_priv), dev_priv->pm_ier);
 367         /* though a barrier is missing here, but don't really need a one */
 368 }
 369
 370 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv)
 371 {
 372         spin_lock_irq(&dev_priv->irq_lock);
 373         gen6_reset_pm_iir(dev_priv, dev_priv->pm_rps_events);
 374         dev_priv->rps.pm_iir = 0;
 375         spin_unlock_irq(&dev_priv->irq_lock);
 376 }
 377
 378 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv)
 379 {
 380         if (READ_ONCE(dev_priv->rps.interrupts_enabled))
 381                 return;
 382
 383         spin_lock_irq(&dev_priv->irq_lock);
 384         WARN_ON_ONCE(dev_priv->rps.pm_iir);
 385         WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
 386         dev_priv->rps.interrupts_enabled = true;
 387         gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
 388
 389         spin_unlock_irq(&dev_priv->irq_lock);
 390 }
 391
 392 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask)
 393 {
 394         return (mask & ~dev_priv->rps.pm_intr_keep);
 395 }
 396
 397 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
 398 {
 399         if (!READ_ONCE(dev_priv->rps.interrupts_enabled))
 400                 return;
 401
 402         spin_lock_irq(&dev_priv->irq_lock);
 403         dev_priv->rps.interrupts_enabled = false;
 404
 405         I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0u));
 406
 407         gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events);
 408
 409         spin_unlock_irq(&dev_priv->irq_lock);
 410         synchronize_irq(dev_priv->drm.irq);
 411
 412         /* Now that we will not be generating any more work, flush any
 413          * outsanding tasks. As we are called on the RPS idle path,
 414          * we will reset the GPU to minimum frequencies, so the current
 415          * state of the worker can be discarded.
 416          */
 417         cancel_work_sync(&dev_priv->rps.work);
 418         gen6_reset_rps_interrupts(dev_priv);
 419 }
 420
 421 void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv)
 422 {
 423         spin_lock_irq(&dev_priv->irq_lock);
 424         gen6_reset_pm_iir(dev_priv, dev_priv->pm_guc_events);
 425         spin_unlock_irq(&dev_priv->irq_lock);
 426 }
 427
 428 void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv)
 429 {
 430         spin_lock_irq(&dev_priv->irq_lock);
 431         if (!dev_priv->guc.interrupts_enabled) {
 432                 WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) &
 433                                        dev_priv->pm_guc_events);
 434                 dev_priv->guc.interrupts_enabled = true;
 435                 gen6_enable_pm_irq(dev_priv, dev_priv->pm_guc_events);
 436         }
 437         spin_unlock_irq(&dev_priv->irq_lock);
 438 }
 439
 440 void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv)
 441 {
 442         spin_lock_irq(&dev_priv->irq_lock);
 443         dev_priv->guc.interrupts_enabled = false;
 444
 445         gen6_disable_pm_irq(dev_priv, dev_priv->pm_guc_events);
 446
 447         spin_unlock_irq(&dev_priv->irq_lock);
 448         synchronize_irq(dev_priv->drm.irq);
 449
 450         gen9_reset_guc_interrupts(dev_priv);
 451 }
 452
 453 /**
 454  * bdw_update_port_irq - update DE port interrupt
 455  * @dev_priv: driver private
 456  * @interrupt_mask: mask of interrupt bits to update
 457  * @enabled_irq_mask: mask of interrupt bits to enable
 458  */
 459 static void bdw_update_port_irq(struct drm_i915_private *dev_priv,
 460                                 uint32_t interrupt_mask,
 461                                 uint32_t enabled_irq_mask)
 462 {
 463         uint32_t new_val;
 464         uint32_t old_val;
 465
 466         lockdep_assert_held(&dev_priv->irq_lock);
 467
 468         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 469
 470         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 471                 return;
 472
 473         old_val = I915_READ(GEN8_DE_PORT_IMR);
 474
 475         new_val = old_val;
 476         new_val &= ~interrupt_mask;
 477         new_val |= (~enabled_irq_mask & interrupt_mask);
 478
 479         if (new_val != old_val) {
 480                 I915_WRITE(GEN8_DE_PORT_IMR, new_val);
 481                 POSTING_READ(GEN8_DE_PORT_IMR);
 482         }
 483 }
 484
 485 /**
 486  * bdw_update_pipe_irq - update DE pipe interrupt
 487  * @dev_priv: driver private
 488  * @pipe: pipe whose interrupt to update
 489  * @interrupt_mask: mask of interrupt bits to update
 490  * @enabled_irq_mask: mask of interrupt bits to enable
 491  */
 492 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
 493                          enum pipe pipe,
 494                          uint32_t interrupt_mask,
 495                          uint32_t enabled_irq_mask)
 496 {
 497         uint32_t new_val;
 498
 499         lockdep_assert_held(&dev_priv->irq_lock);
 500
 501         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 502
 503         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 504                 return;
 505
 506         new_val = dev_priv->de_irq_mask[pipe];
 507         new_val &= ~interrupt_mask;
 508         new_val |= (~enabled_irq_mask & interrupt_mask);
 509
 510         if (new_val != dev_priv->de_irq_mask[pipe]) {
 511                 dev_priv->de_irq_mask[pipe] = new_val;
 512                 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
 513                 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
 514         }
 515 }
 516
 517 /**
 518  * ibx_display_interrupt_update - update SDEIMR
 519  * @dev_priv: driver private
 520  * @interrupt_mask: mask of interrupt bits to update
 521  * @enabled_irq_mask: mask of interrupt bits to enable
 522  */
 523 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
 524                                   uint32_t interrupt_mask,
 525                                   uint32_t enabled_irq_mask)
 526 {
 527         uint32_t sdeimr = I915_READ(SDEIMR);
 528         sdeimr &= ~interrupt_mask;
 529         sdeimr |= (~enabled_irq_mask & interrupt_mask);
 530
 531         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 532
 533         lockdep_assert_held(&dev_priv->irq_lock);
 534
 535         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 536                 return;
 537
 538         I915_WRITE(SDEIMR, sdeimr);
 539         POSTING_READ(SDEIMR);
 540 }
 541
 542 static void
 543 __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 544                        u32 enable_mask, u32 status_mask)
 545 {
 546         i915_reg_t reg = PIPESTAT(pipe);
 547         u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
 548
 549         lockdep_assert_held(&dev_priv->irq_lock);
 550         WARN_ON(!intel_irqs_enabled(dev_priv));
 551
 552         if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
 553                       status_mask & ~PIPESTAT_INT_STATUS_MASK,
 554                       "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
 555                       pipe_name(pipe), enable_mask, status_mask))
 556                 return;
 557
 558         if ((pipestat & enable_mask) == enable_mask)
 559                 return;
 560
 561         dev_priv->pipestat_irq_mask[pipe] |= status_mask;
 562
 563         /* Enable the interrupt, clear any pending status */
 564         pipestat |= enable_mask | status_mask;
 565         I915_WRITE(reg, pipestat);
 566         POSTING_READ(reg);
 567 }
 568
 569 static void
 570 __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 571                         u32 enable_mask, u32 status_mask)
 572 {
 573         i915_reg_t reg = PIPESTAT(pipe);
 574         u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
 575
 576         lockdep_assert_held(&dev_priv->irq_lock);
 577         WARN_ON(!intel_irqs_enabled(dev_priv));
 578
 579         if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
 580                       status_mask & ~PIPESTAT_INT_STATUS_MASK,
 581                       "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
 582                       pipe_name(pipe), enable_mask, status_mask))
 583                 return;
 584
 585         if ((pipestat & enable_mask) == 0)
 586                 return;
 587
 588         dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
 589
 590         pipestat &= ~enable_mask;
 591         I915_WRITE(reg, pipestat);
 592         POSTING_READ(reg);
 593 }
 594
 595 static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
 596 {
 597         u32 enable_mask = status_mask << 16;
 598
 599         /*
 600          * On pipe A we don't support the PSR interrupt yet,
 601          * on pipe B and C the same bit MBZ.
 602          */
 603         if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
 604                 return 0;
 605         /*
 606          * On pipe B and C we don't support the PSR interrupt yet, on pipe
 607          * A the same bit is for perf counters which we don't use either.
 608          */
 609         if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
 610                 return 0;
 611
 612         enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
 613                          SPRITE0_FLIP_DONE_INT_EN_VLV |
 614                          SPRITE1_FLIP_DONE_INT_EN_VLV);
 615         if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
 616                 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
 617         if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
 618                 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
 619
 620         return enable_mask;
 621 }
 622
 623 void
 624 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 625                      u32 status_mask)
 626 {
 627         u32 enable_mask;
 628
 629         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 630                 enable_mask = vlv_get_pipestat_enable_mask(&dev_priv->drm,
 631                                                            status_mask);
 632         else
 633                 enable_mask = status_mask << 16;
 634         __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
 635 }
 636
 637 void
 638 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 639                       u32 status_mask)
 640 {
 641         u32 enable_mask;
 642
 643         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 644                 enable_mask = vlv_get_pipestat_enable_mask(&dev_priv->drm,
 645                                                            status_mask);
 646         else
 647                 enable_mask = status_mask << 16;
 648         __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
 649 }
 650
 651 /**
 652  * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
 653  * @dev_priv: i915 device private
 654  */
 655 static void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv)
 656 {
 657         if (!dev_priv->opregion.asle || !IS_MOBILE(dev_priv))
 658                 return;
 659
 660         spin_lock_irq(&dev_priv->irq_lock);
 661
 662         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
 663         if (INTEL_GEN(dev_priv) >= 4)
 664                 i915_enable_pipestat(dev_priv, PIPE_A,
 665                                      PIPE_LEGACY_BLC_EVENT_STATUS);
 666
 667         spin_unlock_irq(&dev_priv->irq_lock);
 668 }
 669
 670 /*
 671  * This timing diagram depicts the video signal in and
 672  * around the vertical blanking period.
 673  *
 674  * Assumptions about the fictitious mode used in this example:
 675  *  vblank_start >= 3
 676  *  vsync_start = vblank_start + 1
 677  *  vsync_end = vblank_start + 2
 678  *  vtotal = vblank_start + 3
 679  *
 680  *           start of vblank:
 681  *           latch double buffered registers
 682  *           increment frame counter (ctg+)
 683  *           generate start of vblank interrupt (gen4+)
 684  *           |
 685  *           |          frame start:
 686  *           |          generate frame start interrupt (aka. vblank interrupt) (gmch)
 687  *           |          may be shifted forward 1-3 extra lines via PIPECONF
 688  *           |          |
 689  *           |          |  start of vsync:
 690  *           |          |  generate vsync interrupt
 691  *           |          |  |
 692  * ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx
 693  *       .   \hs/   .      \hs/          \hs/          \hs/   .      \hs/
 694  * ----va---> <-----------------vb--------------------> <--------va-------------
 695  *       |          |       <----vs----->                     |
 696  * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
 697  * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
 698  * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
 699  *       |          |                                         |
 700  *       last visible pixel                                   first visible pixel
 701  *                  |                                         increment frame counter (gen3/4)
 702  *                  pixel counter = vblank_start * htotal     pixel counter = 0 (gen3/4)
 703  *
 704  * x  = horizontal active
 705  * _  = horizontal blanking
 706  * hs = horizontal sync
 707  * va = vertical active
 708  * vb = vertical blanking
 709  * vs = vertical sync
 710  * vbs = vblank_start (number)
 711  *
 712  * Summary:
 713  * - most events happen at the start of horizontal sync
 714  * - frame start happens at the start of horizontal blank, 1-4 lines
 715  *   (depending on PIPECONF settings) after the start of vblank
 716  * - gen3/4 pixel and frame counter are synchronized with the start
 717  *   of horizontal active on the first line of vertical active
 718  */
 719
 720 /* Called from drm generic code, passed a 'crtc', which
 721  * we use as a pipe index
 722  */
 723 static u32 i915_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
 724 {
 725         struct drm_i915_private *dev_priv = to_i915(dev);
 726         i915_reg_t high_frame, low_frame;
 727         u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
 728         struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
 729                                                                 pipe);
 730         const struct drm_display_mode *mode = &intel_crtc->base.hwmode;
 731
 732         htotal = mode->crtc_htotal;
 733         hsync_start = mode->crtc_hsync_start;
 734         vbl_start = mode->crtc_vblank_start;
 735         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 736                 vbl_start = DIV_ROUND_UP(vbl_start, 2);
 737
 738         /* Convert to pixel count */
 739         vbl_start *= htotal;
 740
 741         /* Start of vblank event occurs at start of hsync */
 742         vbl_start -= htotal - hsync_start;
 743
 744         high_frame = PIPEFRAME(pipe);
 745         low_frame = PIPEFRAMEPIXEL(pipe);
 746
 747         /*
 748          * High & low register fields aren't synchronized, so make sure
 749          * we get a low value that's stable across two reads of the high
 750          * register.
 751          */
 752         do {
 753                 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 754                 low   = I915_READ(low_frame);
 755                 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 756         } while (high1 != high2);
 757
 758         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 759         pixel = low & PIPE_PIXEL_MASK;
 760         low >>= PIPE_FRAME_LOW_SHIFT;
 761
 762         /*
 763          * The frame counter increments at beginning of active.
 764          * Cook up a vblank counter by also checking the pixel
 765          * counter against vblank start.
 766          */
 767         return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
 768 }
 769
 770 static u32 g4x_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
 771 {
 772         struct drm_i915_private *dev_priv = to_i915(dev);
 773
 774         return I915_READ(PIPE_FRMCOUNT_G4X(pipe));
 775 }
 776
 777 /* I915_READ_FW, only for fast reads of display block, no need for forcewake etc. */
 778 static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
 779 {
 780         struct drm_device *dev = crtc->base.dev;
 781         struct drm_i915_private *dev_priv = to_i915(dev);
 782         const struct drm_display_mode *mode = &crtc->base.hwmode;
 783         enum pipe pipe = crtc->pipe;
 784         int position, vtotal;
 785
 786         if (!crtc->active)
 787                 return -1;
 788
 789         vtotal = mode->crtc_vtotal;
 790         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 791                 vtotal /= 2;
 792
 793         if (IS_GEN2(dev_priv))
 794                 position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
 795         else
 796                 position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
 797
 798         /*
 799          * On HSW, the DSL reg (0x70000) appears to return 0 if we
 800          * read it just before the start of vblank.  So try it again
 801          * so we don't accidentally end up spanning a vblank frame
 802          * increment, causing the pipe_update_end() code to squak at us.
 803          *
 804          * The nature of this problem means we can't simply check the ISR
 805          * bit and return the vblank start value; nor can we use the scanline
 806          * debug register in the transcoder as it appears to have the same
 807          * problem.  We may need to extend this to include other platforms,
 808          * but so far testing only shows the problem on HSW.
 809          */
 810         if (HAS_DDI(dev_priv) && !position) {
 811                 int i, temp;
 812
 813                 for (i = 0; i < 100; i++) {
 814                         udelay(1);
 815                         temp = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) &
 816                                 DSL_LINEMASK_GEN3;
 817                         if (temp != position) {
 818                                 position = temp;
 819                                 break;
 820                         }
 821                 }
 822         }
 823
 824         /*
 825          * See update_scanline_offset() for the details on the
 826          * scanline_offset adjustment.
 827          */
 828         return (position + crtc->scanline_offset) % vtotal;
 829 }
 830
 831 static int i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
 832                                     unsigned int flags, int *vpos, int *hpos,
 833                                     ktime_t *stime, ktime_t *etime,
 834                                     const struct drm_display_mode *mode)
 835 {
 836         struct drm_i915_private *dev_priv = to_i915(dev);
 837         struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
 838                                                                 pipe);
 839         int position;
 840         int vbl_start, vbl_end, hsync_start, htotal, vtotal;
 841         bool in_vbl = true;
 842         int ret = 0;
 843         unsigned long irqflags;
 844
 845         if (WARN_ON(!mode->crtc_clock)) {
 846                 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
 847                                  "pipe %c\n", pipe_name(pipe));
 848                 return 0;
 849         }
 850
 851         htotal = mode->crtc_htotal;
 852         hsync_start = mode->crtc_hsync_start;
 853         vtotal = mode->crtc_vtotal;
 854         vbl_start = mode->crtc_vblank_start;
 855         vbl_end = mode->crtc_vblank_end;
 856
 857         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
 858                 vbl_start = DIV_ROUND_UP(vbl_start, 2);
 859                 vbl_end /= 2;
 860                 vtotal /= 2;
 861         }
 862
 863         ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
 864
 865         /*
 866          * Lock uncore.lock, as we will do multiple timing critical raw
 867          * register reads, potentially with preemption disabled, so the
 868          * following code must not block on uncore.lock.
 869          */
 870         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 871
 872         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
 873
 874         /* Get optional system timestamp before query. */
 875         if (stime)
 876                 *stime = ktime_get();
 877
 878         if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
 879                 /* No obvious pixelcount register. Only query vertical
 880                  * scanout position from Display scan line register.
 881                  */
 882                 position = __intel_get_crtc_scanline(intel_crtc);
 883         } else {
 884                 /* Have access to pixelcount since start of frame.
 885                  * We can split this into vertical and horizontal
 886                  * scanout position.
 887                  */
 888                 position = (I915_READ_FW(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
 889
 890                 /* convert to pixel counts */
 891                 vbl_start *= htotal;
 892                 vbl_end *= htotal;
 893                 vtotal *= htotal;
 894
 895                 /*
 896                  * In interlaced modes, the pixel counter counts all pixels,
 897                  * so one field will have htotal more pixels. In order to avoid
 898                  * the reported position from jumping backwards when the pixel
 899                  * counter is beyond the length of the shorter field, just
 900                  * clamp the position the length of the shorter field. This
 901                  * matches how the scanline counter based position works since
 902                  * the scanline counter doesn't count the two half lines.
 903                  */
 904                 if (position >= vtotal)
 905                         position = vtotal - 1;
 906
 907                 /*
 908                  * Start of vblank interrupt is triggered at start of hsync,
 909                  * just prior to the first active line of vblank. However we
 910                  * consider lines to start at the leading edge of horizontal
 911                  * active. So, should we get here before we've crossed into
 912                  * the horizontal active of the first line in vblank, we would
 913                  * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
 914                  * always add htotal-hsync_start to the current pixel position.
 915                  */
 916                 position = (position + htotal - hsync_start) % vtotal;
 917         }
 918
 919         /* Get optional system timestamp after query. */
 920         if (etime)
 921                 *etime = ktime_get();
 922
 923         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
 924
 925         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 926
 927         in_vbl = position >= vbl_start && position < vbl_end;
 928
 929         /*
 930          * While in vblank, position will be negative
 931          * counting up towards 0 at vbl_end. And outside
 932          * vblank, position will be positive counting
 933          * up since vbl_end.
 934          */
 935         if (position >= vbl_start)
 936                 position -= vbl_end;
 937         else
 938                 position += vtotal - vbl_end;
 939
 940         if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
 941                 *vpos = position;
 942                 *hpos = 0;
 943         } else {
 944                 *vpos = position / htotal;
 945                 *hpos = position - (*vpos * htotal);
 946         }
 947
 948         /* In vblank? */
 949         if (in_vbl)
 950                 ret |= DRM_SCANOUTPOS_IN_VBLANK;
 951
 952         return ret;
 953 }
 954
 955 int intel_get_crtc_scanline(struct intel_crtc *crtc)
 956 {
 957         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 958         unsigned long irqflags;
 959         int position;
 960
 961         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 962         position = __intel_get_crtc_scanline(crtc);
 963         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 964
 965         return position;
 966 }
 967
 968 static int i915_get_vblank_timestamp(struct drm_device *dev, unsigned int pipe,
 969                               int *max_error,
 970                               struct timeval *vblank_time,
 971                               unsigned flags)
 972 {
 973         struct drm_i915_private *dev_priv = to_i915(dev);
 974         struct intel_crtc *crtc;
 975
 976         if (pipe >= INTEL_INFO(dev_priv)->num_pipes) {
 977                 DRM_ERROR("Invalid crtc %u\n", pipe);
 978                 return -EINVAL;
 979         }
 980
 981         /* Get drm_crtc to timestamp: */
 982         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
 983         if (crtc == NULL) {
 984                 DRM_ERROR("Invalid crtc %u\n", pipe);
 985                 return -EINVAL;
 986         }
 987
 988         if (!crtc->base.hwmode.crtc_clock) {
 989                 DRM_DEBUG_KMS("crtc %u is disabled\n", pipe);
 990                 return -EBUSY;
 991         }
 992
 993         /* Helper routine in DRM core does all the work: */
 994         return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
 995                                                      vblank_time, flags,
 996                                                      &crtc->base.hwmode);
 997 }
 998
 999 static void ironlake_rps_change_irq_handler(struct drm_i915_private *dev_priv)
1000 {
1001         u32 busy_up, busy_down, max_avg, min_avg;
1002         u8 new_delay;
1003
1004         spin_lock(&mchdev_lock);
1005
1006         I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
1007
1008         new_delay = dev_priv->ips.cur_delay;
1009
1010         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
1011         busy_up = I915_READ(RCPREVBSYTUPAVG);
1012         busy_down = I915_READ(RCPREVBSYTDNAVG);
1013         max_avg = I915_READ(RCBMAXAVG);
1014         min_avg = I915_READ(RCBMINAVG);
1015
1016         /* Handle RCS change request from hw */
1017         if (busy_up > max_avg) {
1018                 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
1019                         new_delay = dev_priv->ips.cur_delay - 1;
1020                 if (new_delay < dev_priv->ips.max_delay)
1021                         new_delay = dev_priv->ips.max_delay;
1022         } else if (busy_down < min_avg) {
1023                 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
1024                         new_delay = dev_priv->ips.cur_delay + 1;
1025                 if (new_delay > dev_priv->ips.min_delay)
1026                         new_delay = dev_priv->ips.min_delay;
1027         }
1028
1029         if (ironlake_set_drps(dev_priv, new_delay))
1030                 dev_priv->ips.cur_delay = new_delay;
1031
1032         spin_unlock(&mchdev_lock);
1033
1034         return;
1035 }
1036
1037 static void notify_ring(struct intel_engine_cs *engine)
1038 {
1039         struct drm_i915_gem_request *rq = NULL;
1040         struct intel_wait *wait;
1041
1042         atomic_inc(&engine->irq_count);
1043         set_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_posted);
1044
1045         spin_lock(&engine->breadcrumbs.irq_lock);
1046         wait = engine->breadcrumbs.irq_wait;
1047         if (wait) {
1048                 /* We use a callback from the dma-fence to submit
1049                  * requests after waiting on our own requests. To
1050                  * ensure minimum delay in queuing the next request to
1051                  * hardware, signal the fence now rather than wait for
1052                  * the signaler to be woken up. We still wake up the
1053                  * waiter in order to handle the irq-seqno coherency
1054                  * issues (we may receive the interrupt before the
1055                  * seqno is written, see __i915_request_irq_complete())
1056                  * and to handle coalescing of multiple seqno updates
1057                  * and many waiters.
1058                  */
1059                 if (i915_seqno_passed(intel_engine_get_seqno(engine),
1060                                       wait->seqno))
1061                         rq = i915_gem_request_get(wait->request);
1062
1063                 wake_up_process(wait->tsk);
1064         } else {
1065                 __intel_engine_disarm_breadcrumbs(engine);
1066         }
1067         spin_unlock(&engine->breadcrumbs.irq_lock);
1068
1069         if (rq) {
1070                 dma_fence_signal(&rq->fence);
1071                 i915_gem_request_put(rq);
1072         }
1073
1074         trace_intel_engine_notify(engine, wait);
1075 }
1076
1077 static void vlv_c0_read(struct drm_i915_private *dev_priv,
1078                         struct intel_rps_ei *ei)
1079 {
1080         ei->cz_clock = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP);
1081         ei->render_c0 = I915_READ(VLV_RENDER_C0_COUNT);
1082         ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT);
1083 }
1084
1085 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv)
1086 {
1087         memset(&dev_priv->rps.ei, 0, sizeof(dev_priv->rps.ei));
1088 }
1089
1090 static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
1091 {
1092         const struct intel_rps_ei *prev = &dev_priv->rps.ei;
1093         struct intel_rps_ei now;
1094         u32 events = 0;
1095
1096         if ((pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) == 0)
1097                 return 0;
1098
1099         vlv_c0_read(dev_priv, &now);
1100         if (now.cz_clock == 0)
1101                 return 0;
1102
1103         if (prev->cz_clock) {
1104                 u64 time, c0;
1105                 unsigned int mul;
1106
1107                 mul = VLV_CZ_CLOCK_TO_MILLI_SEC * 100; /* scale to threshold% */
1108                 if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH)
1109                         mul <<= 8;
1110
1111                 time = now.cz_clock - prev->cz_clock;
1112                 time *= dev_priv->czclk_freq;
1113
1114                 /* Workload can be split between render + media,
1115                  * e.g. SwapBuffers being blitted in X after being rendered in
1116                  * mesa. To account for this we need to combine both engines
1117                  * into our activity counter.
1118                  */
1119                 c0 = now.render_c0 - prev->render_c0;
1120                 c0 += now.media_c0 - prev->media_c0;
1121                 c0 *= mul;
1122
1123                 if (c0 > time * dev_priv->rps.up_threshold)
1124                         events = GEN6_PM_RP_UP_THRESHOLD;
1125                 else if (c0 < time * dev_priv->rps.down_threshold)
1126                         events = GEN6_PM_RP_DOWN_THRESHOLD;
1127         }
1128
1129         dev_priv->rps.ei = now;
1130         return events;
1131 }
1132
1133 static bool any_waiters(struct drm_i915_private *dev_priv)
1134 {
1135         struct intel_engine_cs *engine;
1136         enum intel_engine_id id;
1137
1138         for_each_engine(engine, dev_priv, id)
1139                 if (intel_engine_has_waiter(engine))
1140                         return true;
1141
1142         return false;
1143 }
1144
1145 static void gen6_pm_rps_work(struct work_struct *work)
1146 {
1147         struct drm_i915_private *dev_priv =
1148                 container_of(work, struct drm_i915_private, rps.work);
1149         bool client_boost;
1150         int new_delay, adj, min, max;
1151         u32 pm_iir;
1152
1153         spin_lock_irq(&dev_priv->irq_lock);
1154         /* Speed up work cancelation during disabling rps interrupts. */
1155         if (!dev_priv->rps.interrupts_enabled) {
1156                 spin_unlock_irq(&dev_priv->irq_lock);
1157                 return;
1158         }
1159
1160         pm_iir = dev_priv->rps.pm_iir;
1161         dev_priv->rps.pm_iir = 0;
1162         /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
1163         gen6_unmask_pm_irq(dev_priv, dev_priv->pm_rps_events);
1164         client_boost = dev_priv->rps.client_boost;
1165         dev_priv->rps.client_boost = false;
1166         spin_unlock_irq(&dev_priv->irq_lock);
1167
1168         /* Make sure we didn't queue anything we're not going to process. */
1169         WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
1170
1171         if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost)
1172                 return;
1173
1174         mutex_lock(&dev_priv->rps.hw_lock);
1175
1176         pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir);
1177
1178         adj = dev_priv->rps.last_adj;
1179         new_delay = dev_priv->rps.cur_freq;
1180         min = dev_priv->rps.min_freq_softlimit;
1181         max = dev_priv->rps.max_freq_softlimit;
1182         if (client_boost || any_waiters(dev_priv))
1183                 max = dev_priv->rps.max_freq;
1184         if (client_boost && new_delay < dev_priv->rps.boost_freq) {
1185                 new_delay = dev_priv->rps.boost_freq;
1186                 adj = 0;
1187         } else if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1188                 if (adj > 0)
1189                         adj *= 2;
1190                 else /* CHV needs even encode values */
1191                         adj = IS_CHERRYVIEW(dev_priv) ? 2 : 1;
1192
1193                 if (new_delay >= dev_priv->rps.max_freq_softlimit)
1194                         adj = 0;
1195         } else if (client_boost || any_waiters(dev_priv)) {
1196                 adj = 0;
1197         } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1198                 if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
1199                         new_delay = dev_priv->rps.efficient_freq;
1200                 else if (dev_priv->rps.cur_freq > dev_priv->rps.min_freq_softlimit)
1201                         new_delay = dev_priv->rps.min_freq_softlimit;
1202                 adj = 0;
1203         } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1204                 if (adj < 0)
1205                         adj *= 2;
1206                 else /* CHV needs even encode values */
1207                         adj = IS_CHERRYVIEW(dev_priv) ? -2 : -1;
1208
1209                 if (new_delay <= dev_priv->rps.min_freq_softlimit)
1210                         adj = 0;
1211         } else { /* unknown event */
1212                 adj = 0;
1213         }
1214
1215         dev_priv->rps.last_adj = adj;
1216
1217         /* sysfs frequency interfaces may have snuck in while servicing the
1218          * interrupt
1219          */
1220         new_delay += adj;
1221         new_delay = clamp_t(int, new_delay, min, max);
1222
1223         if (intel_set_rps(dev_priv, new_delay)) {
1224                 DRM_DEBUG_DRIVER("Failed to set new GPU frequency\n");
1225                 dev_priv->rps.last_adj = 0;
1226         }
1227
1228         mutex_unlock(&dev_priv->rps.hw_lock);
1229 }
1230
1231
1232 /**
1233  * ivybridge_parity_work - Workqueue called when a parity error interrupt
1234  * occurred.
1235  * @work: workqueue struct
1236  *
1237  * Doesn't actually do anything except notify userspace. As a consequence of
1238  * this event, userspace should try to remap the bad rows since statistically
1239  * it is likely the same row is more likely to go bad again.
1240  */
1241 static void ivybridge_parity_work(struct work_struct *work)
1242 {
1243         struct drm_i915_private *dev_priv =
1244                 container_of(work, struct drm_i915_private, l3_parity.error_work);
1245         u32 error_status, row, bank, subbank;
1246         char *parity_event[6];
1247         uint32_t misccpctl;
1248         uint8_t slice = 0;
1249
1250         /* We must turn off DOP level clock gating to access the L3 registers.
1251          * In order to prevent a get/put style interface, acquire struct mutex
1252          * any time we access those registers.
1253          */
1254         mutex_lock(&dev_priv->drm.struct_mutex);
1255
1256         /* If we've screwed up tracking, just let the interrupt fire again */
1257         if (WARN_ON(!dev_priv->l3_parity.which_slice))
1258                 goto out;
1259
1260         misccpctl = I915_READ(GEN7_MISCCPCTL);
1261         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1262         POSTING_READ(GEN7_MISCCPCTL);
1263
1264         while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1265                 i915_reg_t reg;
1266
1267                 slice--;
1268                 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv)))
1269                         break;
1270
1271                 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1272
1273                 reg = GEN7_L3CDERRST1(slice);
1274
1275                 error_status = I915_READ(reg);
1276                 row = GEN7_PARITY_ERROR_ROW(error_status);
1277                 bank = GEN7_PARITY_ERROR_BANK(error_status);
1278                 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1279
1280                 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1281                 POSTING_READ(reg);
1282
1283                 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1284                 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1285                 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1286                 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1287                 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1288                 parity_event[5] = NULL;
1289
1290                 kobject_uevent_env(&dev_priv->drm.primary->kdev->kobj,
1291                                    KOBJ_CHANGE, parity_event);
1292
1293                 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1294                           slice, row, bank, subbank);
1295
1296                 kfree(parity_event[4]);
1297                 kfree(parity_event[3]);
1298                 kfree(parity_event[2]);
1299                 kfree(parity_event[1]);
1300         }
1301
1302         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1303
1304 out:
1305         WARN_ON(dev_priv->l3_parity.which_slice);
1306         spin_lock_irq(&dev_priv->irq_lock);
1307         gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv));
1308         spin_unlock_irq(&dev_priv->irq_lock);
1309
1310         mutex_unlock(&dev_priv->drm.struct_mutex);
1311 }
1312
1313 static void ivybridge_parity_error_irq_handler(struct drm_i915_private *dev_priv,
1314                                                u32 iir)
1315 {
1316         if (!HAS_L3_DPF(dev_priv))
1317                 return;
1318
1319         spin_lock(&dev_priv->irq_lock);
1320         gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv));
1321         spin_unlock(&dev_priv->irq_lock);
1322
1323         iir &= GT_PARITY_ERROR(dev_priv);
1324         if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1325                 dev_priv->l3_parity.which_slice |= 1 << 1;
1326
1327         if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1328                 dev_priv->l3_parity.which_slice |= 1 << 0;
1329
1330         queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1331 }
1332
1333 static void ilk_gt_irq_handler(struct drm_i915_private *dev_priv,
1334                                u32 gt_iir)
1335 {
1336         if (gt_iir & GT_RENDER_USER_INTERRUPT)
1337                 notify_ring(dev_priv->engine[RCS]);
1338         if (gt_iir & ILK_BSD_USER_INTERRUPT)
1339                 notify_ring(dev_priv->engine[VCS]);
1340 }
1341
1342 static void snb_gt_irq_handler(struct drm_i915_private *dev_priv,
1343                                u32 gt_iir)
1344 {
1345         if (gt_iir & GT_RENDER_USER_INTERRUPT)
1346                 notify_ring(dev_priv->engine[RCS]);
1347         if (gt_iir & GT_BSD_USER_INTERRUPT)
1348                 notify_ring(dev_priv->engine[VCS]);
1349         if (gt_iir & GT_BLT_USER_INTERRUPT)
1350                 notify_ring(dev_priv->engine[BCS]);
1351
1352         if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1353                       GT_BSD_CS_ERROR_INTERRUPT |
1354                       GT_RENDER_CS_MASTER_ERROR_INTERRUPT))
1355                 DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir);
1356
1357         if (gt_iir & GT_PARITY_ERROR(dev_priv))
1358                 ivybridge_parity_error_irq_handler(dev_priv, gt_iir);
1359 }
1360
1361 static __always_inline void
1362 gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir, int test_shift)
1363 {
1364         if (iir & (GT_RENDER_USER_INTERRUPT << test_shift))
1365                 notify_ring(engine);
1366
1367         if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << test_shift)) {
1368                 set_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
1369                 tasklet_hi_schedule(&engine->irq_tasklet);
1370         }
1371 }
1372
1373 static irqreturn_t gen8_gt_irq_ack(struct drm_i915_private *dev_priv,
1374                                    u32 master_ctl,
1375                                    u32 gt_iir[4])
1376 {
1377         irqreturn_t ret = IRQ_NONE;
1378
1379         if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1380                 gt_iir[0] = I915_READ_FW(GEN8_GT_IIR(0));
1381                 if (gt_iir[0]) {
1382                         I915_WRITE_FW(GEN8_GT_IIR(0), gt_iir[0]);
1383                         ret = IRQ_HANDLED;
1384                 } else
1385                         DRM_ERROR("The master control interrupt lied (GT0)!\n");
1386         }
1387
1388         if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
1389                 gt_iir[1] = I915_READ_FW(GEN8_GT_IIR(1));
1390                 if (gt_iir[1]) {
1391                         I915_WRITE_FW(GEN8_GT_IIR(1), gt_iir[1]);
1392                         ret = IRQ_HANDLED;
1393                 } else
1394                         DRM_ERROR("The master control interrupt lied (GT1)!\n");
1395         }
1396
1397         if (master_ctl & GEN8_GT_VECS_IRQ) {
1398                 gt_iir[3] = I915_READ_FW(GEN8_GT_IIR(3));
1399                 if (gt_iir[3]) {
1400                         I915_WRITE_FW(GEN8_GT_IIR(3), gt_iir[3]);
1401                         ret = IRQ_HANDLED;
1402                 } else
1403                         DRM_ERROR("The master control interrupt lied (GT3)!\n");
1404         }
1405
1406         if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) {
1407                 gt_iir[2] = I915_READ_FW(GEN8_GT_IIR(2));
1408                 if (gt_iir[2] & (dev_priv->pm_rps_events |
1409                                  dev_priv->pm_guc_events)) {
1410                         I915_WRITE_FW(GEN8_GT_IIR(2),
1411                                       gt_iir[2] & (dev_priv->pm_rps_events |
1412                                                    dev_priv->pm_guc_events));
1413                         ret = IRQ_HANDLED;
1414                 } else
1415                         DRM_ERROR("The master control interrupt lied (PM)!\n");
1416         }
1417
1418         return ret;
1419 }
1420
1421 static void gen8_gt_irq_handler(struct drm_i915_private *dev_priv,
1422                                 u32 gt_iir[4])
1423 {
1424         if (gt_iir[0]) {
1425                 gen8_cs_irq_handler(dev_priv->engine[RCS],
1426                                     gt_iir[0], GEN8_RCS_IRQ_SHIFT);
1427                 gen8_cs_irq_handler(dev_priv->engine[BCS],
1428                                     gt_iir[0], GEN8_BCS_IRQ_SHIFT);
1429         }
1430
1431         if (gt_iir[1]) {
1432                 gen8_cs_irq_handler(dev_priv->engine[VCS],
1433                                     gt_iir[1], GEN8_VCS1_IRQ_SHIFT);
1434                 gen8_cs_irq_handler(dev_priv->engine[VCS2],
1435                                     gt_iir[1], GEN8_VCS2_IRQ_SHIFT);
1436         }
1437
1438         if (gt_iir[3])
1439                 gen8_cs_irq_handler(dev_priv->engine[VECS],
1440                                     gt_iir[3], GEN8_VECS_IRQ_SHIFT);
1441
1442         if (gt_iir[2] & dev_priv->pm_rps_events)
1443                 gen6_rps_irq_handler(dev_priv, gt_iir[2]);
1444
1445         if (gt_iir[2] & dev_priv->pm_guc_events)
1446                 gen9_guc_irq_handler(dev_priv, gt_iir[2]);
1447 }
1448
1449 static bool bxt_port_hotplug_long_detect(enum port port, u32 val)
1450 {
1451         switch (port) {
1452         case PORT_A:
1453                 return val & PORTA_HOTPLUG_LONG_DETECT;
1454         case PORT_B:
1455                 return val & PORTB_HOTPLUG_LONG_DETECT;
1456         case PORT_C:
1457                 return val & PORTC_HOTPLUG_LONG_DETECT;
1458         default:
1459                 return false;
1460         }
1461 }
1462
1463 static bool spt_port_hotplug2_long_detect(enum port port, u32 val)
1464 {
1465         switch (port) {
1466         case PORT_E:
1467                 return val & PORTE_HOTPLUG_LONG_DETECT;
1468         default:
1469                 return false;
1470         }
1471 }
1472
1473 static bool spt_port_hotplug_long_detect(enum port port, u32 val)
1474 {
1475         switch (port) {
1476         case PORT_A:
1477                 return val & PORTA_HOTPLUG_LONG_DETECT;
1478         case PORT_B:
1479                 return val & PORTB_HOTPLUG_LONG_DETECT;
1480         case PORT_C:
1481                 return val & PORTC_HOTPLUG_LONG_DETECT;
1482         case PORT_D:
1483                 return val & PORTD_HOTPLUG_LONG_DETECT;
1484         default:
1485                 return false;
1486         }
1487 }
1488
1489 static bool ilk_port_hotplug_long_detect(enum port port, u32 val)
1490 {
1491         switch (port) {
1492         case PORT_A:
1493                 return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT;
1494         default:
1495                 return false;
1496         }
1497 }
1498
1499 static bool pch_port_hotplug_long_detect(enum port port, u32 val)
1500 {
1501         switch (port) {
1502         case PORT_B:
1503                 return val & PORTB_HOTPLUG_LONG_DETECT;
1504         case PORT_C:
1505                 return val & PORTC_HOTPLUG_LONG_DETECT;
1506         case PORT_D:
1507                 return val & PORTD_HOTPLUG_LONG_DETECT;
1508         default:
1509                 return false;
1510         }
1511 }
1512
1513 static bool i9xx_port_hotplug_long_detect(enum port port, u32 val)
1514 {
1515         switch (port) {
1516         case PORT_B:
1517                 return val & PORTB_HOTPLUG_INT_LONG_PULSE;
1518         case PORT_C:
1519                 return val & PORTC_HOTPLUG_INT_LONG_PULSE;
1520         case PORT_D:
1521                 return val & PORTD_HOTPLUG_INT_LONG_PULSE;
1522         default:
1523                 return false;
1524         }
1525 }
1526
1527 /*
1528  * Get a bit mask of pins that have triggered, and which ones may be long.
1529  * This can be called multiple times with the same masks to accumulate
1530  * hotplug detection results from several registers.
1531  *
1532  * Note that the caller is expected to zero out the masks initially.
1533  */
1534 static void intel_get_hpd_pins(u32 *pin_mask, u32 *long_mask,
1535                              u32 hotplug_trigger, u32 dig_hotplug_reg,
1536                              const u32 hpd[HPD_NUM_PINS],
1537                              bool long_pulse_detect(enum port port, u32 val))
1538 {
1539         enum port port;
1540         int i;
1541
1542         for_each_hpd_pin(i) {
1543                 if ((hpd[i] & hotplug_trigger) == 0)
1544                         continue;
1545
1546                 *pin_mask |= BIT(i);
1547
1548                 if (!intel_hpd_pin_to_port(i, &port))
1549                         continue;
1550
1551                 if (long_pulse_detect(port, dig_hotplug_reg))
1552                         *long_mask |= BIT(i);
1553         }
1554
1555         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x\n",
1556                          hotplug_trigger, dig_hotplug_reg, *pin_mask);
1557
1558 }
1559
1560 static void gmbus_irq_handler(struct drm_i915_private *dev_priv)
1561 {
1562         wake_up_all(&dev_priv->gmbus_wait_queue);
1563 }
1564
1565 static void dp_aux_irq_handler(struct drm_i915_private *dev_priv)
1566 {
1567         wake_up_all(&dev_priv->gmbus_wait_queue);
1568 }
1569
1570 #if defined(CONFIG_DEBUG_FS)
1571 static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1572                                          enum pipe pipe,
1573                                          uint32_t crc0, uint32_t crc1,
1574                                          uint32_t crc2, uint32_t crc3,
1575                                          uint32_t crc4)
1576 {
1577         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1578         struct intel_pipe_crc_entry *entry;
1579         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1580         struct drm_driver *driver = dev_priv->drm.driver;
1581         uint32_t crcs[5];
1582         int head, tail;
1583
1584         spin_lock(&pipe_crc->lock);
1585         if (pipe_crc->source) {
1586                 if (!pipe_crc->entries) {
1587                         spin_unlock(&pipe_crc->lock);
1588                         DRM_DEBUG_KMS("spurious interrupt\n");
1589                         return;
1590                 }
1591
1592                 head = pipe_crc->head;
1593                 tail = pipe_crc->tail;
1594
1595                 if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1596                         spin_unlock(&pipe_crc->lock);
1597                         DRM_ERROR("CRC buffer overflowing\n");
1598                         return;
1599                 }
1600
1601                 entry = &pipe_crc->entries[head];
1602
1603                 entry->frame = driver->get_vblank_counter(&dev_priv->drm, pipe);
1604                 entry->crc[0] = crc0;
1605                 entry->crc[1] = crc1;
1606                 entry->crc[2] = crc2;
1607                 entry->crc[3] = crc3;
1608                 entry->crc[4] = crc4;
1609
1610                 head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1611                 pipe_crc->head = head;
1612
1613                 spin_unlock(&pipe_crc->lock);
1614
1615                 wake_up_interruptible(&pipe_crc->wq);
1616         } else {
1617                 /*
1618                  * For some not yet identified reason, the first CRC is
1619                  * bonkers. So let's just wait for the next vblank and read
1620                  * out the buggy result.
1621                  *
1622                  * On CHV sometimes the second CRC is bonkers as well, so
1623                  * don't trust that one either.
1624                  */
1625                 if (pipe_crc->skipped == 0 ||
1626                     (IS_CHERRYVIEW(dev_priv) && pipe_crc->skipped == 1)) {
1627                         pipe_crc->skipped++;
1628                         spin_unlock(&pipe_crc->lock);
1629                         return;
1630                 }
1631                 spin_unlock(&pipe_crc->lock);
1632                 crcs[0] = crc0;
1633                 crcs[1] = crc1;
1634                 crcs[2] = crc2;
1635                 crcs[3] = crc3;
1636                 crcs[4] = crc4;
1637                 drm_crtc_add_crc_entry(&crtc->base, true,
1638                                        drm_accurate_vblank_count(&crtc->base),
1639                                        crcs);
1640         }
1641 }
1642 #else
1643 static inline void
1644 display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1645                              enum pipe pipe,
1646                              uint32_t crc0, uint32_t crc1,
1647                              uint32_t crc2, uint32_t crc3,
1648                              uint32_t crc4) {}
1649 #endif
1650
1651
1652 static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1653                                      enum pipe pipe)
1654 {
1655         display_pipe_crc_irq_handler(dev_priv, pipe,
1656                                      I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1657                                      0, 0, 0, 0);
1658 }
1659
1660 static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1661                                      enum pipe pipe)
1662 {
1663         display_pipe_crc_irq_handler(dev_priv, pipe,
1664                                      I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1665                                      I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1666                                      I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1667                                      I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1668                                      I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1669 }
1670
1671 static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1672                                       enum pipe pipe)
1673 {
1674         uint32_t res1, res2;
1675
1676         if (INTEL_GEN(dev_priv) >= 3)
1677                 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1678         else
1679                 res1 = 0;
1680
1681         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
1682                 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1683         else
1684                 res2 = 0;
1685
1686         display_pipe_crc_irq_handler(dev_priv, pipe,
1687                                      I915_READ(PIPE_CRC_RES_RED(pipe)),
1688                                      I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1689                                      I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1690                                      res1, res2);
1691 }
1692
1693 /* The RPS events need forcewake, so we add them to a work queue and mask their
1694  * IMR bits until the work is done. Other interrupts can be processed without
1695  * the work queue. */
1696 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1697 {
1698         if (pm_iir & dev_priv->pm_rps_events) {
1699                 spin_lock(&dev_priv->irq_lock);
1700                 gen6_mask_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
1701                 if (dev_priv->rps.interrupts_enabled) {
1702                         dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1703                         schedule_work(&dev_priv->rps.work);
1704                 }
1705                 spin_unlock(&dev_priv->irq_lock);
1706         }
1707
1708         if (INTEL_INFO(dev_priv)->gen >= 8)
1709                 return;
1710
1711         if (HAS_VEBOX(dev_priv)) {
1712                 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1713                         notify_ring(dev_priv->engine[VECS]);
1714
1715                 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT)
1716                         DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
1717         }
1718 }
1719
1720 static void gen9_guc_irq_handler(struct drm_i915_private *dev_priv, u32 gt_iir)
1721 {
1722         if (gt_iir & GEN9_GUC_TO_HOST_INT_EVENT) {
1723                 /* Sample the log buffer flush related bits & clear them out now
1724                  * itself from the message identity register to minimize the
1725                  * probability of losing a flush interrupt, when there are back
1726                  * to back flush interrupts.
1727                  * There can be a new flush interrupt, for different log buffer
1728                  * type (like for ISR), whilst Host is handling one (for DPC).
1729                  * Since same bit is used in message register for ISR & DPC, it
1730                  * could happen that GuC sets the bit for 2nd interrupt but Host
1731                  * clears out the bit on handling the 1st interrupt.
1732                  */
1733                 u32 msg, flush;
1734
1735                 msg = I915_READ(SOFT_SCRATCH(15));
1736                 flush = msg & (INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED |
1737                                INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER);
1738                 if (flush) {
1739                         /* Clear the message bits that are handled */
1740                         I915_WRITE(SOFT_SCRATCH(15), msg & ~flush);
1741
1742                         /* Handle flush interrupt in bottom half */
1743                         queue_work(dev_priv->guc.log.flush_wq,
1744                                    &dev_priv->guc.log.flush_work);
1745
1746                         dev_priv->guc.log.flush_interrupt_count++;
1747                 } else {
1748                         /* Not clearing of unhandled event bits won't result in
1749                          * re-triggering of the interrupt.
1750                          */
1751                 }
1752         }
1753 }
1754
1755 static bool intel_pipe_handle_vblank(struct drm_i915_private *dev_priv,
1756                                      enum pipe pipe)
1757 {
1758         bool ret;
1759
1760         ret = drm_handle_vblank(&dev_priv->drm, pipe);
1761         if (ret)
1762                 intel_finish_page_flip_mmio(dev_priv, pipe);
1763
1764         return ret;
1765 }
1766
1767 static void valleyview_pipestat_irq_ack(struct drm_i915_private *dev_priv,
1768                                         u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1769 {
1770         int pipe;
1771
1772         spin_lock(&dev_priv->irq_lock);
1773
1774         if (!dev_priv->display_irqs_enabled) {
1775                 spin_unlock(&dev_priv->irq_lock);
1776                 return;
1777         }
1778
1779         for_each_pipe(dev_priv, pipe) {
1780                 i915_reg_t reg;
1781                 u32 mask, iir_bit = 0;
1782
1783                 /*
1784                  * PIPESTAT bits get signalled even when the interrupt is
1785                  * disabled with the mask bits, and some of the status bits do
1786                  * not generate interrupts at all (like the underrun bit). Hence
1787                  * we need to be careful that we only handle what we want to
1788                  * handle.
1789                  */
1790
1791                 /* fifo underruns are filterered in the underrun handler. */
1792                 mask = PIPE_FIFO_UNDERRUN_STATUS;
1793
1794                 switch (pipe) {
1795                 case PIPE_A:
1796                         iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1797                         break;
1798                 case PIPE_B:
1799                         iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1800                         break;
1801                 case PIPE_C:
1802                         iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
1803                         break;
1804                 }
1805                 if (iir & iir_bit)
1806                         mask |= dev_priv->pipestat_irq_mask[pipe];
1807
1808                 if (!mask)
1809                         continue;
1810
1811                 reg = PIPESTAT(pipe);
1812                 mask |= PIPESTAT_INT_ENABLE_MASK;
1813                 pipe_stats[pipe] = I915_READ(reg) & mask;
1814
1815                 /*
1816                  * Clear the PIPE*STAT regs before the IIR
1817                  */
1818                 if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
1819                                         PIPESTAT_INT_STATUS_MASK))
1820                         I915_WRITE(reg, pipe_stats[pipe]);
1821         }
1822         spin_unlock(&dev_priv->irq_lock);
1823 }
1824
1825 static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1826                                             u32 pipe_stats[I915_MAX_PIPES])
1827 {
1828         enum pipe pipe;
1829
1830         for_each_pipe(dev_priv, pipe) {
1831                 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
1832                     intel_pipe_handle_vblank(dev_priv, pipe))
1833                         intel_check_page_flip(dev_priv, pipe);
1834
1835                 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV)
1836                         intel_finish_page_flip_cs(dev_priv, pipe);
1837
1838                 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1839                         i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1840
1841                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1842                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1843         }
1844
1845         if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1846                 gmbus_irq_handler(dev_priv);
1847 }
1848
1849 static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv)
1850 {
1851         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1852
1853         if (hotplug_status)
1854                 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1855
1856         return hotplug_status;
1857 }
1858
1859 static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv,
1860                                  u32 hotplug_status)
1861 {
1862         u32 pin_mask = 0, long_mask = 0;
1863
1864         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
1865             IS_CHERRYVIEW(dev_priv)) {
1866                 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
1867
1868                 if (hotplug_trigger) {
1869                         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1870                                            hotplug_trigger, hpd_status_g4x,
1871                                            i9xx_port_hotplug_long_detect);
1872
1873                         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1874                 }
1875
1876                 if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1877                         dp_aux_irq_handler(dev_priv);
1878         } else {
1879                 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1880
1881                 if (hotplug_trigger) {
1882                         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1883                                            hotplug_trigger, hpd_status_i915,
1884                                            i9xx_port_hotplug_long_detect);
1885                         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1886                 }
1887         }
1888 }
1889
1890 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1891 {
1892         struct drm_device *dev = arg;
1893         struct drm_i915_private *dev_priv = to_i915(dev);
1894         irqreturn_t ret = IRQ_NONE;
1895
1896         if (!intel_irqs_enabled(dev_priv))
1897                 return IRQ_NONE;
1898
1899         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1900         disable_rpm_wakeref_asserts(dev_priv);
1901
1902         do {
1903                 u32 iir, gt_iir, pm_iir;
1904                 u32 pipe_stats[I915_MAX_PIPES] = {};
1905                 u32 hotplug_status = 0;
1906                 u32 ier = 0;
1907
1908                 gt_iir = I915_READ(GTIIR);
1909                 pm_iir = I915_READ(GEN6_PMIIR);
1910                 iir = I915_READ(VLV_IIR);
1911
1912                 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1913                         break;
1914
1915                 ret = IRQ_HANDLED;
1916
1917                 /*
1918                  * Theory on interrupt generation, based on empirical evidence:
1919                  *
1920                  * x = ((VLV_IIR & VLV_IER) ||
1921                  *      (((GT_IIR & GT_IER) || (GEN6_PMIIR & GEN6_PMIER)) &&
1922                  *       (VLV_MASTER_IER & MASTER_INTERRUPT_ENABLE)));
1923                  *
1924                  * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1925                  * Hence we clear MASTER_INTERRUPT_ENABLE and VLV_IER to
1926                  * guarantee the CPU interrupt will be raised again even if we
1927                  * don't end up clearing all the VLV_IIR, GT_IIR, GEN6_PMIIR
1928                  * bits this time around.
1929                  */
1930                 I915_WRITE(VLV_MASTER_IER, 0);
1931                 ier = I915_READ(VLV_IER);
1932                 I915_WRITE(VLV_IER, 0);
1933
1934                 if (gt_iir)
1935                         I915_WRITE(GTIIR, gt_iir);
1936                 if (pm_iir)
1937                         I915_WRITE(GEN6_PMIIR, pm_iir);
1938
1939                 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1940                         hotplug_status = i9xx_hpd_irq_ack(dev_priv);
1941
1942                 /* Call regardless, as some status bits might not be
1943                  * signalled in iir */
1944                 valleyview_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1945
1946                 if (iir & (I915_LPE_PIPE_A_INTERRUPT |
1947                            I915_LPE_PIPE_B_INTERRUPT))
1948                         intel_lpe_audio_irq_handler(dev_priv);
1949
1950                 /*
1951                  * VLV_IIR is single buffered, and reflects the level
1952                  * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
1953                  */
1954                 if (iir)
1955                         I915_WRITE(VLV_IIR, iir);
1956
1957                 I915_WRITE(VLV_IER, ier);
1958                 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
1959                 POSTING_READ(VLV_MASTER_IER);
1960
1961                 if (gt_iir)
1962                         snb_gt_irq_handler(dev_priv, gt_iir);
1963                 if (pm_iir)
1964                         gen6_rps_irq_handler(dev_priv, pm_iir);
1965
1966                 if (hotplug_status)
1967                         i9xx_hpd_irq_handler(dev_priv, hotplug_status);
1968
1969                 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
1970         } while (0);
1971
1972         enable_rpm_wakeref_asserts(dev_priv);
1973
1974         return ret;
1975 }
1976
1977 static irqreturn_t cherryview_irq_handler(int irq, void *arg)
1978 {
1979         struct drm_device *dev = arg;
1980         struct drm_i915_private *dev_priv = to_i915(dev);
1981         irqreturn_t ret = IRQ_NONE;
1982
1983         if (!intel_irqs_enabled(dev_priv))
1984                 return IRQ_NONE;
1985
1986         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1987         disable_rpm_wakeref_asserts(dev_priv);
1988
1989         do {
1990                 u32 master_ctl, iir;
1991                 u32 gt_iir[4] = {};
1992                 u32 pipe_stats[I915_MAX_PIPES] = {};
1993                 u32 hotplug_status = 0;
1994                 u32 ier = 0;
1995
1996                 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
1997                 iir = I915_READ(VLV_IIR);
1998
1999                 if (master_ctl == 0 && iir == 0)
2000                         break;
2001
2002                 ret = IRQ_HANDLED;
2003
2004                 /*
2005                  * Theory on interrupt generation, based on empirical evidence:
2006                  *
2007                  * x = ((VLV_IIR & VLV_IER) ||
2008                  *      ((GEN8_MASTER_IRQ & ~GEN8_MASTER_IRQ_CONTROL) &&
2009                  *       (GEN8_MASTER_IRQ & GEN8_MASTER_IRQ_CONTROL)));
2010                  *
2011                  * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
2012                  * Hence we clear GEN8_MASTER_IRQ_CONTROL and VLV_IER to
2013                  * guarantee the CPU interrupt will be raised again even if we
2014                  * don't end up clearing all the VLV_IIR and GEN8_MASTER_IRQ_CONTROL
2015                  * bits this time around.
2016                  */
2017                 I915_WRITE(GEN8_MASTER_IRQ, 0);
2018                 ier = I915_READ(VLV_IER);
2019                 I915_WRITE(VLV_IER, 0);
2020
2021                 gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
2022
2023                 if (iir & I915_DISPLAY_PORT_INTERRUPT)
2024                         hotplug_status = i9xx_hpd_irq_ack(dev_priv);
2025
2026                 /* Call regardless, as some status bits might not be
2027                  * signalled in iir */
2028                 valleyview_pipestat_irq_ack(dev_priv, iir, pipe_stats);
2029
2030                 if (iir & (I915_LPE_PIPE_A_INTERRUPT |
2031                            I915_LPE_PIPE_B_INTERRUPT |
2032                            I915_LPE_PIPE_C_INTERRUPT))
2033                         intel_lpe_audio_irq_handler(dev_priv);
2034
2035                 /*
2036                  * VLV_IIR is single buffered, and reflects the level
2037                  * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
2038                  */
2039                 if (iir)
2040                         I915_WRITE(VLV_IIR, iir);
2041
2042                 I915_WRITE(VLV_IER, ier);
2043                 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2044                 POSTING_READ(GEN8_MASTER_IRQ);
2045
2046                 gen8_gt_irq_handler(dev_priv, gt_iir);
2047
2048                 if (hotplug_status)
2049                         i9xx_hpd_irq_handler(dev_priv, hotplug_status);
2050
2051                 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
2052         } while (0);
2053
2054         enable_rpm_wakeref_asserts(dev_priv);
2055
2056         return ret;
2057 }
2058
2059 static void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv,
2060                                 u32 hotplug_trigger,
2061                                 const u32 hpd[HPD_NUM_PINS])
2062 {
2063         u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2064
2065         /*
2066          * Somehow the PCH doesn't seem to really ack the interrupt to the CPU
2067          * unless we touch the hotplug register, even if hotplug_trigger is
2068          * zero. Not acking leads to "The master control interrupt lied (SDE)!"
2069          * errors.
2070          */
2071         dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2072         if (!hotplug_trigger) {
2073                 u32 mask = PORTA_HOTPLUG_STATUS_MASK |
2074                         PORTD_HOTPLUG_STATUS_MASK |
2075                         PORTC_HOTPLUG_STATUS_MASK |
2076                         PORTB_HOTPLUG_STATUS_MASK;
2077                 dig_hotplug_reg &= ~mask;
2078         }
2079
2080         I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2081         if (!hotplug_trigger)
2082                 return;
2083
2084         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2085                            dig_hotplug_reg, hpd,
2086                            pch_port_hotplug_long_detect);
2087
2088         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2089 }
2090
2091 static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2092 {
2093         int pipe;
2094         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
2095
2096         ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ibx);
2097
2098         if (pch_iir & SDE_AUDIO_POWER_MASK) {
2099                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
2100                                SDE_AUDIO_POWER_SHIFT);
2101                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
2102                                  port_name(port));
2103         }
2104
2105         if (pch_iir & SDE_AUX_MASK)
2106                 dp_aux_irq_handler(dev_priv);
2107
2108         if (pch_iir & SDE_GMBUS)
2109                 gmbus_irq_handler(dev_priv);
2110
2111         if (pch_iir & SDE_AUDIO_HDCP_MASK)
2112                 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
2113
2114         if (pch_iir & SDE_AUDIO_TRANS_MASK)
2115                 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
2116
2117         if (pch_iir & SDE_POISON)
2118                 DRM_ERROR("PCH poison interrupt\n");
2119
2120         if (pch_iir & SDE_FDI_MASK)
2121                 for_each_pipe(dev_priv, pipe)
2122                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
2123                                          pipe_name(pipe),
2124                                          I915_READ(FDI_RX_IIR(pipe)));
2125
2126         if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
2127                 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
2128
2129         if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
2130                 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
2131
2132         if (pch_iir & SDE_TRANSA_FIFO_UNDER)
2133                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
2134
2135         if (pch_iir & SDE_TRANSB_FIFO_UNDER)
2136                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
2137 }
2138
2139 static void ivb_err_int_handler(struct drm_i915_private *dev_priv)
2140 {
2141         u32 err_int = I915_READ(GEN7_ERR_INT);
2142         enum pipe pipe;
2143
2144         if (err_int & ERR_INT_POISON)
2145                 DRM_ERROR("Poison interrupt\n");
2146
2147         for_each_pipe(dev_priv, pipe) {
2148                 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
2149                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2150
2151                 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
2152                         if (IS_IVYBRIDGE(dev_priv))
2153                                 ivb_pipe_crc_irq_handler(dev_priv, pipe);
2154                         else
2155                                 hsw_pipe_crc_irq_handler(dev_priv, pipe);
2156                 }
2157         }
2158
2159         I915_WRITE(GEN7_ERR_INT, err_int);
2160 }
2161
2162 static void cpt_serr_int_handler(struct drm_i915_private *dev_priv)
2163 {
2164         u32 serr_int = I915_READ(SERR_INT);
2165
2166         if (serr_int & SERR_INT_POISON)
2167                 DRM_ERROR("PCH poison interrupt\n");
2168
2169         if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
2170                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
2171
2172         if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
2173                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
2174
2175         if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
2176                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C);
2177
2178         I915_WRITE(SERR_INT, serr_int);
2179 }
2180
2181 static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2182 {
2183         int pipe;
2184         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
2185
2186         ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_cpt);
2187
2188         if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
2189                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
2190                                SDE_AUDIO_POWER_SHIFT_CPT);
2191                 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
2192                                  port_name(port));
2193         }
2194
2195         if (pch_iir & SDE_AUX_MASK_CPT)
2196                 dp_aux_irq_handler(dev_priv);
2197
2198         if (pch_iir & SDE_GMBUS_CPT)
2199                 gmbus_irq_handler(dev_priv);
2200
2201         if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
2202                 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
2203
2204         if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
2205                 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
2206
2207         if (pch_iir & SDE_FDI_MASK_CPT)
2208                 for_each_pipe(dev_priv, pipe)
2209                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
2210                                          pipe_name(pipe),
2211                                          I915_READ(FDI_RX_IIR(pipe)));
2212
2213         if (pch_iir & SDE_ERROR_CPT)
2214                 cpt_serr_int_handler(dev_priv);
2215 }
2216
2217 static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2218 {
2219         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
2220                 ~SDE_PORTE_HOTPLUG_SPT;
2221         u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT;
2222         u32 pin_mask = 0, long_mask = 0;
2223
2224         if (hotplug_trigger) {
2225                 u32 dig_hotplug_reg;
2226
2227                 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2228                 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2229
2230                 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2231                                    dig_hotplug_reg, hpd_spt,
2232                                    spt_port_hotplug_long_detect);
2233         }
2234
2235         if (hotplug2_trigger) {
2236                 u32 dig_hotplug_reg;
2237
2238                 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG2);
2239                 I915_WRITE(PCH_PORT_HOTPLUG2, dig_hotplug_reg);
2240
2241                 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug2_trigger,
2242                                    dig_hotplug_reg, hpd_spt,
2243                                    spt_port_hotplug2_long_detect);
2244         }
2245
2246         if (pin_mask)
2247                 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2248
2249         if (pch_iir & SDE_GMBUS_CPT)
2250                 gmbus_irq_handler(dev_priv);
2251 }
2252
2253 static void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv,
2254                                 u32 hotplug_trigger,
2255                                 const u32 hpd[HPD_NUM_PINS])
2256 {
2257         u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2258
2259         dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
2260         I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg);
2261
2262         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2263                            dig_hotplug_reg, hpd,
2264                            ilk_port_hotplug_long_detect);
2265
2266         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2267 }
2268
2269 static void ilk_display_irq_handler(struct drm_i915_private *dev_priv,
2270                                     u32 de_iir)
2271 {
2272         enum pipe pipe;
2273         u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG;
2274
2275         if (hotplug_trigger)
2276                 ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ilk);
2277
2278         if (de_iir & DE_AUX_CHANNEL_A)
2279                 dp_aux_irq_handler(dev_priv);
2280
2281         if (de_iir & DE_GSE)
2282                 intel_opregion_asle_intr(dev_priv);
2283
2284         if (de_iir & DE_POISON)
2285                 DRM_ERROR("Poison interrupt\n");
2286
2287         for_each_pipe(dev_priv, pipe) {
2288                 if (de_iir & DE_PIPE_VBLANK(pipe) &&
2289                     intel_pipe_handle_vblank(dev_priv, pipe))
2290                         intel_check_page_flip(dev_priv, pipe);
2291
2292                 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2293                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2294
2295                 if (de_iir & DE_PIPE_CRC_DONE(pipe))
2296                         i9xx_pipe_crc_irq_handler(dev_priv, pipe);
2297
2298                 /* plane/pipes map 1:1 on ilk+ */
2299                 if (de_iir & DE_PLANE_FLIP_DONE(pipe))
2300                         intel_finish_page_flip_cs(dev_priv, pipe);
2301         }
2302
2303         /* check event from PCH */
2304         if (de_iir & DE_PCH_EVENT) {
2305                 u32 pch_iir = I915_READ(SDEIIR);
2306
2307                 if (HAS_PCH_CPT(dev_priv))
2308                         cpt_irq_handler(dev_priv, pch_iir);
2309                 else
2310                         ibx_irq_handler(dev_priv, pch_iir);
2311
2312                 /* should clear PCH hotplug event before clear CPU irq */
2313                 I915_WRITE(SDEIIR, pch_iir);
2314         }
2315
2316         if (IS_GEN5(dev_priv) && de_iir & DE_PCU_EVENT)
2317                 ironlake_rps_change_irq_handler(dev_priv);
2318 }
2319
2320 static void ivb_display_irq_handler(struct drm_i915_private *dev_priv,
2321                                     u32 de_iir)
2322 {
2323         enum pipe pipe;
2324         u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB;
2325
2326         if (hotplug_trigger)
2327                 ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ivb);
2328
2329         if (de_iir & DE_ERR_INT_IVB)
2330                 ivb_err_int_handler(dev_priv);
2331
2332         if (de_iir & DE_AUX_CHANNEL_A_IVB)
2333                 dp_aux_irq_handler(dev_priv);
2334
2335         if (de_iir & DE_GSE_IVB)
2336                 intel_opregion_asle_intr(dev_priv);
2337
2338         for_each_pipe(dev_priv, pipe) {
2339                 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) &&
2340                     intel_pipe_handle_vblank(dev_priv, pipe))
2341                         intel_check_page_flip(dev_priv, pipe);
2342
2343                 /* plane/pipes map 1:1 on ilk+ */
2344                 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe))
2345                         intel_finish_page_flip_cs(dev_priv, pipe);
2346         }
2347
2348         /* check event from PCH */
2349         if (!HAS_PCH_NOP(dev_priv) && (de_iir & DE_PCH_EVENT_IVB)) {
2350                 u32 pch_iir = I915_READ(SDEIIR);
2351
2352                 cpt_irq_handler(dev_priv, pch_iir);
2353
2354                 /* clear PCH hotplug event before clear CPU irq */
2355                 I915_WRITE(SDEIIR, pch_iir);
2356         }
2357 }
2358
2359 /*
2360  * To handle irqs with the minimum potential races with fresh interrupts, we:
2361  * 1 - Disable Master Interrupt Control.
2362  * 2 - Find the source(s) of the interrupt.
2363  * 3 - Clear the Interrupt Identity bits (IIR).
2364  * 4 - Process the interrupt(s) that had bits set in the IIRs.
2365  * 5 - Re-enable Master Interrupt Control.
2366  */
2367 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
2368 {
2369         struct drm_device *dev = arg;
2370         struct drm_i915_private *dev_priv = to_i915(dev);
2371         u32 de_iir, gt_iir, de_ier, sde_ier = 0;
2372         irqreturn_t ret = IRQ_NONE;
2373
2374         if (!intel_irqs_enabled(dev_priv))
2375                 return IRQ_NONE;
2376
2377         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2378         disable_rpm_wakeref_asserts(dev_priv);
2379
2380         /* disable master interrupt before clearing iir  */
2381         de_ier = I915_READ(DEIER);
2382         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
2383         POSTING_READ(DEIER);
2384
2385         /* Disable south interrupts. We'll only write to SDEIIR once, so further
2386          * interrupts will will be stored on its back queue, and then we'll be
2387          * able to process them after we restore SDEIER (as soon as we restore
2388          * it, we'll get an interrupt if SDEIIR still has something to process
2389          * due to its back queue). */
2390         if (!HAS_PCH_NOP(dev_priv)) {
2391                 sde_ier = I915_READ(SDEIER);
2392                 I915_WRITE(SDEIER, 0);
2393                 POSTING_READ(SDEIER);
2394         }
2395
2396         /* Find, clear, then process each source of interrupt */
2397
2398         gt_iir = I915_READ(GTIIR);
2399         if (gt_iir) {
2400                 I915_WRITE(GTIIR, gt_iir);
2401                 ret = IRQ_HANDLED;
2402                 if (INTEL_GEN(dev_priv) >= 6)
2403                         snb_gt_irq_handler(dev_priv, gt_iir);
2404                 else
2405                         ilk_gt_irq_handler(dev_priv, gt_iir);
2406         }
2407
2408         de_iir = I915_READ(DEIIR);
2409         if (de_iir) {
2410                 I915_WRITE(DEIIR, de_iir);
2411                 ret = IRQ_HANDLED;
2412                 if (INTEL_GEN(dev_priv) >= 7)
2413                         ivb_display_irq_handler(dev_priv, de_iir);
2414                 else
2415                         ilk_display_irq_handler(dev_priv, de_iir);
2416         }
2417
2418         if (INTEL_GEN(dev_priv) >= 6) {
2419                 u32 pm_iir = I915_READ(GEN6_PMIIR);
2420                 if (pm_iir) {
2421                         I915_WRITE(GEN6_PMIIR, pm_iir);
2422                         ret = IRQ_HANDLED;
2423                         gen6_rps_irq_handler(dev_priv, pm_iir);
2424                 }
2425         }
2426
2427         I915_WRITE(DEIER, de_ier);
2428         POSTING_READ(DEIER);
2429         if (!HAS_PCH_NOP(dev_priv)) {
2430                 I915_WRITE(SDEIER, sde_ier);
2431                 POSTING_READ(SDEIER);
2432         }
2433
2434         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2435         enable_rpm_wakeref_asserts(dev_priv);
2436
2437         return ret;
2438 }
2439
2440 static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv,
2441                                 u32 hotplug_trigger,
2442                                 const u32 hpd[HPD_NUM_PINS])
2443 {
2444         u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2445
2446         dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2447         I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2448
2449         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2450                            dig_hotplug_reg, hpd,
2451                            bxt_port_hotplug_long_detect);
2452
2453         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2454 }
2455
2456 static irqreturn_t
2457 gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
2458 {
2459         irqreturn_t ret = IRQ_NONE;
2460         u32 iir;
2461         enum pipe pipe;
2462
2463         if (master_ctl & GEN8_DE_MISC_IRQ) {
2464                 iir = I915_READ(GEN8_DE_MISC_IIR);
2465                 if (iir) {
2466                         I915_WRITE(GEN8_DE_MISC_IIR, iir);
2467                         ret = IRQ_HANDLED;
2468                         if (iir & GEN8_DE_MISC_GSE)
2469                                 intel_opregion_asle_intr(dev_priv);
2470                         else
2471                                 DRM_ERROR("Unexpected DE Misc interrupt\n");
2472                 }
2473                 else
2474                         DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2475         }
2476
2477         if (master_ctl & GEN8_DE_PORT_IRQ) {
2478                 iir = I915_READ(GEN8_DE_PORT_IIR);
2479                 if (iir) {
2480                         u32 tmp_mask;
2481                         bool found = false;
2482
2483                         I915_WRITE(GEN8_DE_PORT_IIR, iir);
2484                         ret = IRQ_HANDLED;
2485
2486                         tmp_mask = GEN8_AUX_CHANNEL_A;
2487                         if (INTEL_INFO(dev_priv)->gen >= 9)
2488                                 tmp_mask |= GEN9_AUX_CHANNEL_B |
2489                                             GEN9_AUX_CHANNEL_C |
2490                                             GEN9_AUX_CHANNEL_D;
2491
2492                         if (iir & tmp_mask) {
2493                                 dp_aux_irq_handler(dev_priv);
2494                                 found = true;
2495                         }
2496
2497                         if (IS_GEN9_LP(dev_priv)) {
2498                                 tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK;
2499                                 if (tmp_mask) {
2500                                         bxt_hpd_irq_handler(dev_priv, tmp_mask,
2501                                                             hpd_bxt);
2502                                         found = true;
2503                                 }
2504                         } else if (IS_BROADWELL(dev_priv)) {
2505                                 tmp_mask = iir & GEN8_PORT_DP_A_HOTPLUG;
2506                                 if (tmp_mask) {
2507                                         ilk_hpd_irq_handler(dev_priv,
2508                                                             tmp_mask, hpd_bdw);
2509                                         found = true;
2510                                 }
2511                         }
2512
2513                         if (IS_GEN9_LP(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) {
2514                                 gmbus_irq_handler(dev_priv);
2515                                 found = true;
2516                         }
2517
2518                         if (!found)
2519                                 DRM_ERROR("Unexpected DE Port interrupt\n");
2520                 }
2521                 else
2522                         DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2523         }
2524
2525         for_each_pipe(dev_priv, pipe) {
2526                 u32 flip_done, fault_errors;
2527
2528                 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2529                         continue;
2530
2531                 iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2532                 if (!iir) {
2533                         DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2534                         continue;
2535                 }
2536
2537                 ret = IRQ_HANDLED;
2538                 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), iir);
2539
2540                 if (iir & GEN8_PIPE_VBLANK &&
2541                     intel_pipe_handle_vblank(dev_priv, pipe))
2542                         intel_check_page_flip(dev_priv, pipe);
2543
2544                 flip_done = iir;
2545                 if (INTEL_INFO(dev_priv)->gen >= 9)
2546                         flip_done &= GEN9_PIPE_PLANE1_FLIP_DONE;
2547                 else
2548                         flip_done &= GEN8_PIPE_PRIMARY_FLIP_DONE;
2549
2550                 if (flip_done)
2551                         intel_finish_page_flip_cs(dev_priv, pipe);
2552
2553                 if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
2554                         hsw_pipe_crc_irq_handler(dev_priv, pipe);
2555
2556                 if (iir & GEN8_PIPE_FIFO_UNDERRUN)
2557                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2558
2559                 fault_errors = iir;
2560                 if (INTEL_INFO(dev_priv)->gen >= 9)
2561                         fault_errors &= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
2562                 else
2563                         fault_errors &= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2564
2565                 if (fault_errors)
2566                         DRM_ERROR("Fault errors on pipe %c: 0x%08x\n",
2567                                   pipe_name(pipe),
2568                                   fault_errors);
2569         }
2570
2571         if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) &&
2572             master_ctl & GEN8_DE_PCH_IRQ) {
2573                 /*
2574                  * FIXME(BDW): Assume for now that the new interrupt handling
2575                  * scheme also closed the SDE interrupt handling race we've seen
2576                  * on older pch-split platforms. But this needs testing.
2577                  */
2578                 iir = I915_READ(SDEIIR);
2579                 if (iir) {
2580                         I915_WRITE(SDEIIR, iir);
2581                         ret = IRQ_HANDLED;
2582
2583                         if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv))
2584                                 spt_irq_handler(dev_priv, iir);
2585                         else
2586                                 cpt_irq_handler(dev_priv, iir);
2587                 } else {
2588                         /*
2589                          * Like on previous PCH there seems to be something
2590                          * fishy going on with forwarding PCH interrupts.
2591                          */
2592                         DRM_DEBUG_DRIVER("The master control interrupt lied (SDE)!\n");
2593                 }
2594         }
2595
2596         return ret;
2597 }
2598
2599 static irqreturn_t gen8_irq_handler(int irq, void *arg)
2600 {
2601         struct drm_device *dev = arg;
2602         struct drm_i915_private *dev_priv = to_i915(dev);
2603         u32 master_ctl;
2604         u32 gt_iir[4] = {};
2605         irqreturn_t ret;
2606
2607         if (!intel_irqs_enabled(dev_priv))
2608                 return IRQ_NONE;
2609
2610         master_ctl = I915_READ_FW(GEN8_MASTER_IRQ);
2611         master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
2612         if (!master_ctl)
2613                 return IRQ_NONE;
2614
2615         I915_WRITE_FW(GEN8_MASTER_IRQ, 0);
2616
2617         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2618         disable_rpm_wakeref_asserts(dev_priv);
2619
2620         /* Find, clear, then process each source of interrupt */
2621         ret = gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
2622         gen8_gt_irq_handler(dev_priv, gt_iir);
2623         ret |= gen8_de_irq_handler(dev_priv, master_ctl);
2624
2625         I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2626         POSTING_READ_FW(GEN8_MASTER_IRQ);
2627
2628         enable_rpm_wakeref_asserts(dev_priv);
2629
2630         return ret;
2631 }
2632
2633 static void i915_error_wake_up(struct drm_i915_private *dev_priv)
2634 {
2635         /*
2636          * Notify all waiters for GPU completion events that reset state has
2637          * been changed, and that they need to restart their wait after
2638          * checking for potential errors (and bail out to drop locks if there is
2639          * a gpu reset pending so that i915_error_work_func can acquire them).
2640          */
2641
2642         /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2643         wake_up_all(&dev_priv->gpu_error.wait_queue);
2644
2645         /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2646         wake_up_all(&dev_priv->pending_flip_queue);
2647 }
2648
2649 /**
2650  * i915_reset_and_wakeup - do process context error handling work
2651  * @dev_priv: i915 device private
2652  *
2653  * Fire an error uevent so userspace can see that a hang or error
2654  * was detected.
2655  */
2656 static void i915_reset_and_wakeup(struct drm_i915_private *dev_priv)
2657 {
2658         struct kobject *kobj = &dev_priv->drm.primary->kdev->kobj;
2659         char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
2660         char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
2661         char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
2662
2663         kobject_uevent_env(kobj, KOBJ_CHANGE, error_event);
2664
2665         DRM_DEBUG_DRIVER("resetting chip\n");
2666         kobject_uevent_env(kobj, KOBJ_CHANGE, reset_event);
2667
2668         /*
2669          * In most cases it's guaranteed that we get here with an RPM
2670          * reference held, for example because there is a pending GPU
2671          * request that won't finish until the reset is done. This
2672          * isn't the case at least when we get here by doing a
2673          * simulated reset via debugs, so get an RPM reference.
2674          */
2675         intel_runtime_pm_get(dev_priv);
2676         intel_prepare_reset(dev_priv);
2677
2678         do {
2679                 /*
2680                  * All state reset _must_ be completed before we update the
2681                  * reset counter, for otherwise waiters might miss the reset
2682                  * pending state and not properly drop locks, resulting in
2683                  * deadlocks with the reset work.
2684                  */
2685                 if (mutex_trylock(&dev_priv->drm.struct_mutex)) {
2686                         i915_reset(dev_priv);
2687                         mutex_unlock(&dev_priv->drm.struct_mutex);
2688                 }
2689
2690                 /* We need to wait for anyone holding the lock to wakeup */
2691         } while (wait_on_bit_timeout(&dev_priv->gpu_error.flags,
2692                                      I915_RESET_IN_PROGRESS,
2693                                      TASK_UNINTERRUPTIBLE,
2694                                      HZ));
2695
2696         intel_finish_reset(dev_priv);
2697         intel_runtime_pm_put(dev_priv);
2698
2699         if (!test_bit(I915_WEDGED, &dev_priv->gpu_error.flags))
2700                 kobject_uevent_env(kobj,
2701                                    KOBJ_CHANGE, reset_done_event);
2702
2703         /*
2704          * Note: The wake_up also serves as a memory barrier so that
2705          * waiters see the updated value of the dev_priv->gpu_error.
2706          */
2707         wake_up_all(&dev_priv->gpu_error.reset_queue);
2708 }
2709
2710 static inline void
2711 i915_err_print_instdone(struct drm_i915_private *dev_priv,
2712                         struct intel_instdone *instdone)
2713 {
2714         int slice;
2715         int subslice;
2716
2717         pr_err("  INSTDONE: 0x%08x\n", instdone->instdone);
2718
2719         if (INTEL_GEN(dev_priv) <= 3)
2720                 return;
2721
2722         pr_err("  SC_INSTDONE: 0x%08x\n", instdone->slice_common);
2723
2724         if (INTEL_GEN(dev_priv) <= 6)
2725                 return;
2726
2727         for_each_instdone_slice_subslice(dev_priv, slice, subslice)
2728                 pr_err("  SAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
2729                        slice, subslice, instdone->sampler[slice][subslice]);
2730
2731         for_each_instdone_slice_subslice(dev_priv, slice, subslice)
2732                 pr_err("  ROW_INSTDONE[%d][%d]: 0x%08x\n",
2733                        slice, subslice, instdone->row[slice][subslice]);
2734 }
2735
2736 static void i915_clear_error_registers(struct drm_i915_private *dev_priv)
2737 {
2738         u32 eir;
2739
2740         if (!IS_GEN2(dev_priv))
2741                 I915_WRITE(PGTBL_ER, I915_READ(PGTBL_ER));
2742
2743         if (INTEL_GEN(dev_priv) < 4)
2744                 I915_WRITE(IPEIR, I915_READ(IPEIR));
2745         else
2746                 I915_WRITE(IPEIR_I965, I915_READ(IPEIR_I965));
2747
2748         I915_WRITE(EIR, I915_READ(EIR));
2749         eir = I915_READ(EIR);
2750         if (eir) {
2751                 /*
2752                  * some errors might have become stuck,
2753                  * mask them.
2754                  */
2755                 DRM_DEBUG_DRIVER("EIR stuck: 0x%08x, masking\n", eir);
2756                 I915_WRITE(EMR, I915_READ(EMR) | eir);
2757                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2758         }
2759 }
2760
2761 /**
2762  * i915_handle_error - handle a gpu error
2763  * @dev_priv: i915 device private
2764  * @engine_mask: mask representing engines that are hung
2765  * @fmt: Error message format string
2766  *
2767  * Do some basic checking of register state at error time and
2768  * dump it to the syslog.  Also call i915_capture_error_state() to make
2769  * sure we get a record and make it available in debugfs.  Fire a uevent
2770  * so userspace knows something bad happened (should trigger collection
2771  * of a ring dump etc.).
2772  */
2773 void i915_handle_error(struct drm_i915_private *dev_priv,
2774                        u32 engine_mask,
2775                        const char *fmt, ...)
2776 {
2777         va_list args;
2778         char error_msg[80];
2779
2780         va_start(args, fmt);
2781         vscnprintf(error_msg, sizeof(error_msg), fmt, args);
2782         va_end(args);
2783
2784         i915_capture_error_state(dev_priv, engine_mask, error_msg);
2785         i915_clear_error_registers(dev_priv);
2786
2787         if (!engine_mask)
2788                 return;
2789
2790         if (test_and_set_bit(I915_RESET_IN_PROGRESS,
2791                              &dev_priv->gpu_error.flags))
2792                 return;
2793
2794         /*
2795          * Wakeup waiting processes so that the reset function
2796          * i915_reset_and_wakeup doesn't deadlock trying to grab
2797          * various locks. By bumping the reset counter first, the woken
2798          * processes will see a reset in progress and back off,
2799          * releasing their locks and then wait for the reset completion.
2800          * We must do this for _all_ gpu waiters that might hold locks
2801          * that the reset work needs to acquire.
2802          *
2803          * Note: The wake_up also provides a memory barrier to ensure that the
2804          * waiters see the updated value of the reset flags.
2805          */
2806         i915_error_wake_up(dev_priv);
2807
2808         i915_reset_and_wakeup(dev_priv);
2809 }
2810
2811 /* Called from drm generic code, passed 'crtc' which
2812  * we use as a pipe index
2813  */
2814 static int i8xx_enable_vblank(struct drm_device *dev, unsigned int pipe)
2815 {
2816         struct drm_i915_private *dev_priv = to_i915(dev);
2817         unsigned long irqflags;
2818
2819         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2820         i915_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS);
2821         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2822
2823         return 0;
2824 }
2825
2826 static int i965_enable_vblank(struct drm_device *dev, unsigned int pipe)
2827 {
2828         struct drm_i915_private *dev_priv = to_i915(dev);
2829         unsigned long irqflags;
2830
2831         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2832         i915_enable_pipestat(dev_priv, pipe,
2833                              PIPE_START_VBLANK_INTERRUPT_STATUS);
2834         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2835
2836         return 0;
2837 }
2838
2839 static int ironlake_enable_vblank(struct drm_device *dev, unsigned int pipe)
2840 {
2841         struct drm_i915_private *dev_priv = to_i915(dev);
2842         unsigned long irqflags;
2843         uint32_t bit = INTEL_GEN(dev_priv) >= 7 ?
2844                 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
2845
2846         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2847         ilk_enable_display_irq(dev_priv, bit);
2848         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2849
2850         return 0;
2851 }
2852
2853 static int gen8_enable_vblank(struct drm_device *dev, unsigned int pipe)
2854 {
2855         struct drm_i915_private *dev_priv = to_i915(dev);
2856         unsigned long irqflags;
2857
2858         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2859         bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
2860         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2861
2862         return 0;
2863 }
2864
2865 /* Called from drm generic code, passed 'crtc' which
2866  * we use as a pipe index
2867  */
2868 static void i8xx_disable_vblank(struct drm_device *dev, unsigned int pipe)
2869 {
2870         struct drm_i915_private *dev_priv = to_i915(dev);
2871         unsigned long irqflags;
2872
2873         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2874         i915_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS);
2875         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2876 }
2877
2878 static void i965_disable_vblank(struct drm_device *dev, unsigned int pipe)
2879 {
2880         struct drm_i915_private *dev_priv = to_i915(dev);
2881         unsigned long irqflags;
2882
2883         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2884         i915_disable_pipestat(dev_priv, pipe,
2885                               PIPE_START_VBLANK_INTERRUPT_STATUS);
2886         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2887 }
2888
2889 static void ironlake_disable_vblank(struct drm_device *dev, unsigned int pipe)
2890 {
2891         struct drm_i915_private *dev_priv = to_i915(dev);
2892         unsigned long irqflags;
2893         uint32_t bit = INTEL_GEN(dev_priv) >= 7 ?
2894                 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
2895
2896         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2897         ilk_disable_display_irq(dev_priv, bit);
2898         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2899 }
2900
2901 static void gen8_disable_vblank(struct drm_device *dev, unsigned int pipe)
2902 {
2903         struct drm_i915_private *dev_priv = to_i915(dev);
2904         unsigned long irqflags;
2905
2906         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2907         bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
2908         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2909 }
2910
2911 static void ibx_irq_reset(struct drm_i915_private *dev_priv)
2912 {
2913         if (HAS_PCH_NOP(dev_priv))
2914                 return;
2915
2916         GEN5_IRQ_RESET(SDE);
2917
2918         if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv))
2919                 I915_WRITE(SERR_INT, 0xffffffff);
2920 }
2921
2922 /*
2923  * SDEIER is also touched by the interrupt handler to work around missed PCH
2924  * interrupts. Hence we can't update it after the interrupt handler is enabled -
2925  * instead we unconditionally enable all PCH interrupt sources here, but then
2926  * only unmask them as needed with SDEIMR.
2927  *
2928  * This function needs to be called before interrupts are enabled.
2929  */
2930 static void ibx_irq_pre_postinstall(struct drm_device *dev)
2931 {
2932         struct drm_i915_private *dev_priv = to_i915(dev);
2933
2934         if (HAS_PCH_NOP(dev_priv))
2935                 return;
2936
2937         WARN_ON(I915_READ(SDEIER) != 0);
2938         I915_WRITE(SDEIER, 0xffffffff);
2939         POSTING_READ(SDEIER);
2940 }
2941
2942 static void gen5_gt_irq_reset(struct drm_i915_private *dev_priv)
2943 {
2944         GEN5_IRQ_RESET(GT);
2945         if (INTEL_GEN(dev_priv) >= 6)
2946                 GEN5_IRQ_RESET(GEN6_PM);
2947 }
2948
2949 static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
2950 {
2951         enum pipe pipe;
2952
2953         if (IS_CHERRYVIEW(dev_priv))
2954                 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
2955         else
2956                 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2957
2958         i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0);
2959         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2960
2961         for_each_pipe(dev_priv, pipe) {
2962                 I915_WRITE(PIPESTAT(pipe),
2963                            PIPE_FIFO_UNDERRUN_STATUS |
2964                            PIPESTAT_INT_STATUS_MASK);
2965                 dev_priv->pipestat_irq_mask[pipe] = 0;
2966         }
2967
2968         GEN5_IRQ_RESET(VLV_);
2969         dev_priv->irq_mask = ~0;
2970 }
2971
2972 static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
2973 {
2974         u32 pipestat_mask;
2975         u32 enable_mask;
2976         enum pipe pipe;
2977         u32 val;
2978
2979         pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
2980                         PIPE_CRC_DONE_INTERRUPT_STATUS;
2981
2982         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
2983         for_each_pipe(dev_priv, pipe)
2984                 i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
2985
2986         enable_mask = I915_DISPLAY_PORT_INTERRUPT |
2987                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2988                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
2989         if (IS_CHERRYVIEW(dev_priv))
2990                 enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
2991
2992         WARN_ON(dev_priv->irq_mask != ~0);
2993
2994         val = (I915_LPE_PIPE_A_INTERRUPT |
2995                 I915_LPE_PIPE_B_INTERRUPT |
2996                 I915_LPE_PIPE_C_INTERRUPT);
2997
2998         enable_mask |= val;
2999
3000         dev_priv->irq_mask = ~enable_mask;
3001
3002         GEN5_IRQ_INIT(VLV_, dev_priv->irq_mask, enable_mask);
3003 }
3004
3005 /* drm_dma.h hooks
3006 */
3007 static void ironlake_irq_reset(struct drm_device *dev)
3008 {
3009         struct drm_i915_private *dev_priv = to_i915(dev);
3010
3011         I915_WRITE(HWSTAM, 0xffffffff);
3012
3013         GEN5_IRQ_RESET(DE);
3014         if (IS_GEN7(dev_priv))
3015                 I915_WRITE(GEN7_ERR_INT, 0xffffffff);
3016
3017         gen5_gt_irq_reset(dev_priv);
3018
3019         ibx_irq_reset(dev_priv);
3020 }
3021
3022 static void valleyview_irq_preinstall(struct drm_device *dev)
3023 {
3024         struct drm_i915_private *dev_priv = to_i915(dev);
3025
3026         I915_WRITE(VLV_MASTER_IER, 0);
3027         POSTING_READ(VLV_MASTER_IER);
3028
3029         gen5_gt_irq_reset(dev_priv);
3030
3031         spin_lock_irq(&dev_priv->irq_lock);
3032         if (dev_priv->display_irqs_enabled)
3033                 vlv_display_irq_reset(dev_priv);
3034         spin_unlock_irq(&dev_priv->irq_lock);
3035 }
3036
3037 static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
3038 {
3039         GEN8_IRQ_RESET_NDX(GT, 0);
3040         GEN8_IRQ_RESET_NDX(GT, 1);
3041         GEN8_IRQ_RESET_NDX(GT, 2);
3042         GEN8_IRQ_RESET_NDX(GT, 3);
3043 }
3044
3045 static void gen8_irq_reset(struct drm_device *dev)
3046 {
3047         struct drm_i915_private *dev_priv = to_i915(dev);
3048         int pipe;
3049
3050         I915_WRITE(GEN8_MASTER_IRQ, 0);
3051         POSTING_READ(GEN8_MASTER_IRQ);
3052
3053         gen8_gt_irq_reset(dev_priv);
3054
3055         for_each_pipe(dev_priv, pipe)
3056                 if (intel_display_power_is_enabled(dev_priv,
3057                                                    POWER_DOMAIN_PIPE(pipe)))
3058                         GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3059
3060         GEN5_IRQ_RESET(GEN8_DE_PORT_);
3061         GEN5_IRQ_RESET(GEN8_DE_MISC_);
3062         GEN5_IRQ_RESET(GEN8_PCU_);
3063
3064         if (HAS_PCH_SPLIT(dev_priv))
3065                 ibx_irq_reset(dev_priv);
3066 }
3067
3068 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
3069                                      unsigned int pipe_mask)
3070 {
3071         uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
3072         enum pipe pipe;
3073
3074         spin_lock_irq(&dev_priv->irq_lock);
3075         for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3076                 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3077                                   dev_priv->de_irq_mask[pipe],
3078                                   ~dev_priv->de_irq_mask[pipe] | extra_ier);
3079         spin_unlock_irq(&dev_priv->irq_lock);
3080 }
3081
3082 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
3083                                      unsigned int pipe_mask)
3084 {
3085         enum pipe pipe;
3086
3087         spin_lock_irq(&dev_priv->irq_lock);
3088         for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3089                 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3090         spin_unlock_irq(&dev_priv->irq_lock);
3091
3092         /* make sure we're done processing display irqs */
3093         synchronize_irq(dev_priv->drm.irq);
3094 }
3095
3096 static void cherryview_irq_preinstall(struct drm_device *dev)
3097 {
3098         struct drm_i915_private *dev_priv = to_i915(dev);
3099
3100         I915_WRITE(GEN8_MASTER_IRQ, 0);
3101         POSTING_READ(GEN8_MASTER_IRQ);
3102
3103         gen8_gt_irq_reset(dev_priv);
3104
3105         GEN5_IRQ_RESET(GEN8_PCU_);
3106
3107         spin_lock_irq(&dev_priv->irq_lock);
3108         if (dev_priv->display_irqs_enabled)
3109                 vlv_display_irq_reset(dev_priv);
3110         spin_unlock_irq(&dev_priv->irq_lock);
3111 }
3112
3113 static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv,
3114                                   const u32 hpd[HPD_NUM_PINS])
3115 {
3116         struct intel_encoder *encoder;
3117         u32 enabled_irqs = 0;
3118
3119         for_each_intel_encoder(&dev_priv->drm, encoder)
3120                 if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
3121                         enabled_irqs |= hpd[encoder->hpd_pin];
3122
3123         return enabled_irqs;
3124 }
3125
3126 static void ibx_hpd_detection_setup(struct drm_i915_private *dev_priv)
3127 {
3128         u32 hotplug;
3129
3130         /*
3131          * Enable digital hotplug on the PCH, and configure the DP short pulse
3132          * duration to 2ms (which is the minimum in the Display Port spec).
3133          * The pulse duration bits are reserved on LPT+.
3134          */
3135         hotplug = I915_READ(PCH_PORT_HOTPLUG);
3136         hotplug &= ~(PORTB_PULSE_DURATION_MASK |
3137                      PORTC_PULSE_DURATION_MASK |
3138                      PORTD_PULSE_DURATION_MASK);
3139         hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
3140         hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
3141         hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
3142         /*
3143          * When CPU and PCH are on the same package, port A
3144          * HPD must be enabled in both north and south.
3145          */
3146         if (HAS_PCH_LPT_LP(dev_priv))
3147                 hotplug |= PORTA_HOTPLUG_ENABLE;
3148         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3149 }
3150
3151 static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv)
3152 {
3153         u32 hotplug_irqs, enabled_irqs;
3154
3155         if (HAS_PCH_IBX(dev_priv)) {
3156                 hotplug_irqs = SDE_HOTPLUG_MASK;
3157                 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ibx);
3158         } else {
3159                 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
3160                 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_cpt);
3161         }
3162
3163         ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3164
3165         ibx_hpd_detection_setup(dev_priv);
3166 }
3167
3168 static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv)
3169 {
3170         u32 hotplug;
3171
3172         /* Enable digital hotplug on the PCH */
3173         hotplug = I915_READ(PCH_PORT_HOTPLUG);
3174         hotplug |= PORTA_HOTPLUG_ENABLE |
3175                    PORTB_HOTPLUG_ENABLE |
3176                    PORTC_HOTPLUG_ENABLE |
3177                    PORTD_HOTPLUG_ENABLE;
3178         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3179
3180         hotplug = I915_READ(PCH_PORT_HOTPLUG2);
3181         hotplug |= PORTE_HOTPLUG_ENABLE;
3182         I915_WRITE(PCH_PORT_HOTPLUG2, hotplug);
3183 }
3184
3185 static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3186 {
3187         u32 hotplug_irqs, enabled_irqs;
3188
3189         hotplug_irqs = SDE_HOTPLUG_MASK_SPT;
3190         enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_spt);
3191
3192         ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3193
3194         spt_hpd_detection_setup(dev_priv);
3195 }
3196
3197 static void ilk_hpd_detection_setup(struct drm_i915_private *dev_priv)
3198 {
3199         u32 hotplug;
3200
3201         /*
3202          * Enable digital hotplug on the CPU, and configure the DP short pulse
3203          * duration to 2ms (which is the minimum in the Display Port spec)
3204          * The pulse duration bits are reserved on HSW+.
3205          */
3206         hotplug = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
3207         hotplug &= ~DIGITAL_PORTA_PULSE_DURATION_MASK;
3208         hotplug |= DIGITAL_PORTA_HOTPLUG_ENABLE |
3209                    DIGITAL_PORTA_PULSE_DURATION_2ms;
3210         I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, hotplug);
3211 }
3212
3213 static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv)
3214 {
3215         u32 hotplug_irqs, enabled_irqs;
3216
3217         if (INTEL_GEN(dev_priv) >= 8) {
3218                 hotplug_irqs = GEN8_PORT_DP_A_HOTPLUG;
3219                 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bdw);
3220
3221                 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3222         } else if (INTEL_GEN(dev_priv) >= 7) {
3223                 hotplug_irqs = DE_DP_A_HOTPLUG_IVB;
3224                 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ivb);
3225
3226                 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3227         } else {
3228                 hotplug_irqs = DE_DP_A_HOTPLUG;
3229                 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ilk);
3230
3231                 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3232         }
3233
3234         ilk_hpd_detection_setup(dev_priv);
3235
3236         ibx_hpd_irq_setup(dev_priv);
3237 }
3238
3239 static void __bxt_hpd_detection_setup(struct drm_i915_private *dev_priv,
3240                                       u32 enabled_irqs)
3241 {
3242         u32 hotplug;
3243
3244         hotplug = I915_READ(PCH_PORT_HOTPLUG);
3245         hotplug |= PORTA_HOTPLUG_ENABLE |
3246                    PORTB_HOTPLUG_ENABLE |
3247                    PORTC_HOTPLUG_ENABLE;
3248
3249         DRM_DEBUG_KMS("Invert bit setting: hp_ctl:%x hp_port:%x\n",
3250                       hotplug, enabled_irqs);
3251         hotplug &= ~BXT_DDI_HPD_INVERT_MASK;
3252
3253         /*
3254          * For BXT invert bit has to be set based on AOB design
3255          * for HPD detection logic, update it based on VBT fields.
3256          */
3257         if ((enabled_irqs & BXT_DE_PORT_HP_DDIA) &&
3258             intel_bios_is_port_hpd_inverted(dev_priv, PORT_A))
3259                 hotplug |= BXT_DDIA_HPD_INVERT;
3260         if ((enabled_irqs & BXT_DE_PORT_HP_DDIB) &&
3261             intel_bios_is_port_hpd_inverted(dev_priv, PORT_B))
3262                 hotplug |= BXT_DDIB_HPD_INVERT;
3263         if ((enabled_irqs & BXT_DE_PORT_HP_DDIC) &&
3264             intel_bios_is_port_hpd_inverted(dev_priv, PORT_C))
3265                 hotplug |= BXT_DDIC_HPD_INVERT;
3266
3267         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3268 }
3269
3270 static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv)
3271 {
3272         __bxt_hpd_detection_setup(dev_priv, BXT_DE_PORT_HOTPLUG_MASK);
3273 }
3274
3275 static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3276 {
3277         u32 hotplug_irqs, enabled_irqs;
3278
3279         enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bxt);
3280         hotplug_irqs = BXT_DE_PORT_HOTPLUG_MASK;
3281
3282         bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3283
3284         __bxt_hpd_detection_setup(dev_priv, enabled_irqs);
3285 }
3286
3287 static void ibx_irq_postinstall(struct drm_device *dev)
3288 {
3289         struct drm_i915_private *dev_priv = to_i915(dev);
3290         u32 mask;
3291
3292         if (HAS_PCH_NOP(dev_priv))
3293                 return;
3294
3295         if (HAS_PCH_IBX(dev_priv))
3296                 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
3297         else
3298                 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
3299
3300         gen5_assert_iir_is_zero(dev_priv, SDEIIR);
3301         I915_WRITE(SDEIMR, ~mask);
3302
3303         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
3304             HAS_PCH_LPT(dev_priv))
3305                 ibx_hpd_detection_setup(dev_priv);
3306         else
3307                 spt_hpd_detection_setup(dev_priv);
3308 }
3309
3310 static void gen5_gt_irq_postinstall(struct drm_device *dev)
3311 {
3312         struct drm_i915_private *dev_priv = to_i915(dev);
3313         u32 pm_irqs, gt_irqs;
3314
3315         pm_irqs = gt_irqs = 0;
3316
3317         dev_priv->gt_irq_mask = ~0;
3318         if (HAS_L3_DPF(dev_priv)) {
3319                 /* L3 parity interrupt is always unmasked. */
3320                 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev_priv);
3321                 gt_irqs |= GT_PARITY_ERROR(dev_priv);
3322         }
3323
3324         gt_irqs |= GT_RENDER_USER_INTERRUPT;
3325         if (IS_GEN5(dev_priv)) {
3326                 gt_irqs |= ILK_BSD_USER_INTERRUPT;
3327         } else {
3328                 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
3329         }
3330
3331         GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
3332
3333         if (INTEL_GEN(dev_priv) >= 6) {
3334                 /*
3335                  * RPS interrupts will get enabled/disabled on demand when RPS
3336                  * itself is enabled/disabled.
3337                  */
3338                 if (HAS_VEBOX(dev_priv)) {
3339                         pm_irqs |= PM_VEBOX_USER_INTERRUPT;
3340                         dev_priv->pm_ier |= PM_VEBOX_USER_INTERRUPT;
3341                 }
3342
3343                 dev_priv->pm_imr = 0xffffffff;
3344                 GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_imr, pm_irqs);
3345         }
3346 }
3347
3348 static int ironlake_irq_postinstall(struct drm_device *dev)
3349 {
3350         struct drm_i915_private *dev_priv = to_i915(dev);
3351         u32 display_mask, extra_mask;
3352
3353         if (INTEL_GEN(dev_priv) >= 7) {
3354                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3355                                 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
3356                                 DE_PLANEB_FLIP_DONE_IVB |
3357                                 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
3358                 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
3359                               DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB |
3360                               DE_DP_A_HOTPLUG_IVB);
3361         } else {
3362                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3363                                 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
3364                                 DE_AUX_CHANNEL_A |
3365                                 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
3366                                 DE_POISON);
3367                 extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
3368                               DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
3369                               DE_DP_A_HOTPLUG);
3370         }
3371
3372         dev_priv->irq_mask = ~display_mask;
3373
3374         I915_WRITE(HWSTAM, 0xeffe);
3375
3376         ibx_irq_pre_postinstall(dev);
3377
3378         GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
3379
3380         gen5_gt_irq_postinstall(dev);
3381
3382         ilk_hpd_detection_setup(dev_priv);
3383
3384         ibx_irq_postinstall(dev);
3385
3386         if (IS_IRONLAKE_M(dev_priv)) {
3387                 /* Enable PCU event interrupts
3388                  *
3389                  * spinlocking not required here for correctness since interrupt
3390                  * setup is guaranteed to run in single-threaded context. But we
3391                  * need it to make the assert_spin_locked happy. */
3392                 spin_lock_irq(&dev_priv->irq_lock);
3393                 ilk_enable_display_irq(dev_priv, DE_PCU_EVENT);
3394                 spin_unlock_irq(&dev_priv->irq_lock);
3395         }
3396
3397         return 0;
3398 }
3399
3400 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3401 {
3402         lockdep_assert_held(&dev_priv->irq_lock);
3403
3404         if (dev_priv->display_irqs_enabled)
3405                 return;
3406
3407         dev_priv->display_irqs_enabled = true;
3408
3409         if (intel_irqs_enabled(dev_priv)) {
3410                 vlv_display_irq_reset(dev_priv);
3411                 vlv_display_irq_postinstall(dev_priv);
3412         }
3413 }
3414
3415 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3416 {
3417         lockdep_assert_held(&dev_priv->irq_lock);
3418
3419         if (!dev_priv->display_irqs_enabled)
3420                 return;
3421
3422         dev_priv->display_irqs_enabled = false;
3423
3424         if (intel_irqs_enabled(dev_priv))
3425                 vlv_display_irq_reset(dev_priv);
3426 }
3427
3428
3429 static int valleyview_irq_postinstall(struct drm_device *dev)
3430 {
3431         struct drm_i915_private *dev_priv = to_i915(dev);
3432
3433         gen5_gt_irq_postinstall(dev);
3434
3435         spin_lock_irq(&dev_priv->irq_lock);
3436         if (dev_priv->display_irqs_enabled)
3437                 vlv_display_irq_postinstall(dev_priv);
3438         spin_unlock_irq(&dev_priv->irq_lock);
3439
3440         I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3441         POSTING_READ(VLV_MASTER_IER);
3442
3443         return 0;
3444 }
3445
3446 static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
3447 {
3448         /* These are interrupts we'll toggle with the ring mask register */
3449         uint32_t gt_interrupts[] = {
3450                 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3451                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3452                         GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT |
3453                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
3454                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3455                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3456                         GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT |
3457                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
3458                 0,
3459                 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT |
3460                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT
3461                 };
3462
3463         if (HAS_L3_DPF(dev_priv))
3464                 gt_interrupts[0] |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
3465
3466         dev_priv->pm_ier = 0x0;
3467         dev_priv->pm_imr = ~dev_priv->pm_ier;
3468         GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
3469         GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
3470         /*
3471          * RPS interrupts will get enabled/disabled on demand when RPS itself
3472          * is enabled/disabled. Same wil be the case for GuC interrupts.
3473          */
3474         GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_imr, dev_priv->pm_ier);
3475         GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
3476 }
3477
3478 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3479 {
3480         uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
3481         uint32_t de_pipe_enables;
3482         u32 de_port_masked = GEN8_AUX_CHANNEL_A;
3483         u32 de_port_enables;
3484         u32 de_misc_masked = GEN8_DE_MISC_GSE;
3485         enum pipe pipe;
3486
3487         if (INTEL_INFO(dev_priv)->gen >= 9) {
3488                 de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE |
3489                                   GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
3490                 de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
3491                                   GEN9_AUX_CHANNEL_D;
3492                 if (IS_GEN9_LP(dev_priv))
3493                         de_port_masked |= BXT_DE_PORT_GMBUS;
3494         } else {
3495                 de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
3496                                   GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
3497         }
3498
3499         de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
3500                                            GEN8_PIPE_FIFO_UNDERRUN;
3501
3502         de_port_enables = de_port_masked;
3503         if (IS_GEN9_LP(dev_priv))
3504                 de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
3505         else if (IS_BROADWELL(dev_priv))
3506                 de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
3507
3508         dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
3509         dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
3510         dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
3511
3512         for_each_pipe(dev_priv, pipe)
3513                 if (intel_display_power_is_enabled(dev_priv,
3514                                 POWER_DOMAIN_PIPE(pipe)))
3515                         GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3516                                           dev_priv->de_irq_mask[pipe],
3517                                           de_pipe_enables);
3518
3519         GEN5_IRQ_INIT(GEN8_DE_PORT_, ~de_port_masked, de_port_enables);
3520         GEN5_IRQ_INIT(GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked);
3521
3522         if (IS_GEN9_LP(dev_priv))
3523                 bxt_hpd_detection_setup(dev_priv);
3524         else if (IS_BROADWELL(dev_priv))
3525                 ilk_hpd_detection_setup(dev_priv);
3526 }
3527
3528 static int gen8_irq_postinstall(struct drm_device *dev)
3529 {
3530         struct drm_i915_private *dev_priv = to_i915(dev);
3531
3532         if (HAS_PCH_SPLIT(dev_priv))
3533                 ibx_irq_pre_postinstall(dev);
3534
3535         gen8_gt_irq_postinstall(dev_priv);
3536         gen8_de_irq_postinstall(dev_priv);
3537
3538         if (HAS_PCH_SPLIT(dev_priv))
3539                 ibx_irq_postinstall(dev);
3540
3541         I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
3542         POSTING_READ(GEN8_MASTER_IRQ);
3543
3544         return 0;
3545 }
3546
3547 static int cherryview_irq_postinstall(struct drm_device *dev)
3548 {
3549         struct drm_i915_private *dev_priv = to_i915(dev);
3550
3551         gen8_gt_irq_postinstall(dev_priv);
3552
3553         spin_lock_irq(&dev_priv->irq_lock);
3554         if (dev_priv->display_irqs_enabled)
3555                 vlv_display_irq_postinstall(dev_priv);
3556         spin_unlock_irq(&dev_priv->irq_lock);
3557
3558         I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
3559         POSTING_READ(GEN8_MASTER_IRQ);
3560
3561         return 0;
3562 }
3563
3564 static void gen8_irq_uninstall(struct drm_device *dev)
3565 {
3566         struct drm_i915_private *dev_priv = to_i915(dev);
3567
3568         if (!dev_priv)
3569                 return;
3570
3571         gen8_irq_reset(dev);
3572 }
3573
3574 static void valleyview_irq_uninstall(struct drm_device *dev)
3575 {
3576         struct drm_i915_private *dev_priv = to_i915(dev);
3577
3578         if (!dev_priv)
3579                 return;
3580
3581         I915_WRITE(VLV_MASTER_IER, 0);
3582         POSTING_READ(VLV_MASTER_IER);
3583
3584         gen5_gt_irq_reset(dev_priv);
3585
3586         I915_WRITE(HWSTAM, 0xffffffff);
3587
3588         spin_lock_irq(&dev_priv->irq_lock);
3589         if (dev_priv->display_irqs_enabled)
3590                 vlv_display_irq_reset(dev_priv);
3591         spin_unlock_irq(&dev_priv->irq_lock);
3592 }
3593
3594 static void cherryview_irq_uninstall(struct drm_device *dev)
3595 {
3596         struct drm_i915_private *dev_priv = to_i915(dev);
3597
3598         if (!dev_priv)
3599                 return;
3600
3601         I915_WRITE(GEN8_MASTER_IRQ, 0);
3602         POSTING_READ(GEN8_MASTER_IRQ);
3603
3604         gen8_gt_irq_reset(dev_priv);
3605
3606         GEN5_IRQ_RESET(GEN8_PCU_);
3607
3608         spin_lock_irq(&dev_priv->irq_lock);
3609         if (dev_priv->display_irqs_enabled)
3610                 vlv_display_irq_reset(dev_priv);
3611         spin_unlock_irq(&dev_priv->irq_lock);
3612 }
3613
3614 static void ironlake_irq_uninstall(struct drm_device *dev)
3615 {
3616         struct drm_i915_private *dev_priv = to_i915(dev);
3617
3618         if (!dev_priv)
3619                 return;
3620
3621         ironlake_irq_reset(dev);
3622 }
3623
3624 static void i8xx_irq_preinstall(struct drm_device * dev)
3625 {
3626         struct drm_i915_private *dev_priv = to_i915(dev);
3627         int pipe;
3628
3629         for_each_pipe(dev_priv, pipe)
3630                 I915_WRITE(PIPESTAT(pipe), 0);
3631         I915_WRITE16(IMR, 0xffff);
3632         I915_WRITE16(IER, 0x0);
3633         POSTING_READ16(IER);
3634 }
3635
3636 static int i8xx_irq_postinstall(struct drm_device *dev)
3637 {
3638         struct drm_i915_private *dev_priv = to_i915(dev);
3639
3640         I915_WRITE16(EMR,
3641                      ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3642
3643         /* Unmask the interrupts that we always want on. */
3644         dev_priv->irq_mask =
3645                 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3646                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3647                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3648                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3649         I915_WRITE16(IMR, dev_priv->irq_mask);
3650
3651         I915_WRITE16(IER,
3652                      I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3653                      I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3654                      I915_USER_INTERRUPT);
3655         POSTING_READ16(IER);
3656
3657         /* Interrupt setup is already guaranteed to be single-threaded, this is
3658          * just to make the assert_spin_locked check happy. */
3659         spin_lock_irq(&dev_priv->irq_lock);
3660         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3661         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3662         spin_unlock_irq(&dev_priv->irq_lock);
3663
3664         return 0;
3665 }
3666
3667 /*
3668  * Returns true when a page flip has completed.
3669  */
3670 static bool i8xx_handle_vblank(struct drm_i915_private *dev_priv,
3671                                int plane, int pipe, u32 iir)
3672 {
3673         u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3674
3675         if (!intel_pipe_handle_vblank(dev_priv, pipe))
3676                 return false;
3677
3678         if ((iir & flip_pending) == 0)
3679                 goto check_page_flip;
3680
3681         /* We detect FlipDone by looking for the change in PendingFlip from '1'
3682          * to '0' on the following vblank, i.e. IIR has the Pendingflip
3683          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3684          * the flip is completed (no longer pending). Since this doesn't raise
3685          * an interrupt per se, we watch for the change at vblank.
3686          */
3687         if (I915_READ16(ISR) & flip_pending)
3688                 goto check_page_flip;
3689
3690         intel_finish_page_flip_cs(dev_priv, pipe);
3691         return true;
3692
3693 check_page_flip:
3694         intel_check_page_flip(dev_priv, pipe);
3695         return false;
3696 }
3697
3698 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
3699 {
3700         struct drm_device *dev = arg;
3701         struct drm_i915_private *dev_priv = to_i915(dev);
3702         u16 iir, new_iir;
3703         u32 pipe_stats[2];
3704         int pipe;
3705         u16 flip_mask =
3706                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3707                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3708         irqreturn_t ret;
3709
3710         if (!intel_irqs_enabled(dev_priv))
3711                 return IRQ_NONE;
3712
3713         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
3714         disable_rpm_wakeref_asserts(dev_priv);
3715
3716         ret = IRQ_NONE;
3717         iir = I915_READ16(IIR);
3718         if (iir == 0)
3719                 goto out;
3720
3721         while (iir & ~flip_mask) {
3722                 /* Can't rely on pipestat interrupt bit in iir as it might
3723                  * have been cleared after the pipestat interrupt was received.
3724                  * It doesn't set the bit in iir again, but it still produces
3725                  * interrupts (for non-MSI).
3726                  */
3727                 spin_lock(&dev_priv->irq_lock);
3728                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3729                         DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
3730
3731                 for_each_pipe(dev_priv, pipe) {
3732                         i915_reg_t reg = PIPESTAT(pipe);
3733                         pipe_stats[pipe] = I915_READ(reg);
3734
3735                         /*
3736                          * Clear the PIPE*STAT regs before the IIR
3737                          */
3738                         if (pipe_stats[pipe] & 0x8000ffff)
3739                                 I915_WRITE(reg, pipe_stats[pipe]);
3740                 }
3741                 spin_unlock(&dev_priv->irq_lock);
3742
3743                 I915_WRITE16(IIR, iir & ~flip_mask);
3744                 new_iir = I915_READ16(IIR); /* Flush posted writes */
3745
3746                 if (iir & I915_USER_INTERRUPT)
3747                         notify_ring(dev_priv->engine[RCS]);
3748
3749                 for_each_pipe(dev_priv, pipe) {
3750                         int plane = pipe;
3751                         if (HAS_FBC(dev_priv))
3752                                 plane = !plane;
3753
3754                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3755                             i8xx_handle_vblank(dev_priv, plane, pipe, iir))
3756                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3757
3758                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3759                                 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
3760
3761                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3762                                 intel_cpu_fifo_underrun_irq_handler(dev_priv,
3763                                                                     pipe);
3764                 }
3765
3766                 iir = new_iir;
3767         }
3768         ret = IRQ_HANDLED;
3769
3770 out:
3771         enable_rpm_wakeref_asserts(dev_priv);
3772
3773         return ret;
3774 }
3775
3776 static void i8xx_irq_uninstall(struct drm_device * dev)
3777 {
3778         struct drm_i915_private *dev_priv = to_i915(dev);
3779         int pipe;
3780
3781         for_each_pipe(dev_priv, pipe) {
3782                 /* Clear enable bits; then clear status bits */
3783                 I915_WRITE(PIPESTAT(pipe), 0);
3784                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3785         }
3786         I915_WRITE16(IMR, 0xffff);
3787         I915_WRITE16(IER, 0x0);
3788         I915_WRITE16(IIR, I915_READ16(IIR));
3789 }
3790
3791 static void i915_irq_preinstall(struct drm_device * dev)
3792 {
3793         struct drm_i915_private *dev_priv = to_i915(dev);
3794         int pipe;
3795
3796         if (I915_HAS_HOTPLUG(dev_priv)) {
3797                 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
3798                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3799         }
3800
3801         I915_WRITE16(HWSTAM, 0xeffe);
3802         for_each_pipe(dev_priv, pipe)
3803                 I915_WRITE(PIPESTAT(pipe), 0);
3804         I915_WRITE(IMR, 0xffffffff);
3805         I915_WRITE(IER, 0x0);
3806         POSTING_READ(IER);
3807 }
3808
3809 static int i915_irq_postinstall(struct drm_device *dev)
3810 {
3811         struct drm_i915_private *dev_priv = to_i915(dev);
3812         u32 enable_mask;
3813
3814         I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3815
3816         /* Unmask the interrupts that we always want on. */
3817         dev_priv->irq_mask =
3818                 ~(I915_ASLE_INTERRUPT |
3819                   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3820                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3821                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3822                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3823
3824         enable_mask =
3825                 I915_ASLE_INTERRUPT |
3826                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3827                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3828                 I915_USER_INTERRUPT;
3829
3830         if (I915_HAS_HOTPLUG(dev_priv)) {
3831                 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
3832                 POSTING_READ(PORT_HOTPLUG_EN);
3833
3834                 /* Enable in IER... */
3835                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
3836                 /* and unmask in IMR */
3837                 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
3838         }
3839
3840         I915_WRITE(IMR, dev_priv->irq_mask);
3841         I915_WRITE(IER, enable_mask);
3842         POSTING_READ(IER);
3843
3844         i915_enable_asle_pipestat(dev_priv);
3845
3846         /* Interrupt setup is already guaranteed to be single-threaded, this is
3847          * just to make the assert_spin_locked check happy. */
3848         spin_lock_irq(&dev_priv->irq_lock);
3849         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3850         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3851         spin_unlock_irq(&dev_priv->irq_lock);
3852
3853         return 0;
3854 }
3855
3856 /*
3857  * Returns true when a page flip has completed.
3858  */
3859 static bool i915_handle_vblank(struct drm_i915_private *dev_priv,
3860                                int plane, int pipe, u32 iir)
3861 {
3862         u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3863
3864         if (!intel_pipe_handle_vblank(dev_priv, pipe))
3865                 return false;
3866
3867         if ((iir & flip_pending) == 0)
3868                 goto check_page_flip;
3869
3870         /* We detect FlipDone by looking for the change in PendingFlip from '1'
3871          * to '0' on the following vblank, i.e. IIR has the Pendingflip
3872          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3873          * the flip is completed (no longer pending). Since this doesn't raise
3874          * an interrupt per se, we watch for the change at vblank.
3875          */
3876         if (I915_READ(ISR) & flip_pending)
3877                 goto check_page_flip;
3878
3879         intel_finish_page_flip_cs(dev_priv, pipe);
3880         return true;
3881
3882 check_page_flip:
3883         intel_check_page_flip(dev_priv, pipe);
3884         return false;
3885 }
3886
3887 static irqreturn_t i915_irq_handler(int irq, void *arg)
3888 {
3889         struct drm_device *dev = arg;
3890         struct drm_i915_private *dev_priv = to_i915(dev);
3891         u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
3892         u32 flip_mask =
3893                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3894                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3895         int pipe, ret = IRQ_NONE;
3896
3897         if (!intel_irqs_enabled(dev_priv))
3898                 return IRQ_NONE;
3899
3900         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
3901         disable_rpm_wakeref_asserts(dev_priv);
3902
3903         iir = I915_READ(IIR);
3904         do {
3905                 bool irq_received = (iir & ~flip_mask) != 0;
3906                 bool blc_event = false;
3907
3908                 /* Can't rely on pipestat interrupt bit in iir as it might
3909                  * have been cleared after the pipestat interrupt was received.
3910                  * It doesn't set the bit in iir again, but it still produces
3911                  * interrupts (for non-MSI).
3912                  */
3913                 spin_lock(&dev_priv->irq_lock);
3914                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3915                         DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
3916
3917                 for_each_pipe(dev_priv, pipe) {
3918                         i915_reg_t reg = PIPESTAT(pipe);
3919                         pipe_stats[pipe] = I915_READ(reg);
3920
3921                         /* Clear the PIPE*STAT regs before the IIR */
3922                         if (pipe_stats[pipe] & 0x8000ffff) {
3923                                 I915_WRITE(reg, pipe_stats[pipe]);
3924                                 irq_received = true;
3925                         }
3926                 }
3927                 spin_unlock(&dev_priv->irq_lock);
3928
3929                 if (!irq_received)
3930                         break;
3931
3932                 /* Consume port.  Then clear IIR or we'll miss events */
3933                 if (I915_HAS_HOTPLUG(dev_priv) &&
3934                     iir & I915_DISPLAY_PORT_INTERRUPT) {
3935                         u32 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
3936                         if (hotplug_status)
3937                                 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
3938                 }
3939
3940                 I915_WRITE(IIR, iir & ~flip_mask);
3941                 new_iir = I915_READ(IIR); /* Flush posted writes */
3942
3943                 if (iir & I915_USER_INTERRUPT)
3944                         notify_ring(dev_priv->engine[RCS]);
3945
3946                 for_each_pipe(dev_priv, pipe) {
3947                         int plane = pipe;
3948                         if (HAS_FBC(dev_priv))
3949                                 plane = !plane;
3950
3951                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3952                             i915_handle_vblank(dev_priv, plane, pipe, iir))
3953                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3954
3955                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3956                                 blc_event = true;
3957
3958                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3959                                 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
3960
3961                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3962                                 intel_cpu_fifo_underrun_irq_handler(dev_priv,
3963                                                                     pipe);
3964                 }
3965
3966                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3967                         intel_opregion_asle_intr(dev_priv);
3968
3969                 /* With MSI, interrupts are only generated when iir
3970                  * transitions from zero to nonzero.  If another bit got
3971                  * set while we were handling the existing iir bits, then
3972                  * we would never get another interrupt.
3973                  *
3974                  * This is fine on non-MSI as well, as if we hit this path
3975                  * we avoid exiting the interrupt handler only to generate
3976                  * another one.
3977                  *
3978                  * Note that for MSI this could cause a stray interrupt report
3979                  * if an interrupt landed in the time between writing IIR and
3980                  * the posting read.  This should be rare enough to never
3981                  * trigger the 99% of 100,000 interrupts test for disabling
3982                  * stray interrupts.
3983                  */
3984                 ret = IRQ_HANDLED;
3985                 iir = new_iir;
3986         } while (iir & ~flip_mask);
3987
3988         enable_rpm_wakeref_asserts(dev_priv);
3989
3990         return ret;
3991 }
3992
3993 static void i915_irq_uninstall(struct drm_device * dev)
3994 {
3995         struct drm_i915_private *dev_priv = to_i915(dev);
3996         int pipe;
3997
3998         if (I915_HAS_HOTPLUG(dev_priv)) {
3999                 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4000                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4001         }
4002
4003         I915_WRITE16(HWSTAM, 0xffff);
4004         for_each_pipe(dev_priv, pipe) {
4005                 /* Clear enable bits; then clear status bits */
4006                 I915_WRITE(PIPESTAT(pipe), 0);
4007                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
4008         }
4009         I915_WRITE(IMR, 0xffffffff);
4010         I915_WRITE(IER, 0x0);
4011
4012         I915_WRITE(IIR, I915_READ(IIR));
4013 }
4014
4015 static void i965_irq_preinstall(struct drm_device * dev)
4016 {
4017         struct drm_i915_private *dev_priv = to_i915(dev);
4018         int pipe;
4019
4020         i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4021         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4022
4023         I915_WRITE(HWSTAM, 0xeffe);
4024         for_each_pipe(dev_priv, pipe)
4025                 I915_WRITE(PIPESTAT(pipe), 0);
4026         I915_WRITE(IMR, 0xffffffff);
4027         I915_WRITE(IER, 0x0);
4028         POSTING_READ(IER);
4029 }
4030
4031 static int i965_irq_postinstall(struct drm_device *dev)
4032 {
4033         struct drm_i915_private *dev_priv = to_i915(dev);
4034         u32 enable_mask;
4035         u32 error_mask;
4036
4037         /* Unmask the interrupts that we always want on. */
4038         dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
4039                                I915_DISPLAY_PORT_INTERRUPT |
4040                                I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4041                                I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4042                                I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4043                                I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
4044                                I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
4045
4046         enable_mask = ~dev_priv->irq_mask;
4047         enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4048                          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
4049         enable_mask |= I915_USER_INTERRUPT;
4050
4051         if (IS_G4X(dev_priv))
4052                 enable_mask |= I915_BSD_USER_INTERRUPT;
4053
4054         /* Interrupt setup is already guaranteed to be single-threaded, this is
4055          * just to make the assert_spin_locked check happy. */
4056         spin_lock_irq(&dev_priv->irq_lock);
4057         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
4058         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4059         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4060         spin_unlock_irq(&dev_priv->irq_lock);
4061
4062         /*
4063          * Enable some error detection, note the instruction error mask
4064          * bit is reserved, so we leave it masked.
4065          */
4066         if (IS_G4X(dev_priv)) {
4067                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
4068                                GM45_ERROR_MEM_PRIV |
4069                                GM45_ERROR_CP_PRIV |
4070                                I915_ERROR_MEMORY_REFRESH);
4071         } else {
4072                 error_mask = ~(I915_ERROR_PAGE_TABLE |
4073                                I915_ERROR_MEMORY_REFRESH);
4074         }
4075         I915_WRITE(EMR, error_mask);
4076
4077         I915_WRITE(IMR, dev_priv->irq_mask);
4078         I915_WRITE(IER, enable_mask);
4079         POSTING_READ(IER);
4080
4081         i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4082         POSTING_READ(PORT_HOTPLUG_EN);
4083
4084         i915_enable_asle_pipestat(dev_priv);
4085
4086         return 0;
4087 }
4088
4089 static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv)
4090 {
4091         u32 hotplug_en;
4092
4093         lockdep_assert_held(&dev_priv->irq_lock);
4094
4095         /* Note HDMI and DP share hotplug bits */
4096         /* enable bits are the same for all generations */
4097         hotplug_en = intel_hpd_enabled_irqs(dev_priv, hpd_mask_i915);
4098         /* Programming the CRT detection parameters tends
4099            to generate a spurious hotplug event about three
4100            seconds later.  So just do it once.
4101         */
4102         if (IS_G4X(dev_priv))
4103                 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
4104         hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
4105
4106         /* Ignore TV since it's buggy */
4107         i915_hotplug_interrupt_update_locked(dev_priv,
4108                                              HOTPLUG_INT_EN_MASK |
4109                                              CRT_HOTPLUG_VOLTAGE_COMPARE_MASK |
4110                                              CRT_HOTPLUG_ACTIVATION_PERIOD_64,
4111                                              hotplug_en);
4112 }
4113
4114 static irqreturn_t i965_irq_handler(int irq, void *arg)
4115 {
4116         struct drm_device *dev = arg;
4117         struct drm_i915_private *dev_priv = to_i915(dev);
4118         u32 iir, new_iir;
4119         u32 pipe_stats[I915_MAX_PIPES];
4120         int ret = IRQ_NONE, pipe;
4121         u32 flip_mask =
4122                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4123                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4124
4125         if (!intel_irqs_enabled(dev_priv))
4126                 return IRQ_NONE;
4127
4128         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4129         disable_rpm_wakeref_asserts(dev_priv);
4130
4131         iir = I915_READ(IIR);
4132
4133         for (;;) {
4134                 bool irq_received = (iir & ~flip_mask) != 0;
4135                 bool blc_event = false;
4136
4137                 /* Can't rely on pipestat interrupt bit in iir as it might
4138                  * have been cleared after the pipestat interrupt was received.
4139                  * It doesn't set the bit in iir again, but it still produces
4140                  * interrupts (for non-MSI).
4141                  */
4142                 spin_lock(&dev_priv->irq_lock);
4143                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4144                         DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
4145
4146                 for_each_pipe(dev_priv, pipe) {
4147                         i915_reg_t reg = PIPESTAT(pipe);
4148                         pipe_stats[pipe] = I915_READ(reg);
4149
4150                         /*
4151                          * Clear the PIPE*STAT regs before the IIR
4152                          */
4153                         if (pipe_stats[pipe] & 0x8000ffff) {
4154                                 I915_WRITE(reg, pipe_stats[pipe]);
4155                                 irq_received = true;
4156                         }
4157                 }
4158                 spin_unlock(&dev_priv->irq_lock);
4159
4160                 if (!irq_received)
4161                         break;
4162
4163                 ret = IRQ_HANDLED;
4164
4165                 /* Consume port.  Then clear IIR or we'll miss events */
4166                 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
4167                         u32 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
4168                         if (hotplug_status)
4169                                 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
4170                 }
4171
4172                 I915_WRITE(IIR, iir & ~flip_mask);
4173                 new_iir = I915_READ(IIR); /* Flush posted writes */
4174
4175                 if (iir & I915_USER_INTERRUPT)
4176                         notify_ring(dev_priv->engine[RCS]);
4177                 if (iir & I915_BSD_USER_INTERRUPT)
4178                         notify_ring(dev_priv->engine[VCS]);
4179
4180                 for_each_pipe(dev_priv, pipe) {
4181                         if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
4182                             i915_handle_vblank(dev_priv, pipe, pipe, iir))
4183                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
4184
4185                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4186                                 blc_event = true;
4187
4188                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4189                                 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
4190
4191                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4192                                 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
4193                 }
4194
4195                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4196                         intel_opregion_asle_intr(dev_priv);
4197
4198                 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
4199                         gmbus_irq_handler(dev_priv);
4200
4201                 /* With MSI, interrupts are only generated when iir
4202                  * transitions from zero to nonzero.  If another bit got
4203                  * set while we were handling the existing iir bits, then
4204                  * we would never get another interrupt.
4205                  *
4206                  * This is fine on non-MSI as well, as if we hit this path
4207                  * we avoid exiting the interrupt handler only to generate
4208                  * another one.
4209                  *
4210                  * Note that for MSI this could cause a stray interrupt report
4211                  * if an interrupt landed in the time between writing IIR and
4212                  * the posting read.  This should be rare enough to never
4213                  * trigger the 99% of 100,000 interrupts test for disabling
4214                  * stray interrupts.
4215                  */
4216                 iir = new_iir;
4217         }
4218
4219         enable_rpm_wakeref_asserts(dev_priv);
4220
4221         return ret;
4222 }
4223
4224 static void i965_irq_uninstall(struct drm_device * dev)
4225 {
4226         struct drm_i915_private *dev_priv = to_i915(dev);
4227         int pipe;
4228
4229         if (!dev_priv)
4230                 return;
4231
4232         i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4233         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4234
4235         I915_WRITE(HWSTAM, 0xffffffff);
4236         for_each_pipe(dev_priv, pipe)
4237                 I915_WRITE(PIPESTAT(pipe), 0);
4238         I915_WRITE(IMR, 0xffffffff);
4239         I915_WRITE(IER, 0x0);
4240
4241         for_each_pipe(dev_priv, pipe)
4242                 I915_WRITE(PIPESTAT(pipe),
4243                            I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
4244         I915_WRITE(IIR, I915_READ(IIR));
4245 }
4246
4247 /**
4248  * intel_irq_init - initializes irq support
4249  * @dev_priv: i915 device instance
4250  *
4251  * This function initializes all the irq support including work items, timers
4252  * and all the vtables. It does not setup the interrupt itself though.
4253  */
4254 void intel_irq_init(struct drm_i915_private *dev_priv)
4255 {
4256         struct drm_device *dev = &dev_priv->drm;
4257
4258         intel_hpd_init_work(dev_priv);
4259
4260         INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
4261         INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
4262
4263         if (HAS_GUC_SCHED(dev_priv))
4264                 dev_priv->pm_guc_events = GEN9_GUC_TO_HOST_INT_EVENT;
4265
4266         /* Let's track the enabled rps events */
4267         if (IS_VALLEYVIEW(dev_priv))
4268                 /* WaGsvRC0ResidencyMethod:vlv */
4269                 dev_priv->pm_rps_events = GEN6_PM_RP_UP_EI_EXPIRED;
4270         else
4271                 dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
4272
4273         dev_priv->rps.pm_intr_keep = 0;
4274
4275         /*
4276          * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer
4277          * if GEN6_PM_UP_EI_EXPIRED is masked.
4278          *
4279          * TODO: verify if this can be reproduced on VLV,CHV.
4280          */
4281         if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv))
4282                 dev_priv->rps.pm_intr_keep |= GEN6_PM_RP_UP_EI_EXPIRED;
4283
4284         if (INTEL_INFO(dev_priv)->gen >= 8)
4285                 dev_priv->rps.pm_intr_keep |= GEN8_PMINTR_REDIRECT_TO_GUC;
4286
4287         /*
4288          * The REDIRECT_TO_GUC bit of the PMINTRMSK register directs all
4289          * (unmasked) PM interrupts to the GuC. All other bits of this
4290          * register *disable* generation of a specific interrupt.
4291          *
4292          * 'pm_intr_keep' indicates bits that are NOT to be set when
4293          * writing to the PM interrupt mask register, i.e. interrupts
4294          * that must not be disabled.
4295          *
4296          * If the GuC is handling these interrupts, then we must not let
4297          * the PM code disable ANY interrupt that the GuC is expecting.
4298          * So for each ENABLED (0) bit in this register, we must SET the
4299          * bit in pm_intr_keep so that it's left enabled for the GuC.
4300          * GuC needs ARAT expired interrupt unmasked hence it is set in
4301          * pm_intr_keep.
4302          *
4303          * Here we CLEAR REDIRECT_TO_GUC bit in pm_intr_keep, which will
4304          * result in the register bit being left SET!
4305          */
4306         if (HAS_GUC_SCHED(dev_priv)) {
4307                 dev_priv->rps.pm_intr_keep |= ARAT_EXPIRED_INTRMSK;
4308                 dev_priv->rps.pm_intr_keep &= ~GEN8_PMINTR_REDIRECT_TO_GUC;
4309         }
4310
4311         if (IS_GEN2(dev_priv)) {
4312                 /* Gen2 doesn't have a hardware frame counter */
4313                 dev->max_vblank_count = 0;
4314         } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) {
4315                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
4316                 dev->driver->get_vblank_counter = g4x_get_vblank_counter;
4317         } else {
4318                 dev->driver->get_vblank_counter = i915_get_vblank_counter;
4319                 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
4320         }
4321
4322         /*
4323          * Opt out of the vblank disable timer on everything except gen2.
4324          * Gen2 doesn't have a hardware frame counter and so depends on
4325          * vblank interrupts to produce sane vblank seuquence numbers.
4326          */
4327         if (!IS_GEN2(dev_priv))
4328                 dev->vblank_disable_immediate = true;
4329
4330         /* Most platforms treat the display irq block as an always-on
4331          * power domain. vlv/chv can disable it at runtime and need
4332          * special care to avoid writing any of the display block registers
4333          * outside of the power domain. We defer setting up the display irqs
4334          * in this case to the runtime pm.
4335          */
4336         dev_priv->display_irqs_enabled = true;
4337         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4338                 dev_priv->display_irqs_enabled = false;
4339
4340         dev_priv->hotplug.hpd_storm_threshold = HPD_STORM_DEFAULT_THRESHOLD;
4341
4342         dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
4343         dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
4344
4345         if (IS_CHERRYVIEW(dev_priv)) {
4346                 dev->driver->irq_handler = cherryview_irq_handler;
4347                 dev->driver->irq_preinstall = cherryview_irq_preinstall;
4348                 dev->driver->irq_postinstall = cherryview_irq_postinstall;
4349                 dev->driver->irq_uninstall = cherryview_irq_uninstall;
4350                 dev->driver->enable_vblank = i965_enable_vblank;
4351                 dev->driver->disable_vblank = i965_disable_vblank;
4352                 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4353         } else if (IS_VALLEYVIEW(dev_priv)) {
4354                 dev->driver->irq_handler = valleyview_irq_handler;
4355                 dev->driver->irq_preinstall = valleyview_irq_preinstall;
4356                 dev->driver->irq_postinstall = valleyview_irq_postinstall;
4357                 dev->driver->irq_uninstall = valleyview_irq_uninstall;
4358                 dev->driver->enable_vblank = i965_enable_vblank;
4359                 dev->driver->disable_vblank = i965_disable_vblank;
4360                 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4361         } else if (INTEL_INFO(dev_priv)->gen >= 8) {
4362                 dev->driver->irq_handler = gen8_irq_handler;
4363                 dev->driver->irq_preinstall = gen8_irq_reset;
4364                 dev->driver->irq_postinstall = gen8_irq_postinstall;
4365                 dev->driver->irq_uninstall = gen8_irq_uninstall;
4366                 dev->driver->enable_vblank = gen8_enable_vblank;
4367                 dev->driver->disable_vblank = gen8_disable_vblank;
4368                 if (IS_GEN9_LP(dev_priv))
4369                         dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
4370                 else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv))
4371                         dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
4372                 else
4373                         dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4374         } else if (HAS_PCH_SPLIT(dev_priv)) {
4375                 dev->driver->irq_handler = ironlake_irq_handler;
4376                 dev->driver->irq_preinstall = ironlake_irq_reset;
4377                 dev->driver->irq_postinstall = ironlake_irq_postinstall;
4378                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
4379                 dev->driver->enable_vblank = ironlake_enable_vblank;
4380                 dev->driver->disable_vblank = ironlake_disable_vblank;
4381                 dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4382         } else {
4383                 if (IS_GEN2(dev_priv)) {
4384                         dev->driver->irq_preinstall = i8xx_irq_preinstall;
4385                         dev->driver->irq_postinstall = i8xx_irq_postinstall;
4386                         dev->driver->irq_handler = i8xx_irq_handler;
4387                         dev->driver->irq_uninstall = i8xx_irq_uninstall;
4388                         dev->driver->enable_vblank = i8xx_enable_vblank;
4389                         dev->driver->disable_vblank = i8xx_disable_vblank;
4390                 } else if (IS_GEN3(dev_priv)) {
4391                         dev->driver->irq_preinstall = i915_irq_preinstall;
4392                         dev->driver->irq_postinstall = i915_irq_postinstall;
4393                         dev->driver->irq_uninstall = i915_irq_uninstall;
4394                         dev->driver->irq_handler = i915_irq_handler;
4395                         dev->driver->enable_vblank = i8xx_enable_vblank;
4396                         dev->driver->disable_vblank = i8xx_disable_vblank;
4397                 } else {
4398                         dev->driver->irq_preinstall = i965_irq_preinstall;
4399                         dev->driver->irq_postinstall = i965_irq_postinstall;
4400                         dev->driver->irq_uninstall = i965_irq_uninstall;
4401                         dev->driver->irq_handler = i965_irq_handler;
4402                         dev->driver->enable_vblank = i965_enable_vblank;
4403                         dev->driver->disable_vblank = i965_disable_vblank;
4404                 }
4405                 if (I915_HAS_HOTPLUG(dev_priv))
4406                         dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4407         }
4408 }
4409
4410 /**
4411  * intel_irq_install - enables the hardware interrupt
4412  * @dev_priv: i915 device instance
4413  *
4414  * This function enables the hardware interrupt handling, but leaves the hotplug
4415  * handling still disabled. It is called after intel_irq_init().
4416  *
4417  * In the driver load and resume code we need working interrupts in a few places
4418  * but don't want to deal with the hassle of concurrent probe and hotplug
4419  * workers. Hence the split into this two-stage approach.
4420  */
4421 int intel_irq_install(struct drm_i915_private *dev_priv)
4422 {
4423         /*
4424          * We enable some interrupt sources in our postinstall hooks, so mark
4425          * interrupts as enabled _before_ actually enabling them to avoid
4426          * special cases in our ordering checks.
4427          */
4428         dev_priv->pm.irqs_enabled = true;
4429
4430         return drm_irq_install(&dev_priv->drm, dev_priv->drm.pdev->irq);
4431 }
4432
4433 /**
4434  * intel_irq_uninstall - finilizes all irq handling
4435  * @dev_priv: i915 device instance
4436  *
4437  * This stops interrupt and hotplug handling and unregisters and frees all
4438  * resources acquired in the init functions.
4439  */
4440 void intel_irq_uninstall(struct drm_i915_private *dev_priv)
4441 {
4442         drm_irq_uninstall(&dev_priv->drm);
4443         intel_hpd_cancel_work(dev_priv);
4444         dev_priv->pm.irqs_enabled = false;
4445 }
4446
4447 /**
4448  * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4449  * @dev_priv: i915 device instance
4450  *
4451  * This function is used to disable interrupts at runtime, both in the runtime
4452  * pm and the system suspend/resume code.
4453  */
4454 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
4455 {
4456         dev_priv->drm.driver->irq_uninstall(&dev_priv->drm);
4457         dev_priv->pm.irqs_enabled = false;
4458         synchronize_irq(dev_priv->drm.irq);
4459 }
4460
4461 /**
4462  * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4463  * @dev_priv: i915 device instance
4464  *
4465  * This function is used to enable interrupts at runtime, both in the runtime
4466  * pm and the system suspend/resume code.
4467  */
4468 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
4469 {
4470         dev_priv->pm.irqs_enabled = true;
4471         dev_priv->drm.driver->irq_preinstall(&dev_priv->drm);
4472         dev_priv->drm.driver->irq_postinstall(&dev_priv->drm);
4473 }