drivers/gpu/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <linux/cpufreq.h>
  29 #include "i915_drv.h"
  30 #include "intel_drv.h"
  31 #include "../../../platform/x86/intel_ips.h"
  32 #include <linux/module.h>
  33
  34 typedef enum _UHBUsage {
  35         OSPM_UHB_ONLY_IF_ON = 0,
  36         OSPM_UHB_FORCE_POWER_ON,
  37 } UHBUsage;
  38
  39 static struct drm_device *gdev;
  40
  41 #ifdef CONFIG_HAS_EARLYSUSPEND
  42         #include <linux/earlysuspend.h>
  43 #endif
  44
  45 /**
  46  * RC6 is a special power stage which allows the GPU to enter an very
  47  * low-voltage mode when idle, using down to 0V while at this stage.  This
  48  * stage is entered automatically when the GPU is idle when RC6 support is
  49  * enabled, and as soon as new workload arises GPU wakes up automatically as well.
  50  *
  51  * There are different RC6 modes available in Intel GPU, which differentiate
  52  * among each other with the latency required to enter and leave RC6 and
  53  * voltage consumed by the GPU in different states.
  54  *
  55  * The combination of the following flags define which states GPU is allowed
  56  * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
  57  * RC6pp is deepest RC6. Their support by hardware varies according to the
  58  * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
  59  * which brings the most power savings; deeper states save more power, but
  60  * require higher latency to switch to and wake up.
  61  */
  62 #define INTEL_RC6_ENABLE                        (1<<0)
  63 #define INTEL_RC6p_ENABLE                       (1<<1)
  64 #define INTEL_RC6pp_ENABLE                      (1<<2)
  65
  66 static void bxt_init_clock_gating(struct drm_device *dev)
  67 {
  68         struct drm_i915_private *dev_priv = dev->dev_private;
  69
  70         /* WaDisableSDEUnitClockGating:bxt */
  71         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
  72                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
  73
  74         /*
  75          * FIXME:
  76          * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
  77          */
  78         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
  79                    GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
  80 }
  81
  82 static void i915_pineview_get_mem_freq(struct drm_device *dev)
  83 {
  84         struct drm_i915_private *dev_priv = dev->dev_private;
  85         u32 tmp;
  86
  87         tmp = I915_READ(CLKCFG);
  88
  89         switch (tmp & CLKCFG_FSB_MASK) {
  90         case CLKCFG_FSB_533:
  91                 dev_priv->fsb_freq = 533; /* 133*4 */
  92                 break;
  93         case CLKCFG_FSB_800:
  94                 dev_priv->fsb_freq = 800; /* 200*4 */
  95                 break;
  96         case CLKCFG_FSB_667:
  97                 dev_priv->fsb_freq =  667; /* 167*4 */
  98                 break;
  99         case CLKCFG_FSB_400:
 100                 dev_priv->fsb_freq = 400; /* 100*4 */
 101                 break;
 102         }
 103
 104         switch (tmp & CLKCFG_MEM_MASK) {
 105         case CLKCFG_MEM_533:
 106                 dev_priv->mem_freq = 533;
 107                 break;
 108         case CLKCFG_MEM_667:
 109                 dev_priv->mem_freq = 667;
 110                 break;
 111         case CLKCFG_MEM_800:
 112                 dev_priv->mem_freq = 800;
 113                 break;
 114         }
 115
 116         /* detect pineview DDR3 setting */
 117         tmp = I915_READ(CSHRDDR3CTL);
 118         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 119 }
 120
 121 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
 122 {
 123         struct drm_i915_private *dev_priv = dev->dev_private;
 124         u16 ddrpll, csipll;
 125
 126         ddrpll = I915_READ16(DDRMPLL1);
 127         csipll = I915_READ16(CSIPLL0);
 128
 129         switch (ddrpll & 0xff) {
 130         case 0xc:
 131                 dev_priv->mem_freq = 800;
 132                 break;
 133         case 0x10:
 134                 dev_priv->mem_freq = 1066;
 135                 break;
 136         case 0x14:
 137                 dev_priv->mem_freq = 1333;
 138                 break;
 139         case 0x18:
 140                 dev_priv->mem_freq = 1600;
 141                 break;
 142         default:
 143                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
 144                                  ddrpll & 0xff);
 145                 dev_priv->mem_freq = 0;
 146                 break;
 147         }
 148
 149         dev_priv->ips.r_t = dev_priv->mem_freq;
 150
 151         switch (csipll & 0x3ff) {
 152         case 0x00c:
 153                 dev_priv->fsb_freq = 3200;
 154                 break;
 155         case 0x00e:
 156                 dev_priv->fsb_freq = 3733;
 157                 break;
 158         case 0x010:
 159                 dev_priv->fsb_freq = 4266;
 160                 break;
 161         case 0x012:
 162                 dev_priv->fsb_freq = 4800;
 163                 break;
 164         case 0x014:
 165                 dev_priv->fsb_freq = 5333;
 166                 break;
 167         case 0x016:
 168                 dev_priv->fsb_freq = 5866;
 169                 break;
 170         case 0x018:
 171                 dev_priv->fsb_freq = 6400;
 172                 break;
 173         default:
 174                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
 175                                  csipll & 0x3ff);
 176                 dev_priv->fsb_freq = 0;
 177                 break;
 178         }
 179
 180         if (dev_priv->fsb_freq == 3200) {
 181                 dev_priv->ips.c_m = 0;
 182         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
 183                 dev_priv->ips.c_m = 1;
 184         } else {
 185                 dev_priv->ips.c_m = 2;
 186         }
 187 }
 188
 189 static const struct cxsr_latency cxsr_latency_table[] = {
 190         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 191         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 192         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 193         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 194         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 195
 196         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 197         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 198         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 199         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 200         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 201
 202         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 203         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 204         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 205         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 206         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 207
 208         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 209         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 210         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 211         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 212         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 213
 214         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 215         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 216         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 217         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 218         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 219
 220         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 221         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 222         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 223         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 224         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 225 };
 226
 227 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
 228                                                          int is_ddr3,
 229                                                          int fsb,
 230                                                          int mem)
 231 {
 232         const struct cxsr_latency *latency;
 233         int i;
 234
 235         if (fsb == 0 || mem == 0)
 236                 return NULL;
 237
 238         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 239                 latency = &cxsr_latency_table[i];
 240                 if (is_desktop == latency->is_desktop &&
 241                     is_ddr3 == latency->is_ddr3 &&
 242                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 243                         return latency;
 244         }
 245
 246         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 247
 248         return NULL;
 249 }
 250
 251 static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
 252 {
 253         u32 val;
 254
 255         mutex_lock(&dev_priv->rps.hw_lock);
 256
 257         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
 258         if (enable)
 259                 val &= ~FORCE_DDR_HIGH_FREQ;
 260         else
 261                 val |= FORCE_DDR_HIGH_FREQ;
 262         val &= ~FORCE_DDR_LOW_FREQ;
 263         val |= FORCE_DDR_FREQ_REQ_ACK;
 264         vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
 265
 266         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
 267                       FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
 268                 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
 269
 270         mutex_unlock(&dev_priv->rps.hw_lock);
 271 }
 272
 273 static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
 274 {
 275         u32 val;
 276
 277         mutex_lock(&dev_priv->rps.hw_lock);
 278
 279         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
 280         if (enable)
 281                 val |= DSP_MAXFIFO_PM5_ENABLE;
 282         else
 283                 val &= ~DSP_MAXFIFO_PM5_ENABLE;
 284         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
 285
 286         mutex_unlock(&dev_priv->rps.hw_lock);
 287 }
 288
 289 #define FW_WM(value, plane) \
 290         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
 291
 292 void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
 293 {
 294         struct drm_device *dev = dev_priv->dev;
 295         u32 val;
 296
 297         if (IS_VALLEYVIEW(dev)) {
 298                 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
 299                 POSTING_READ(FW_BLC_SELF_VLV);
 300                 dev_priv->wm.vlv.cxsr = enable;
 301         } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
 302                 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
 303                 POSTING_READ(FW_BLC_SELF);
 304         } else if (IS_PINEVIEW(dev)) {
 305                 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
 306                 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
 307                 I915_WRITE(DSPFW3, val);
 308                 POSTING_READ(DSPFW3);
 309         } else if (IS_I945G(dev) || IS_I945GM(dev)) {
 310                 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
 311                                _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
 312                 I915_WRITE(FW_BLC_SELF, val);
 313                 POSTING_READ(FW_BLC_SELF);
 314         } else if (IS_I915GM(dev)) {
 315                 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
 316                                _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
 317                 I915_WRITE(INSTPM, val);
 318                 POSTING_READ(INSTPM);
 319         } else {
 320                 return;
 321         }
 322
 323         DRM_DEBUG_KMS("memory self-refresh is %s\n",
 324                       enable ? "enabled" : "disabled");
 325 }
 326
 327
 328 /*
 329  * Latency for FIFO fetches is dependent on several factors:
 330  *   - memory configuration (speed, channels)
 331  *   - chipset
 332  *   - current MCH state
 333  * It can be fairly high in some situations, so here we assume a fairly
 334  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 335  * set this value too high, the FIFO will fetch frequently to stay full)
 336  * and power consumption (set it too low to save power and we might see
 337  * FIFO underruns and display "flicker").
 338  *
 339  * A value of 5us seems to be a good balance; safe for very low end
 340  * platforms but not overly aggressive on lower latency configs.
 341  */
 342 static const int pessimal_latency_ns = 5000;
 343
 344 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
 345         ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
 346
 347 static int vlv_get_fifo_size(struct drm_device *dev,
 348                               enum pipe pipe, int plane)
 349 {
 350         struct drm_i915_private *dev_priv = dev->dev_private;
 351         int sprite0_start, sprite1_start, size;
 352
 353         switch (pipe) {
 354                 uint32_t dsparb, dsparb2, dsparb3;
 355         case PIPE_A:
 356                 dsparb = I915_READ(DSPARB);
 357                 dsparb2 = I915_READ(DSPARB2);
 358                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
 359                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
 360                 break;
 361         case PIPE_B:
 362                 dsparb = I915_READ(DSPARB);
 363                 dsparb2 = I915_READ(DSPARB2);
 364                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
 365                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
 366                 break;
 367         case PIPE_C:
 368                 dsparb2 = I915_READ(DSPARB2);
 369                 dsparb3 = I915_READ(DSPARB3);
 370                 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
 371                 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
 372                 break;
 373         default:
 374                 return 0;
 375         }
 376
 377         switch (plane) {
 378         case 0:
 379                 size = sprite0_start;
 380                 break;
 381         case 1:
 382                 size = sprite1_start - sprite0_start;
 383                 break;
 384         case 2:
 385                 size = 512 - 1 - sprite1_start;
 386                 break;
 387         default:
 388                 return 0;
 389         }
 390
 391         DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
 392                       pipe_name(pipe), plane == 0 ? "primary" : "sprite",
 393                       plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
 394                       size);
 395
 396         return size;
 397 }
 398
 399 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
 400 {
 401         struct drm_i915_private *dev_priv = dev->dev_private;
 402         uint32_t dsparb = I915_READ(DSPARB);
 403         int size;
 404
 405         size = dsparb & 0x7f;
 406         if (plane)
 407                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 408
 409         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 410                       plane ? "B" : "A", size);
 411
 412         return size;
 413 }
 414
 415 static int i830_get_fifo_size(struct drm_device *dev, int plane)
 416 {
 417         struct drm_i915_private *dev_priv = dev->dev_private;
 418         uint32_t dsparb = I915_READ(DSPARB);
 419         int size;
 420
 421         size = dsparb & 0x1ff;
 422         if (plane)
 423                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 424         size >>= 1; /* Convert to cachelines */
 425
 426         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 427                       plane ? "B" : "A", size);
 428
 429         return size;
 430 }
 431
 432 static int i845_get_fifo_size(struct drm_device *dev, int plane)
 433 {
 434         struct drm_i915_private *dev_priv = dev->dev_private;
 435         uint32_t dsparb = I915_READ(DSPARB);
 436         int size;
 437
 438         size = dsparb & 0x7f;
 439         size >>= 2; /* Convert to cachelines */
 440
 441         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 442                       plane ? "B" : "A",
 443                       size);
 444
 445         return size;
 446 }
 447
 448 /* Pineview has different values for various configs */
 449 static const struct intel_watermark_params pineview_display_wm = {
 450         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 451         .max_wm = PINEVIEW_MAX_WM,
 452         .default_wm = PINEVIEW_DFT_WM,
 453         .guard_size = PINEVIEW_GUARD_WM,
 454         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 455 };
 456 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 457         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 458         .max_wm = PINEVIEW_MAX_WM,
 459         .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
 460         .guard_size = PINEVIEW_GUARD_WM,
 461         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 462 };
 463 static const struct intel_watermark_params pineview_cursor_wm = {
 464         .fifo_size = PINEVIEW_CURSOR_FIFO,
 465         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 466         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 467         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 468         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 469 };
 470 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 471         .fifo_size = PINEVIEW_CURSOR_FIFO,
 472         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 473         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 474         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 475         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 476 };
 477 static const struct intel_watermark_params g4x_wm_info = {
 478         .fifo_size = G4X_FIFO_SIZE,
 479         .max_wm = G4X_MAX_WM,
 480         .default_wm = G4X_MAX_WM,
 481         .guard_size = 2,
 482         .cacheline_size = G4X_FIFO_LINE_SIZE,
 483 };
 484 static const struct intel_watermark_params g4x_cursor_wm_info = {
 485         .fifo_size = I965_CURSOR_FIFO,
 486         .max_wm = I965_CURSOR_MAX_WM,
 487         .default_wm = I965_CURSOR_DFT_WM,
 488         .guard_size = 2,
 489         .cacheline_size = G4X_FIFO_LINE_SIZE,
 490 };
 491 static const struct intel_watermark_params valleyview_wm_info = {
 492         .fifo_size = VALLEYVIEW_FIFO_SIZE,
 493         .max_wm = VALLEYVIEW_MAX_WM,
 494         .default_wm = VALLEYVIEW_MAX_WM,
 495         .guard_size = 2,
 496         .cacheline_size = G4X_FIFO_LINE_SIZE,
 497 };
 498 static const struct intel_watermark_params valleyview_cursor_wm_info = {
 499         .fifo_size = I965_CURSOR_FIFO,
 500         .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
 501         .default_wm = I965_CURSOR_DFT_WM,
 502         .guard_size = 2,
 503         .cacheline_size = G4X_FIFO_LINE_SIZE,
 504 };
 505 static const struct intel_watermark_params i965_cursor_wm_info = {
 506         .fifo_size = I965_CURSOR_FIFO,
 507         .max_wm = I965_CURSOR_MAX_WM,
 508         .default_wm = I965_CURSOR_DFT_WM,
 509         .guard_size = 2,
 510         .cacheline_size = I915_FIFO_LINE_SIZE,
 511 };
 512 static const struct intel_watermark_params i945_wm_info = {
 513         .fifo_size = I945_FIFO_SIZE,
 514         .max_wm = I915_MAX_WM,
 515         .default_wm = 1,
 516         .guard_size = 2,
 517         .cacheline_size = I915_FIFO_LINE_SIZE,
 518 };
 519 static const struct intel_watermark_params i915_wm_info = {
 520         .fifo_size = I915_FIFO_SIZE,
 521         .max_wm = I915_MAX_WM,
 522         .default_wm = 1,
 523         .guard_size = 2,
 524         .cacheline_size = I915_FIFO_LINE_SIZE,
 525 };
 526 static const struct intel_watermark_params i830_a_wm_info = {
 527         .fifo_size = I855GM_FIFO_SIZE,
 528         .max_wm = I915_MAX_WM,
 529         .default_wm = 1,
 530         .guard_size = 2,
 531         .cacheline_size = I830_FIFO_LINE_SIZE,
 532 };
 533 static const struct intel_watermark_params i830_bc_wm_info = {
 534         .fifo_size = I855GM_FIFO_SIZE,
 535         .max_wm = I915_MAX_WM/2,
 536         .default_wm = 1,
 537         .guard_size = 2,
 538         .cacheline_size = I830_FIFO_LINE_SIZE,
 539 };
 540 static const struct intel_watermark_params i845_wm_info = {
 541         .fifo_size = I830_FIFO_SIZE,
 542         .max_wm = I915_MAX_WM,
 543         .default_wm = 1,
 544         .guard_size = 2,
 545         .cacheline_size = I830_FIFO_LINE_SIZE,
 546 };
 547
 548 /**
 549  * intel_calculate_wm - calculate watermark level
 550  * @clock_in_khz: pixel clock
 551  * @wm: chip FIFO params
 552  * @pixel_size: display pixel size
 553  * @latency_ns: memory latency for the platform
 554  *
 555  * Calculate the watermark level (the level at which the display plane will
 556  * start fetching from memory again).  Each chip has a different display
 557  * FIFO size and allocation, so the caller needs to figure that out and pass
 558  * in the correct intel_watermark_params structure.
 559  *
 560  * As the pixel clock runs, the FIFO will be drained at a rate that depends
 561  * on the pixel size.  When it reaches the watermark level, it'll start
 562  * fetching FIFO line sized based chunks from memory until the FIFO fills
 563  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
 564  * will occur, and a display engine hang could result.
 565  */
 566 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
 567                                         const struct intel_watermark_params *wm,
 568                                         int fifo_size,
 569                                         int pixel_size,
 570                                         unsigned long latency_ns)
 571 {
 572         long entries_required, wm_size;
 573
 574         /*
 575          * Note: we need to make sure we don't overflow for various clock &
 576          * latency values.
 577          * clocks go from a few thousand to several hundred thousand.
 578          * latency is usually a few thousand
 579          */
 580         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
 581                 1000;
 582         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
 583
 584         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
 585
 586         wm_size = fifo_size - (entries_required + wm->guard_size);
 587
 588         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
 589
 590         /* Don't promote wm_size to unsigned... */
 591         if (wm_size > (long)wm->max_wm)
 592                 wm_size = wm->max_wm;
 593         if (wm_size <= 0)
 594                 wm_size = wm->default_wm;
 595
 596         /*
 597          * Bspec seems to indicate that the value shouldn't be lower than
 598          * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
 599          * Lets go for 8 which is the burst size since certain platforms
 600          * already use a hardcoded 8 (which is what the spec says should be
 601          * done).
 602          */
 603         if (wm_size <= 8)
 604                 wm_size = 8;
 605
 606         return wm_size;
 607 }
 608
 609 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
 610 {
 611         struct drm_crtc *crtc, *enabled = NULL;
 612
 613         for_each_crtc(dev, crtc) {
 614                 if (intel_crtc_active(crtc)) {
 615                         if (enabled)
 616                                 return NULL;
 617                         enabled = crtc;
 618                 }
 619         }
 620
 621         return enabled;
 622 }
 623
 624 static void pineview_update_wm(struct drm_crtc *unused_crtc)
 625 {
 626         struct drm_device *dev = unused_crtc->dev;
 627         struct drm_i915_private *dev_priv = dev->dev_private;
 628         struct drm_crtc *crtc;
 629         const struct cxsr_latency *latency;
 630         u32 reg;
 631         unsigned long wm;
 632
 633         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
 634                                          dev_priv->fsb_freq, dev_priv->mem_freq);
 635         if (!latency) {
 636                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 637                 intel_set_memory_cxsr(dev_priv, false);
 638                 return;
 639         }
 640
 641         crtc = single_enabled_crtc(dev);
 642         if (crtc) {
 643                 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 644                 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
 645                 int clock = adjusted_mode->crtc_clock;
 646
 647                 /* Display SR */
 648                 wm = intel_calculate_wm(clock, &pineview_display_wm,
 649                                         pineview_display_wm.fifo_size,
 650                                         pixel_size, latency->display_sr);
 651                 reg = I915_READ(DSPFW1);
 652                 reg &= ~DSPFW_SR_MASK;
 653                 reg |= FW_WM(wm, SR);
 654                 I915_WRITE(DSPFW1, reg);
 655                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
 656
 657                 /* cursor SR */
 658                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
 659                                         pineview_display_wm.fifo_size,
 660                                         pixel_size, latency->cursor_sr);
 661                 reg = I915_READ(DSPFW3);
 662                 reg &= ~DSPFW_CURSOR_SR_MASK;
 663                 reg |= FW_WM(wm, CURSOR_SR);
 664                 I915_WRITE(DSPFW3, reg);
 665
 666                 /* Display HPLL off SR */
 667                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
 668                                         pineview_display_hplloff_wm.fifo_size,
 669                                         pixel_size, latency->display_hpll_disable);
 670                 reg = I915_READ(DSPFW3);
 671                 reg &= ~DSPFW_HPLL_SR_MASK;
 672                 reg |= FW_WM(wm, HPLL_SR);
 673                 I915_WRITE(DSPFW3, reg);
 674
 675                 /* cursor HPLL off SR */
 676                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
 677                                         pineview_display_hplloff_wm.fifo_size,
 678                                         pixel_size, latency->cursor_hpll_disable);
 679                 reg = I915_READ(DSPFW3);
 680                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
 681                 reg |= FW_WM(wm, HPLL_CURSOR);
 682                 I915_WRITE(DSPFW3, reg);
 683                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
 684
 685                 intel_set_memory_cxsr(dev_priv, true);
 686         } else {
 687                 intel_set_memory_cxsr(dev_priv, false);
 688         }
 689 }
 690
 691 static bool g4x_compute_wm0(struct drm_device *dev,
 692                             int plane,
 693                             const struct intel_watermark_params *display,
 694                             int display_latency_ns,
 695                             const struct intel_watermark_params *cursor,
 696                             int cursor_latency_ns,
 697                             int *plane_wm,
 698                             int *cursor_wm)
 699 {
 700         struct drm_crtc *crtc;
 701         const struct drm_display_mode *adjusted_mode;
 702         int htotal, hdisplay, clock, pixel_size;
 703         int line_time_us, line_count;
 704         int entries, tlb_miss;
 705
 706         crtc = intel_get_crtc_for_plane(dev, plane);
 707         if (!intel_crtc_active(crtc)) {
 708                 *cursor_wm = cursor->guard_size;
 709                 *plane_wm = display->guard_size;
 710                 return false;
 711         }
 712
 713         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 714         clock = adjusted_mode->crtc_clock;
 715         htotal = adjusted_mode->crtc_htotal;
 716         hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
 717         pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
 718
 719         /* Use the small buffer method to calculate plane watermark */
 720         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
 721         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
 722         if (tlb_miss > 0)
 723                 entries += tlb_miss;
 724         entries = DIV_ROUND_UP(entries, display->cacheline_size);
 725         *plane_wm = entries + display->guard_size;
 726         if (*plane_wm > (int)display->max_wm)
 727                 *plane_wm = display->max_wm;
 728
 729         /* Use the large buffer method to calculate cursor watermark */
 730         line_time_us = max(htotal * 1000 / clock, 1);
 731         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
 732         entries = line_count * crtc->cursor->state->crtc_w * pixel_size;
 733         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
 734         if (tlb_miss > 0)
 735                 entries += tlb_miss;
 736         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 737         *cursor_wm = entries + cursor->guard_size;
 738         if (*cursor_wm > (int)cursor->max_wm)
 739                 *cursor_wm = (int)cursor->max_wm;
 740
 741         return true;
 742 }
 743
 744 /*
 745  * Check the wm result.
 746  *
 747  * If any calculated watermark values is larger than the maximum value that
 748  * can be programmed into the associated watermark register, that watermark
 749  * must be disabled.
 750  */
 751 static bool g4x_check_srwm(struct drm_device *dev,
 752                            int display_wm, int cursor_wm,
 753                            const struct intel_watermark_params *display,
 754                            const struct intel_watermark_params *cursor)
 755 {
 756         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
 757                       display_wm, cursor_wm);
 758
 759         if (display_wm > display->max_wm) {
 760                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
 761                               display_wm, display->max_wm);
 762                 return false;
 763         }
 764
 765         if (cursor_wm > cursor->max_wm) {
 766                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
 767                               cursor_wm, cursor->max_wm);
 768                 return false;
 769         }
 770
 771         if (!(display_wm || cursor_wm)) {
 772                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
 773                 return false;
 774         }
 775
 776         return true;
 777 }
 778
 779 static bool g4x_compute_srwm(struct drm_device *dev,
 780                              int plane,
 781                              int latency_ns,
 782                              const struct intel_watermark_params *display,
 783                              const struct intel_watermark_params *cursor,
 784                              int *display_wm, int *cursor_wm)
 785 {
 786         struct drm_crtc *crtc;
 787         const struct drm_display_mode *adjusted_mode;
 788         int hdisplay, htotal, pixel_size, clock;
 789         unsigned long line_time_us;
 790         int line_count, line_size;
 791         int small, large;
 792         int entries;
 793
 794         if (!latency_ns) {
 795                 *display_wm = *cursor_wm = 0;
 796                 return false;
 797         }
 798
 799         crtc = intel_get_crtc_for_plane(dev, plane);
 800         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 801         clock = adjusted_mode->crtc_clock;
 802         htotal = adjusted_mode->crtc_htotal;
 803         hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
 804         pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
 805
 806         line_time_us = max(htotal * 1000 / clock, 1);
 807         line_count = (latency_ns / line_time_us + 1000) / 1000;
 808         line_size = hdisplay * pixel_size;
 809
 810         /* Use the minimum of the small and large buffer method for primary */
 811         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
 812         large = line_count * line_size;
 813
 814         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
 815         *display_wm = entries + display->guard_size;
 816
 817         /* calculate the self-refresh watermark for display cursor */
 818         entries = line_count * pixel_size * crtc->cursor->state->crtc_w;
 819         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 820         *cursor_wm = entries + cursor->guard_size;
 821
 822         return g4x_check_srwm(dev,
 823                               *display_wm, *cursor_wm,
 824                               display, cursor);
 825 }
 826
 827 #define FW_WM_VLV(value, plane) \
 828         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
 829
 830 static void vlv_write_wm_values(struct intel_crtc *crtc,
 831                                 const struct vlv_wm_values *wm)
 832 {
 833         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 834         enum pipe pipe = crtc->pipe;
 835
 836         I915_WRITE(VLV_DDL(pipe),
 837                    (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
 838                    (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
 839                    (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
 840                    (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
 841
 842         I915_WRITE(DSPFW1,
 843                    FW_WM(wm->sr.plane, SR) |
 844                    FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
 845                    FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
 846                    FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
 847         I915_WRITE(DSPFW2,
 848                    FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
 849                    FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
 850                    FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
 851         I915_WRITE(DSPFW3,
 852                    FW_WM(wm->sr.cursor, CURSOR_SR));
 853
 854         if (IS_CHERRYVIEW(dev_priv)) {
 855                 I915_WRITE(DSPFW7_CHV,
 856                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
 857                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
 858                 I915_WRITE(DSPFW8_CHV,
 859                            FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
 860                            FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
 861                 I915_WRITE(DSPFW9_CHV,
 862                            FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
 863                            FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
 864                 I915_WRITE(DSPHOWM,
 865                            FW_WM(wm->sr.plane >> 9, SR_HI) |
 866                            FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
 867                            FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
 868                            FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
 869                            FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
 870                            FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
 871                            FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
 872                            FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
 873                            FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
 874                            FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
 875         } else {
 876                 I915_WRITE(DSPFW7,
 877                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
 878                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
 879                 I915_WRITE(DSPHOWM,
 880                            FW_WM(wm->sr.plane >> 9, SR_HI) |
 881                            FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
 882                            FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
 883                            FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
 884                            FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
 885                            FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
 886                            FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
 887         }
 888
 889         /* zero (unused) WM1 watermarks */
 890         I915_WRITE(DSPFW4, 0);
 891         I915_WRITE(DSPFW5, 0);
 892         I915_WRITE(DSPFW6, 0);
 893         I915_WRITE(DSPHOWM1, 0);
 894
 895         POSTING_READ(DSPFW1);
 896 }
 897
 898 #undef FW_WM_VLV
 899
 900 enum vlv_wm_level {
 901         VLV_WM_LEVEL_PM2,
 902         VLV_WM_LEVEL_PM5,
 903         VLV_WM_LEVEL_DDR_DVFS,
 904 };
 905
 906 /* latency must be in 0.1us units. */
 907 static unsigned int vlv_wm_method2(unsigned int pixel_rate,
 908                                    unsigned int pipe_htotal,
 909                                    unsigned int horiz_pixels,
 910                                    unsigned int bytes_per_pixel,
 911                                    unsigned int latency)
 912 {
 913         unsigned int ret;
 914
 915         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
 916         ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
 917         ret = DIV_ROUND_UP(ret, 64);
 918
 919         return ret;
 920 }
 921
 922 static void vlv_setup_wm_latency(struct drm_device *dev)
 923 {
 924         struct drm_i915_private *dev_priv = dev->dev_private;
 925
 926         /* all latencies in usec */
 927         dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
 928
 929         dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
 930
 931         if (IS_CHERRYVIEW(dev_priv)) {
 932                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
 933                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
 934
 935                 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
 936         }
 937 }
 938
 939 static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
 940                                      struct intel_crtc *crtc,
 941                                      const struct intel_plane_state *state,
 942                                      int level)
 943 {
 944         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 945         int clock, htotal, pixel_size, width, wm;
 946
 947         if (dev_priv->wm.pri_latency[level] == 0)
 948                 return USHRT_MAX;
 949
 950         if (!state->visible)
 951                 return 0;
 952
 953         pixel_size = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
 954         clock = crtc->config->base.adjusted_mode.crtc_clock;
 955         htotal = crtc->config->base.adjusted_mode.crtc_htotal;
 956         width = crtc->config->pipe_src_w;
 957         if (WARN_ON(htotal == 0))
 958                 htotal = 1;
 959
 960         if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
 961                 /*
 962                  * FIXME the formula gives values that are
 963                  * too big for the cursor FIFO, and hence we
 964                  * would never be able to use cursors. For
 965                  * now just hardcode the watermark.
 966                  */
 967                 wm = 63;
 968         } else {
 969                 wm = vlv_wm_method2(clock, htotal, width, pixel_size,
 970                                     dev_priv->wm.pri_latency[level] * 10);
 971         }
 972
 973         return min_t(int, wm, USHRT_MAX);
 974 }
 975
 976 static void vlv_compute_fifo(struct intel_crtc *crtc)
 977 {
 978         struct drm_device *dev = crtc->base.dev;
 979         struct vlv_wm_state *wm_state = &crtc->wm_state;
 980         struct intel_plane *plane;
 981         unsigned int total_rate = 0;
 982         const int fifo_size = 512 - 1;
 983         int fifo_extra, fifo_left = fifo_size;
 984
 985         for_each_intel_plane_on_crtc(dev, crtc, plane) {
 986                 struct intel_plane_state *state =
 987                         to_intel_plane_state(plane->base.state);
 988
 989                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
 990                         continue;
 991
 992                 if (state->visible) {
 993                         wm_state->num_active_planes++;
 994                         total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
 995                 }
 996         }
 997
 998         for_each_intel_plane_on_crtc(dev, crtc, plane) {
 999                 struct intel_plane_state *state =
1000                         to_intel_plane_state(plane->base.state);
1001                 unsigned int rate;
1002
1003                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1004                         plane->wm.fifo_size = 63;
1005                         continue;
1006                 }
1007
1008                 if (!state->visible) {
1009                         plane->wm.fifo_size = 0;
1010                         continue;
1011                 }
1012
1013                 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1014                 plane->wm.fifo_size = fifo_size * rate / total_rate;
1015                 fifo_left -= plane->wm.fifo_size;
1016         }
1017
1018         fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1019
1020         /* spread the remainder evenly */
1021         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1022                 int plane_extra;
1023
1024                 if (fifo_left == 0)
1025                         break;
1026
1027                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1028                         continue;
1029
1030                 /* give it all to the first plane if none are active */
1031                 if (plane->wm.fifo_size == 0 &&
1032                     wm_state->num_active_planes)
1033                         continue;
1034
1035                 plane_extra = min(fifo_extra, fifo_left);
1036                 plane->wm.fifo_size += plane_extra;
1037                 fifo_left -= plane_extra;
1038         }
1039
1040         WARN_ON(fifo_left != 0);
1041 }
1042
1043 static void vlv_invert_wms(struct intel_crtc *crtc)
1044 {
1045         struct vlv_wm_state *wm_state = &crtc->wm_state;
1046         int level;
1047
1048         for (level = 0; level < wm_state->num_levels; level++) {
1049                 struct drm_device *dev = crtc->base.dev;
1050                 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1051                 struct intel_plane *plane;
1052
1053                 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1054                 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1055
1056                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1057                         switch (plane->base.type) {
1058                                 int sprite;
1059                         case DRM_PLANE_TYPE_CURSOR:
1060                                 wm_state->wm[level].cursor = plane->wm.fifo_size -
1061                                         wm_state->wm[level].cursor;
1062                                 break;
1063                         case DRM_PLANE_TYPE_PRIMARY:
1064                                 wm_state->wm[level].primary = plane->wm.fifo_size -
1065                                         wm_state->wm[level].primary;
1066                                 break;
1067                         case DRM_PLANE_TYPE_OVERLAY:
1068                                 sprite = plane->plane;
1069                                 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1070                                         wm_state->wm[level].sprite[sprite];
1071                                 break;
1072                         }
1073                 }
1074         }
1075 }
1076
1077 static void vlv_compute_wm(struct intel_crtc *crtc)
1078 {
1079         struct drm_device *dev = crtc->base.dev;
1080         struct vlv_wm_state *wm_state = &crtc->wm_state;
1081         struct intel_plane *plane;
1082         int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1083         int level;
1084
1085         memset(wm_state, 0, sizeof(*wm_state));
1086
1087         wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
1088         wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
1089
1090         wm_state->num_active_planes = 0;
1091
1092         vlv_compute_fifo(crtc);
1093
1094         if (wm_state->num_active_planes != 1)
1095                 wm_state->cxsr = false;
1096
1097         if (wm_state->cxsr) {
1098                 for (level = 0; level < wm_state->num_levels; level++) {
1099                         wm_state->sr[level].plane = sr_fifo_size;
1100                         wm_state->sr[level].cursor = 63;
1101                 }
1102         }
1103
1104         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1105                 struct intel_plane_state *state =
1106                         to_intel_plane_state(plane->base.state);
1107
1108                 if (!state->visible)
1109                         continue;
1110
1111                 /* normal watermarks */
1112                 for (level = 0; level < wm_state->num_levels; level++) {
1113                         int wm = vlv_compute_wm_level(plane, crtc, state, level);
1114                         int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1115
1116                         /* hack */
1117                         if (WARN_ON(level == 0 && wm > max_wm))
1118                                 wm = max_wm;
1119
1120                         if (wm > plane->wm.fifo_size)
1121                                 break;
1122
1123                         switch (plane->base.type) {
1124                                 int sprite;
1125                         case DRM_PLANE_TYPE_CURSOR:
1126                                 wm_state->wm[level].cursor = wm;
1127                                 break;
1128                         case DRM_PLANE_TYPE_PRIMARY:
1129                                 wm_state->wm[level].primary = wm;
1130                                 break;
1131                         case DRM_PLANE_TYPE_OVERLAY:
1132                                 sprite = plane->plane;
1133                                 wm_state->wm[level].sprite[sprite] = wm;
1134                                 break;
1135                         }
1136                 }
1137
1138                 wm_state->num_levels = level;
1139
1140                 if (!wm_state->cxsr)
1141                         continue;
1142
1143                 /* maxfifo watermarks */
1144                 switch (plane->base.type) {
1145                         int sprite, level;
1146                 case DRM_PLANE_TYPE_CURSOR:
1147                         for (level = 0; level < wm_state->num_levels; level++)
1148                                 wm_state->sr[level].cursor =
1149                                         wm_state->wm[level].cursor;
1150                         break;
1151                 case DRM_PLANE_TYPE_PRIMARY:
1152                         for (level = 0; level < wm_state->num_levels; level++)
1153                                 wm_state->sr[level].plane =
1154                                         min(wm_state->sr[level].plane,
1155                                             wm_state->wm[level].primary);
1156                         break;
1157                 case DRM_PLANE_TYPE_OVERLAY:
1158                         sprite = plane->plane;
1159                         for (level = 0; level < wm_state->num_levels; level++)
1160                                 wm_state->sr[level].plane =
1161                                         min(wm_state->sr[level].plane,
1162                                             wm_state->wm[level].sprite[sprite]);
1163                         break;
1164                 }
1165         }
1166
1167         /* clear any (partially) filled invalid levels */
1168         for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
1169                 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1170                 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1171         }
1172
1173         vlv_invert_wms(crtc);
1174 }
1175
1176 #define VLV_FIFO(plane, value) \
1177         (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1178
1179 static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1180 {
1181         struct drm_device *dev = crtc->base.dev;
1182         struct drm_i915_private *dev_priv = to_i915(dev);
1183         struct intel_plane *plane;
1184         int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1185
1186         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1187                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1188                         WARN_ON(plane->wm.fifo_size != 63);
1189                         continue;
1190                 }
1191
1192                 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1193                         sprite0_start = plane->wm.fifo_size;
1194                 else if (plane->plane == 0)
1195                         sprite1_start = sprite0_start + plane->wm.fifo_size;
1196                 else
1197                         fifo_size = sprite1_start + plane->wm.fifo_size;
1198         }
1199
1200         WARN_ON(fifo_size != 512 - 1);
1201
1202         DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1203                       pipe_name(crtc->pipe), sprite0_start,
1204                       sprite1_start, fifo_size);
1205
1206         switch (crtc->pipe) {
1207                 uint32_t dsparb, dsparb2, dsparb3;
1208         case PIPE_A:
1209                 dsparb = I915_READ(DSPARB);
1210                 dsparb2 = I915_READ(DSPARB2);
1211
1212                 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1213                             VLV_FIFO(SPRITEB, 0xff));
1214                 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1215                            VLV_FIFO(SPRITEB, sprite1_start));
1216
1217                 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1218                              VLV_FIFO(SPRITEB_HI, 0x1));
1219                 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1220                            VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1221
1222                 I915_WRITE(DSPARB, dsparb);
1223                 I915_WRITE(DSPARB2, dsparb2);
1224                 break;
1225         case PIPE_B:
1226                 dsparb = I915_READ(DSPARB);
1227                 dsparb2 = I915_READ(DSPARB2);
1228
1229                 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1230                             VLV_FIFO(SPRITED, 0xff));
1231                 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1232                            VLV_FIFO(SPRITED, sprite1_start));
1233
1234                 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1235                              VLV_FIFO(SPRITED_HI, 0xff));
1236                 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1237                            VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1238
1239                 I915_WRITE(DSPARB, dsparb);
1240                 I915_WRITE(DSPARB2, dsparb2);
1241                 break;
1242         case PIPE_C:
1243                 dsparb3 = I915_READ(DSPARB3);
1244                 dsparb2 = I915_READ(DSPARB2);
1245
1246                 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1247                              VLV_FIFO(SPRITEF, 0xff));
1248                 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1249                             VLV_FIFO(SPRITEF, sprite1_start));
1250
1251                 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1252                              VLV_FIFO(SPRITEF_HI, 0xff));
1253                 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1254                            VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1255
1256                 I915_WRITE(DSPARB3, dsparb3);
1257                 I915_WRITE(DSPARB2, dsparb2);
1258                 break;
1259         default:
1260                 break;
1261         }
1262 }
1263
1264 #undef VLV_FIFO
1265
1266 static void vlv_merge_wm(struct drm_device *dev,
1267                          struct vlv_wm_values *wm)
1268 {
1269         struct intel_crtc *crtc;
1270         int num_active_crtcs = 0;
1271
1272         wm->level = to_i915(dev)->wm.max_level;
1273         wm->cxsr = true;
1274
1275         for_each_intel_crtc(dev, crtc) {
1276                 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1277
1278                 if (!crtc->active)
1279                         continue;
1280
1281                 if (!wm_state->cxsr)
1282                         wm->cxsr = false;
1283
1284                 num_active_crtcs++;
1285                 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1286         }
1287
1288         if (num_active_crtcs != 1)
1289                 wm->cxsr = false;
1290
1291         if (num_active_crtcs > 1)
1292                 wm->level = VLV_WM_LEVEL_PM2;
1293
1294         for_each_intel_crtc(dev, crtc) {
1295                 struct vlv_wm_state *wm_state = &crtc->wm_state;
1296                 enum pipe pipe = crtc->pipe;
1297
1298                 if (!crtc->active)
1299                         continue;
1300
1301                 wm->pipe[pipe] = wm_state->wm[wm->level];
1302                 if (wm->cxsr)
1303                         wm->sr = wm_state->sr[wm->level];
1304
1305                 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1306                 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1307                 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1308                 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1309         }
1310 }
1311
1312 static void vlv_update_wm(struct drm_crtc *crtc)
1313 {
1314         struct drm_device *dev = crtc->dev;
1315         struct drm_i915_private *dev_priv = dev->dev_private;
1316         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1317         enum pipe pipe = intel_crtc->pipe;
1318         struct vlv_wm_values wm = {};
1319
1320         vlv_compute_wm(intel_crtc);
1321         vlv_merge_wm(dev, &wm);
1322
1323         if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1324                 /* FIXME should be part of crtc atomic commit */
1325                 vlv_pipe_set_fifo_size(intel_crtc);
1326                 return;
1327         }
1328
1329         if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1330             dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1331                 chv_set_memory_dvfs(dev_priv, false);
1332
1333         if (wm.level < VLV_WM_LEVEL_PM5 &&
1334             dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1335                 chv_set_memory_pm5(dev_priv, false);
1336
1337         if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
1338                 intel_set_memory_cxsr(dev_priv, false);
1339
1340         /* FIXME should be part of crtc atomic commit */
1341         vlv_pipe_set_fifo_size(intel_crtc);
1342
1343         vlv_write_wm_values(intel_crtc, &wm);
1344
1345         DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1346                       "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1347                       pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1348                       wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1349                       wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1350
1351         if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
1352                 intel_set_memory_cxsr(dev_priv, true);
1353
1354         if (wm.level >= VLV_WM_LEVEL_PM5 &&
1355             dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1356                 chv_set_memory_pm5(dev_priv, true);
1357
1358         if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1359             dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1360                 chv_set_memory_dvfs(dev_priv, true);
1361
1362         dev_priv->wm.vlv = wm;
1363 }
1364
1365 #define single_plane_enabled(mask) is_power_of_2(mask)
1366
1367 static void g4x_update_wm(struct drm_crtc *crtc)
1368 {
1369         struct drm_device *dev = crtc->dev;
1370         static const int sr_latency_ns = 12000;
1371         struct drm_i915_private *dev_priv = dev->dev_private;
1372         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1373         int plane_sr, cursor_sr;
1374         unsigned int enabled = 0;
1375         bool cxsr_enabled;
1376
1377         if (g4x_compute_wm0(dev, PIPE_A,
1378                             &g4x_wm_info, pessimal_latency_ns,
1379                             &g4x_cursor_wm_info, pessimal_latency_ns,
1380                             &planea_wm, &cursora_wm))
1381                 enabled |= 1 << PIPE_A;
1382
1383         if (g4x_compute_wm0(dev, PIPE_B,
1384                             &g4x_wm_info, pessimal_latency_ns,
1385                             &g4x_cursor_wm_info, pessimal_latency_ns,
1386                             &planeb_wm, &cursorb_wm))
1387                 enabled |= 1 << PIPE_B;
1388
1389         if (single_plane_enabled(enabled) &&
1390             g4x_compute_srwm(dev, ffs(enabled) - 1,
1391                              sr_latency_ns,
1392                              &g4x_wm_info,
1393                              &g4x_cursor_wm_info,
1394                              &plane_sr, &cursor_sr)) {
1395                 cxsr_enabled = true;
1396         } else {
1397                 cxsr_enabled = false;
1398                 intel_set_memory_cxsr(dev_priv, false);
1399                 plane_sr = cursor_sr = 0;
1400         }
1401
1402         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1403                       "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1404                       planea_wm, cursora_wm,
1405                       planeb_wm, cursorb_wm,
1406                       plane_sr, cursor_sr);
1407
1408         I915_WRITE(DSPFW1,
1409                    FW_WM(plane_sr, SR) |
1410                    FW_WM(cursorb_wm, CURSORB) |
1411                    FW_WM(planeb_wm, PLANEB) |
1412                    FW_WM(planea_wm, PLANEA));
1413         I915_WRITE(DSPFW2,
1414                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1415                    FW_WM(cursora_wm, CURSORA));
1416         /* HPLL off in SR has some issues on G4x... disable it */
1417         I915_WRITE(DSPFW3,
1418                    (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1419                    FW_WM(cursor_sr, CURSOR_SR));
1420
1421         if (cxsr_enabled)
1422                 intel_set_memory_cxsr(dev_priv, true);
1423 }
1424
1425 static void i965_update_wm(struct drm_crtc *unused_crtc)
1426 {
1427         struct drm_device *dev = unused_crtc->dev;
1428         struct drm_i915_private *dev_priv = dev->dev_private;
1429         struct drm_crtc *crtc;
1430         int srwm = 1;
1431         int cursor_sr = 16;
1432         bool cxsr_enabled;
1433
1434         /* Calc sr entries for one plane configs */
1435         crtc = single_enabled_crtc(dev);
1436         if (crtc) {
1437                 /* self-refresh has much higher latency */
1438                 static const int sr_latency_ns = 12000;
1439                 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1440                 int clock = adjusted_mode->crtc_clock;
1441                 int htotal = adjusted_mode->crtc_htotal;
1442                 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
1443                 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
1444                 unsigned long line_time_us;
1445                 int entries;
1446
1447                 line_time_us = max(htotal * 1000 / clock, 1);
1448
1449                 /* Use ns/us then divide to preserve precision */
1450                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1451                         pixel_size * hdisplay;
1452                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1453                 srwm = I965_FIFO_SIZE - entries;
1454                 if (srwm < 0)
1455                         srwm = 1;
1456                 srwm &= 0x1ff;
1457                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1458                               entries, srwm);
1459
1460                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1461                         pixel_size * crtc->cursor->state->crtc_w;
1462                 entries = DIV_ROUND_UP(entries,
1463                                           i965_cursor_wm_info.cacheline_size);
1464                 cursor_sr = i965_cursor_wm_info.fifo_size -
1465                         (entries + i965_cursor_wm_info.guard_size);
1466
1467                 if (cursor_sr > i965_cursor_wm_info.max_wm)
1468                         cursor_sr = i965_cursor_wm_info.max_wm;
1469
1470                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1471                               "cursor %d\n", srwm, cursor_sr);
1472
1473                 cxsr_enabled = true;
1474         } else {
1475                 cxsr_enabled = false;
1476                 /* Turn off self refresh if both pipes are enabled */
1477                 intel_set_memory_cxsr(dev_priv, false);
1478         }
1479
1480         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1481                       srwm);
1482
1483         /* 965 has limitations... */
1484         I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1485                    FW_WM(8, CURSORB) |
1486                    FW_WM(8, PLANEB) |
1487                    FW_WM(8, PLANEA));
1488         I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1489                    FW_WM(8, PLANEC_OLD));
1490         /* update cursor SR watermark */
1491         I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
1492
1493         if (cxsr_enabled)
1494                 intel_set_memory_cxsr(dev_priv, true);
1495 }
1496
1497 #undef FW_WM
1498
1499 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1500 {
1501         struct drm_device *dev = unused_crtc->dev;
1502         struct drm_i915_private *dev_priv = dev->dev_private;
1503         const struct intel_watermark_params *wm_info;
1504         uint32_t fwater_lo;
1505         uint32_t fwater_hi;
1506         int cwm, srwm = 1;
1507         int fifo_size;
1508         int planea_wm, planeb_wm;
1509         struct drm_crtc *crtc, *enabled = NULL;
1510
1511         if (IS_I945GM(dev))
1512                 wm_info = &i945_wm_info;
1513         else if (!IS_GEN2(dev))
1514                 wm_info = &i915_wm_info;
1515         else
1516                 wm_info = &i830_a_wm_info;
1517
1518         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1519         crtc = intel_get_crtc_for_plane(dev, 0);
1520         if (intel_crtc_active(crtc)) {
1521                 const struct drm_display_mode *adjusted_mode;
1522                 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
1523                 if (IS_GEN2(dev))
1524                         cpp = 4;
1525
1526                 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1527                 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1528                                                wm_info, fifo_size, cpp,
1529                                                pessimal_latency_ns);
1530                 enabled = crtc;
1531         } else {
1532                 planea_wm = fifo_size - wm_info->guard_size;
1533                 if (planea_wm > (long)wm_info->max_wm)
1534                         planea_wm = wm_info->max_wm;
1535         }
1536
1537         if (IS_GEN2(dev))
1538                 wm_info = &i830_bc_wm_info;
1539
1540         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1541         crtc = intel_get_crtc_for_plane(dev, 1);
1542         if (intel_crtc_active(crtc)) {
1543                 const struct drm_display_mode *adjusted_mode;
1544                 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
1545                 if (IS_GEN2(dev))
1546                         cpp = 4;
1547
1548                 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1549                 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1550                                                wm_info, fifo_size, cpp,
1551                                                pessimal_latency_ns);
1552                 if (enabled == NULL)
1553                         enabled = crtc;
1554                 else
1555                         enabled = NULL;
1556         } else {
1557                 planeb_wm = fifo_size - wm_info->guard_size;
1558                 if (planeb_wm > (long)wm_info->max_wm)
1559                         planeb_wm = wm_info->max_wm;
1560         }
1561
1562         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1563
1564         if (IS_I915GM(dev) && enabled) {
1565                 struct drm_i915_gem_object *obj;
1566
1567                 obj = intel_fb_obj(enabled->primary->state->fb);
1568
1569                 /* self-refresh seems busted with untiled */
1570                 if (obj->tiling_mode == I915_TILING_NONE)
1571                         enabled = NULL;
1572         }
1573
1574         /*
1575          * Overlay gets an aggressive default since video jitter is bad.
1576          */
1577         cwm = 2;
1578
1579         /* Play safe and disable self-refresh before adjusting watermarks. */
1580         intel_set_memory_cxsr(dev_priv, false);
1581
1582         /* Calc sr entries for one plane configs */
1583         if (HAS_FW_BLC(dev) && enabled) {
1584                 /* self-refresh has much higher latency */
1585                 static const int sr_latency_ns = 6000;
1586                 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode;
1587                 int clock = adjusted_mode->crtc_clock;
1588                 int htotal = adjusted_mode->crtc_htotal;
1589                 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
1590                 int pixel_size = enabled->primary->state->fb->bits_per_pixel / 8;
1591                 unsigned long line_time_us;
1592                 int entries;
1593
1594                 line_time_us = max(htotal * 1000 / clock, 1);
1595
1596                 /* Use ns/us then divide to preserve precision */
1597                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1598                         pixel_size * hdisplay;
1599                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1600                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1601                 srwm = wm_info->fifo_size - entries;
1602                 if (srwm < 0)
1603                         srwm = 1;
1604
1605                 if (IS_I945G(dev) || IS_I945GM(dev))
1606                         I915_WRITE(FW_BLC_SELF,
1607                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1608                 else if (IS_I915GM(dev))
1609                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1610         }
1611
1612         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1613                       planea_wm, planeb_wm, cwm, srwm);
1614
1615         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1616         fwater_hi = (cwm & 0x1f);
1617
1618         /* Set request length to 8 cachelines per fetch */
1619         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1620         fwater_hi = fwater_hi | (1 << 8);
1621
1622         I915_WRITE(FW_BLC, fwater_lo);
1623         I915_WRITE(FW_BLC2, fwater_hi);
1624
1625         if (enabled)
1626                 intel_set_memory_cxsr(dev_priv, true);
1627 }
1628
1629 static void i845_update_wm(struct drm_crtc *unused_crtc)
1630 {
1631         struct drm_device *dev = unused_crtc->dev;
1632         struct drm_i915_private *dev_priv = dev->dev_private;
1633         struct drm_crtc *crtc;
1634         const struct drm_display_mode *adjusted_mode;
1635         uint32_t fwater_lo;
1636         int planea_wm;
1637
1638         crtc = single_enabled_crtc(dev);
1639         if (crtc == NULL)
1640                 return;
1641
1642         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1643         planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1644                                        &i845_wm_info,
1645                                        dev_priv->display.get_fifo_size(dev, 0),
1646                                        4, pessimal_latency_ns);
1647         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1648         fwater_lo |= (3<<8) | planea_wm;
1649
1650         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1651
1652         I915_WRITE(FW_BLC, fwater_lo);
1653 }
1654
1655 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
1656 {
1657         uint32_t pixel_rate;
1658
1659         pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
1660
1661         /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1662          * adjust the pixel_rate here. */
1663
1664         if (pipe_config->pch_pfit.enabled) {
1665                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1666                 uint32_t pfit_size = pipe_config->pch_pfit.size;
1667
1668                 pipe_w = pipe_config->pipe_src_w;
1669                 pipe_h = pipe_config->pipe_src_h;
1670
1671                 pfit_w = (pfit_size >> 16) & 0xFFFF;
1672                 pfit_h = pfit_size & 0xFFFF;
1673                 if (pipe_w < pfit_w)
1674                         pipe_w = pfit_w;
1675                 if (pipe_h < pfit_h)
1676                         pipe_h = pfit_h;
1677
1678                 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1679                                      pfit_w * pfit_h);
1680         }
1681
1682         return pixel_rate;
1683 }
1684
1685 /* latency must be in 0.1us units. */
1686 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
1687                                uint32_t latency)
1688 {
1689         uint64_t ret;
1690
1691         if (WARN(latency == 0, "Latency value missing\n"))
1692                 return UINT_MAX;
1693
1694         ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1695         ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1696
1697         return ret;
1698 }
1699
1700 /* latency must be in 0.1us units. */
1701 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1702                                uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1703                                uint32_t latency)
1704 {
1705         uint32_t ret;
1706
1707         if (WARN(latency == 0, "Latency value missing\n"))
1708                 return UINT_MAX;
1709
1710         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1711         ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1712         ret = DIV_ROUND_UP(ret, 64) + 2;
1713         return ret;
1714 }
1715
1716 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1717                            uint8_t bytes_per_pixel)
1718 {
1719         return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1720 }
1721
1722 struct skl_pipe_wm_parameters {
1723         bool active;
1724         uint32_t pipe_htotal;
1725         uint32_t pixel_rate; /* in KHz */
1726         struct intel_plane_wm_parameters plane[I915_MAX_PLANES];
1727 };
1728
1729 struct ilk_wm_maximums {
1730         uint16_t pri;
1731         uint16_t spr;
1732         uint16_t cur;
1733         uint16_t fbc;
1734 };
1735
1736 /* used in computing the new watermarks state */
1737 struct intel_wm_config {
1738         unsigned int num_pipes_active;
1739         bool sprites_enabled;
1740         bool sprites_scaled;
1741 };
1742
1743 /*
1744  * For both WM_PIPE and WM_LP.
1745  * mem_value must be in 0.1us units.
1746  */
1747 static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
1748                                    const struct intel_plane_state *pstate,
1749                                    uint32_t mem_value,
1750                                    bool is_lp)
1751 {
1752         int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
1753         uint32_t method1, method2;
1754
1755         if (!cstate->base.active || !pstate->visible)
1756                 return 0;
1757
1758         method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), bpp, mem_value);
1759
1760         if (!is_lp)
1761                 return method1;
1762
1763         method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1764                                  cstate->base.adjusted_mode.crtc_htotal,
1765                                  drm_rect_width(&pstate->dst),
1766                                  bpp,
1767                                  mem_value);
1768
1769         return min(method1, method2);
1770 }
1771
1772 /*
1773  * For both WM_PIPE and WM_LP.
1774  * mem_value must be in 0.1us units.
1775  */
1776 static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
1777                                    const struct intel_plane_state *pstate,
1778                                    uint32_t mem_value)
1779 {
1780         int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
1781         uint32_t method1, method2;
1782
1783         if (!cstate->base.active || !pstate->visible)
1784                 return 0;
1785
1786         method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), bpp, mem_value);
1787         method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1788                                  cstate->base.adjusted_mode.crtc_htotal,
1789                                  drm_rect_width(&pstate->dst),
1790                                  bpp,
1791                                  mem_value);
1792         return min(method1, method2);
1793 }
1794
1795 /*
1796  * For both WM_PIPE and WM_LP.
1797  * mem_value must be in 0.1us units.
1798  */
1799 static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
1800                                    const struct intel_plane_state *pstate,
1801                                    uint32_t mem_value)
1802 {
1803         /*
1804          * We treat the cursor plane as always-on for the purposes of watermark
1805          * calculation.  Until we have two-stage watermark programming merged,
1806          * this is necessary to avoid flickering.
1807          */
1808         int cpp = 4;
1809         int width = pstate->visible ? pstate->base.crtc_w : 64;
1810
1811         if (!cstate->base.active)
1812                 return 0;
1813
1814         return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1815                               cstate->base.adjusted_mode.crtc_htotal,
1816                               width, cpp, mem_value);
1817 }
1818
1819 /* Only for WM_LP. */
1820 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
1821                                    const struct intel_plane_state *pstate,
1822                                    uint32_t pri_val)
1823 {
1824         int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
1825
1826         if (!cstate->base.active || !pstate->visible)
1827                 return 0;
1828
1829         return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->dst), bpp);
1830 }
1831
1832 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1833 {
1834         if (INTEL_INFO(dev)->gen >= 8)
1835                 return 3072;
1836         else if (INTEL_INFO(dev)->gen >= 7)
1837                 return 768;
1838         else
1839                 return 512;
1840 }
1841
1842 static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1843                                          int level, bool is_sprite)
1844 {
1845         if (INTEL_INFO(dev)->gen >= 8)
1846                 /* BDW primary/sprite plane watermarks */
1847                 return level == 0 ? 255 : 2047;
1848         else if (INTEL_INFO(dev)->gen >= 7)
1849                 /* IVB/HSW primary/sprite plane watermarks */
1850                 return level == 0 ? 127 : 1023;
1851         else if (!is_sprite)
1852                 /* ILK/SNB primary plane watermarks */
1853                 return level == 0 ? 127 : 511;
1854         else
1855                 /* ILK/SNB sprite plane watermarks */
1856                 return level == 0 ? 63 : 255;
1857 }
1858
1859 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1860                                           int level)
1861 {
1862         if (INTEL_INFO(dev)->gen >= 7)
1863                 return level == 0 ? 63 : 255;
1864         else
1865                 return level == 0 ? 31 : 63;
1866 }
1867
1868 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1869 {
1870         if (INTEL_INFO(dev)->gen >= 8)
1871                 return 31;
1872         else
1873                 return 15;
1874 }
1875
1876 /* Calculate the maximum primary/sprite plane watermark */
1877 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1878                                      int level,
1879                                      const struct intel_wm_config *config,
1880                                      enum intel_ddb_partitioning ddb_partitioning,
1881                                      bool is_sprite)
1882 {
1883         unsigned int fifo_size = ilk_display_fifo_size(dev);
1884
1885         /* if sprites aren't enabled, sprites get nothing */
1886         if (is_sprite && !config->sprites_enabled)
1887                 return 0;
1888
1889         /* HSW allows LP1+ watermarks even with multiple pipes */
1890         if (level == 0 || config->num_pipes_active > 1) {
1891                 fifo_size /= INTEL_INFO(dev)->num_pipes;
1892
1893                 /*
1894                  * For some reason the non self refresh
1895                  * FIFO size is only half of the self
1896                  * refresh FIFO size on ILK/SNB.
1897                  */
1898                 if (INTEL_INFO(dev)->gen <= 6)
1899                         fifo_size /= 2;
1900         }
1901
1902         if (config->sprites_enabled) {
1903                 /* level 0 is always calculated with 1:1 split */
1904                 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1905                         if (is_sprite)
1906                                 fifo_size *= 5;
1907                         fifo_size /= 6;
1908                 } else {
1909                         fifo_size /= 2;
1910                 }
1911         }
1912
1913         /* clamp to max that the registers can hold */
1914         return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
1915 }
1916
1917 /* Calculate the maximum cursor plane watermark */
1918 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1919                                       int level,
1920                                       const struct intel_wm_config *config)
1921 {
1922         /* HSW LP1+ watermarks w/ multiple pipes */
1923         if (level > 0 && config->num_pipes_active > 1)
1924                 return 64;
1925
1926         /* otherwise just report max that registers can hold */
1927         return ilk_cursor_wm_reg_max(dev, level);
1928 }
1929
1930 static void ilk_compute_wm_maximums(const struct drm_device *dev,
1931                                     int level,
1932                                     const struct intel_wm_config *config,
1933                                     enum intel_ddb_partitioning ddb_partitioning,
1934                                     struct ilk_wm_maximums *max)
1935 {
1936         max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1937         max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1938         max->cur = ilk_cursor_wm_max(dev, level, config);
1939         max->fbc = ilk_fbc_wm_reg_max(dev);
1940 }
1941
1942 static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1943                                         int level,
1944                                         struct ilk_wm_maximums *max)
1945 {
1946         max->pri = ilk_plane_wm_reg_max(dev, level, false);
1947         max->spr = ilk_plane_wm_reg_max(dev, level, true);
1948         max->cur = ilk_cursor_wm_reg_max(dev, level);
1949         max->fbc = ilk_fbc_wm_reg_max(dev);
1950 }
1951
1952 static bool ilk_validate_wm_level(int level,
1953                                   const struct ilk_wm_maximums *max,
1954                                   struct intel_wm_level *result)
1955 {
1956         bool ret;
1957
1958         /* already determined to be invalid? */
1959         if (!result->enable)
1960                 return false;
1961
1962         result->enable = result->pri_val <= max->pri &&
1963                          result->spr_val <= max->spr &&
1964                          result->cur_val <= max->cur;
1965
1966         ret = result->enable;
1967
1968         /*
1969          * HACK until we can pre-compute everything,
1970          * and thus fail gracefully if LP0 watermarks
1971          * are exceeded...
1972          */
1973         if (level == 0 && !result->enable) {
1974                 if (result->pri_val > max->pri)
1975                         DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1976                                       level, result->pri_val, max->pri);
1977                 if (result->spr_val > max->spr)
1978                         DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1979                                       level, result->spr_val, max->spr);
1980                 if (result->cur_val > max->cur)
1981                         DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1982                                       level, result->cur_val, max->cur);
1983
1984                 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1985                 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1986                 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1987                 result->enable = true;
1988         }
1989
1990         return ret;
1991 }
1992
1993 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
1994                                  const struct intel_crtc *intel_crtc,
1995                                  int level,
1996                                  struct intel_crtc_state *cstate,
1997                                  struct intel_wm_level *result)
1998 {
1999         struct intel_plane *intel_plane;
2000         uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2001         uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2002         uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2003
2004         /* WM1+ latency values stored in 0.5us units */
2005         if (level > 0) {
2006                 pri_latency *= 5;
2007                 spr_latency *= 5;
2008                 cur_latency *= 5;
2009         }
2010
2011         for_each_intel_plane_on_crtc(dev_priv->dev, intel_crtc, intel_plane) {
2012                 struct intel_plane_state *pstate =
2013                         to_intel_plane_state(intel_plane->base.state);
2014
2015                 switch (intel_plane->base.type) {
2016                 case DRM_PLANE_TYPE_PRIMARY:
2017                         result->pri_val = ilk_compute_pri_wm(cstate, pstate,
2018                                                              pri_latency,
2019                                                              level);
2020                         result->fbc_val = ilk_compute_fbc_wm(cstate, pstate,
2021                                                              result->pri_val);
2022                         break;
2023                 case DRM_PLANE_TYPE_OVERLAY:
2024                         result->spr_val = ilk_compute_spr_wm(cstate, pstate,
2025                                                              spr_latency);
2026                         break;
2027                 case DRM_PLANE_TYPE_CURSOR:
2028                         result->cur_val = ilk_compute_cur_wm(cstate, pstate,
2029                                                              cur_latency);
2030                         break;
2031                 }
2032         }
2033
2034         result->enable = true;
2035 }
2036
2037 static uint32_t
2038 hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
2039 {
2040         struct drm_i915_private *dev_priv = dev->dev_private;
2041         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2042         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
2043         u32 linetime, ips_linetime;
2044
2045         if (!intel_crtc->active)
2046                 return 0;
2047
2048         /* The WM are computed with base on how long it takes to fill a single
2049          * row at the given clock rate, multiplied by 8.
2050          * */
2051         linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2052                                      adjusted_mode->crtc_clock);
2053         ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2054                                          dev_priv->cdclk_freq);
2055
2056         return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2057                PIPE_WM_LINETIME_TIME(linetime);
2058 }
2059
2060 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
2061 {
2062         struct drm_i915_private *dev_priv = dev->dev_private;
2063
2064         if (IS_GEN9(dev)) {
2065                 uint32_t val;
2066                 int ret, i;
2067                 int level, max_level = ilk_wm_max_level(dev);
2068
2069                 /* read the first set of memory latencies[0:3] */
2070                 val = 0; /* data0 to be programmed to 0 for first set */
2071                 mutex_lock(&dev_priv->rps.hw_lock);
2072                 ret = sandybridge_pcode_read(dev_priv,
2073                                              GEN9_PCODE_READ_MEM_LATENCY,
2074                                              &val);
2075                 mutex_unlock(&dev_priv->rps.hw_lock);
2076
2077                 if (ret) {
2078                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2079                         return;
2080                 }
2081
2082                 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2083                 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2084                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2085                 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2086                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2087                 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2088                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2089
2090                 /* read the second set of memory latencies[4:7] */
2091                 val = 1; /* data0 to be programmed to 1 for second set */
2092                 mutex_lock(&dev_priv->rps.hw_lock);
2093                 ret = sandybridge_pcode_read(dev_priv,
2094                                              GEN9_PCODE_READ_MEM_LATENCY,
2095                                              &val);
2096                 mutex_unlock(&dev_priv->rps.hw_lock);
2097                 if (ret) {
2098                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2099                         return;
2100                 }
2101
2102                 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2103                 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2104                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2105                 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2106                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2107                 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2108                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2109
2110                 /*
2111                  * If a level n (n > 1) has a 0us latency, all levels m (m >= n)
2112                  * need to be disabled. We make sure to sanitize the values out
2113                  * of the punit to satisfy this requirement.
2114                  */
2115                 for (level = 1; level <= max_level; level++) {
2116                         if (wm[level] == 0) {
2117                                 for (i = level + 1; i <= max_level; i++)
2118                                         wm[i] = 0;
2119                                 break;
2120                         }
2121                 }
2122
2123                 /*
2124                  * WaWmMemoryReadLatency:skl
2125                  *
2126                  * punit doesn't take into account the read latency so we need
2127                  * to add 2us to the various latency levels we retrieve from the
2128                  * punit when level 0 response data us 0us.
2129                  */
2130                 if (wm[0] == 0) {
2131                         wm[0] += 2;
2132                         for (level = 1; level <= max_level; level++) {
2133                                 if (wm[level] == 0)
2134                                         break;
2135                                 wm[level] += 2;
2136                         }
2137                 }
2138
2139         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2140                 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2141
2142                 wm[0] = (sskpd >> 56) & 0xFF;
2143                 if (wm[0] == 0)
2144                         wm[0] = sskpd & 0xF;
2145                 wm[1] = (sskpd >> 4) & 0xFF;
2146                 wm[2] = (sskpd >> 12) & 0xFF;
2147                 wm[3] = (sskpd >> 20) & 0x1FF;
2148                 wm[4] = (sskpd >> 32) & 0x1FF;
2149         } else if (INTEL_INFO(dev)->gen >= 6) {
2150                 uint32_t sskpd = I915_READ(MCH_SSKPD);
2151
2152                 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2153                 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2154                 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2155                 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2156         } else if (INTEL_INFO(dev)->gen >= 5) {
2157                 uint32_t mltr = I915_READ(MLTR_ILK);
2158
2159                 /* ILK primary LP0 latency is 700 ns */
2160                 wm[0] = 7;
2161                 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2162                 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2163         }
2164 }
2165
2166 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2167 {
2168         /* ILK sprite LP0 latency is 1300 ns */
2169         if (INTEL_INFO(dev)->gen == 5)
2170                 wm[0] = 13;
2171 }
2172
2173 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2174 {
2175         /* ILK cursor LP0 latency is 1300 ns */
2176         if (INTEL_INFO(dev)->gen == 5)
2177                 wm[0] = 13;
2178
2179         /* WaDoubleCursorLP3Latency:ivb */
2180         if (IS_IVYBRIDGE(dev))
2181                 wm[3] *= 2;
2182 }
2183
2184 int ilk_wm_max_level(const struct drm_device *dev)
2185 {
2186         /* how many WM levels are we expecting */
2187         if (INTEL_INFO(dev)->gen >= 9)
2188                 return 7;
2189         else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2190                 return 4;
2191         else if (INTEL_INFO(dev)->gen >= 6)
2192                 return 3;
2193         else
2194                 return 2;
2195 }
2196
2197 static void intel_print_wm_latency(struct drm_device *dev,
2198                                    const char *name,
2199                                    const uint16_t wm[8])
2200 {
2201         int level, max_level = ilk_wm_max_level(dev);
2202
2203         for (level = 0; level <= max_level; level++) {
2204                 unsigned int latency = wm[level];
2205
2206                 if (latency == 0) {
2207                         DRM_ERROR("%s WM%d latency not provided\n",
2208                                   name, level);
2209                         continue;
2210                 }
2211
2212                 /*
2213                  * - latencies are in us on gen9.
2214                  * - before then, WM1+ latency values are in 0.5us units
2215                  */
2216                 if (IS_GEN9(dev))
2217                         latency *= 10;
2218                 else if (level > 0)
2219                         latency *= 5;
2220
2221                 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2222                               name, level, wm[level],
2223                               latency / 10, latency % 10);
2224         }
2225 }
2226
2227 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2228                                     uint16_t wm[5], uint16_t min)
2229 {
2230         int level, max_level = ilk_wm_max_level(dev_priv->dev);
2231
2232         if (wm[0] >= min)
2233                 return false;
2234
2235         wm[0] = max(wm[0], min);
2236         for (level = 1; level <= max_level; level++)
2237                 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2238
2239         return true;
2240 }
2241
2242 static void snb_wm_latency_quirk(struct drm_device *dev)
2243 {
2244         struct drm_i915_private *dev_priv = dev->dev_private;
2245         bool changed;
2246
2247         /*
2248          * The BIOS provided WM memory latency values are often
2249          * inadequate for high resolution displays. Adjust them.
2250          */
2251         changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2252                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2253                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2254
2255         if (!changed)
2256                 return;
2257
2258         DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2259         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2260         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2261         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2262 }
2263
2264 static void ilk_setup_wm_latency(struct drm_device *dev)
2265 {
2266         struct drm_i915_private *dev_priv = dev->dev_private;
2267
2268         intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2269
2270         memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2271                sizeof(dev_priv->wm.pri_latency));
2272         memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2273                sizeof(dev_priv->wm.pri_latency));
2274
2275         intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2276         intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2277
2278         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2279         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2280         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2281
2282         if (IS_GEN6(dev))
2283                 snb_wm_latency_quirk(dev);
2284 }
2285
2286 static void skl_setup_wm_latency(struct drm_device *dev)
2287 {
2288         struct drm_i915_private *dev_priv = dev->dev_private;
2289
2290         intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2291         intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2292 }
2293
2294 static void ilk_compute_wm_config(struct drm_device *dev,
2295                                   struct intel_wm_config *config)
2296 {
2297         struct intel_crtc *intel_crtc;
2298
2299         /* Compute the currently _active_ config */
2300         for_each_intel_crtc(dev, intel_crtc) {
2301                 const struct intel_pipe_wm *wm = &intel_crtc->wm.active;
2302
2303                 if (!wm->pipe_enabled)
2304                         continue;
2305
2306                 config->sprites_enabled |= wm->sprites_enabled;
2307                 config->sprites_scaled |= wm->sprites_scaled;
2308                 config->num_pipes_active++;
2309         }
2310 }
2311
2312 /* Compute new watermarks for the pipe */
2313 static bool intel_compute_pipe_wm(struct intel_crtc_state *cstate,
2314                                   struct intel_pipe_wm *pipe_wm)
2315 {
2316         struct drm_crtc *crtc = cstate->base.crtc;
2317         struct drm_device *dev = crtc->dev;
2318         const struct drm_i915_private *dev_priv = dev->dev_private;
2319         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2320         struct intel_plane *intel_plane;
2321         struct intel_plane_state *sprstate = NULL;
2322         int level, max_level = ilk_wm_max_level(dev);
2323         /* LP0 watermark maximums depend on this pipe alone */
2324         struct intel_wm_config config = {
2325                 .num_pipes_active = 1,
2326         };
2327         struct ilk_wm_maximums max;
2328
2329         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2330                 if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY) {
2331                         sprstate = to_intel_plane_state(intel_plane->base.state);
2332                         break;
2333                 }
2334         }
2335
2336         config.sprites_enabled = sprstate->visible;
2337         config.sprites_scaled = sprstate->visible &&
2338                 (drm_rect_width(&sprstate->dst) != drm_rect_width(&sprstate->src) >> 16 ||
2339                 drm_rect_height(&sprstate->dst) != drm_rect_height(&sprstate->src) >> 16);
2340
2341         pipe_wm->pipe_enabled = cstate->base.active;
2342         pipe_wm->sprites_enabled = sprstate->visible;
2343         pipe_wm->sprites_scaled = config.sprites_scaled;
2344
2345         /* ILK/SNB: LP2+ watermarks only w/o sprites */
2346         if (INTEL_INFO(dev)->gen <= 6 && sprstate->visible)
2347                 max_level = 1;
2348
2349         /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2350         if (config.sprites_scaled)
2351                 max_level = 0;
2352
2353         ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate, &pipe_wm->wm[0]);
2354
2355         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2356                 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
2357
2358         /* LP0 watermarks always use 1/2 DDB partitioning */
2359         ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2360
2361         /* At least LP0 must be valid */
2362         if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2363                 return false;
2364
2365         ilk_compute_wm_reg_maximums(dev, 1, &max);
2366
2367         for (level = 1; level <= max_level; level++) {
2368                 struct intel_wm_level wm = {};
2369
2370                 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate, &wm);
2371
2372                 /*
2373                  * Disable any watermark level that exceeds the
2374                  * register maximums since such watermarks are
2375                  * always invalid.
2376                  */
2377                 if (!ilk_validate_wm_level(level, &max, &wm))
2378                         break;
2379
2380                 pipe_wm->wm[level] = wm;
2381         }
2382
2383         return true;
2384 }
2385
2386 /*
2387  * Merge the watermarks from all active pipes for a specific level.
2388  */
2389 static void ilk_merge_wm_level(struct drm_device *dev,
2390                                int level,
2391                                struct intel_wm_level *ret_wm)
2392 {
2393         const struct intel_crtc *intel_crtc;
2394
2395         ret_wm->enable = true;
2396
2397         for_each_intel_crtc(dev, intel_crtc) {
2398                 const struct intel_pipe_wm *active = &intel_crtc->wm.active;
2399                 const struct intel_wm_level *wm = &active->wm[level];
2400
2401                 if (!active->pipe_enabled)
2402                         continue;
2403
2404                 /*
2405                  * The watermark values may have been used in the past,
2406                  * so we must maintain them in the registers for some
2407                  * time even if the level is now disabled.
2408                  */
2409                 if (!wm->enable)
2410                         ret_wm->enable = false;
2411
2412                 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2413                 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2414                 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2415                 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2416         }
2417 }
2418
2419 /*
2420  * Merge all low power watermarks for all active pipes.
2421  */
2422 static void ilk_wm_merge(struct drm_device *dev,
2423                          const struct intel_wm_config *config,
2424                          const struct ilk_wm_maximums *max,
2425                          struct intel_pipe_wm *merged)
2426 {
2427         struct drm_i915_private *dev_priv = dev->dev_private;
2428         int level, max_level = ilk_wm_max_level(dev);
2429         int last_enabled_level = max_level;
2430
2431         /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2432         if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2433             config->num_pipes_active > 1)
2434                 return;
2435
2436         /* ILK: FBC WM must be disabled always */
2437         merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2438
2439         /* merge each WM1+ level */
2440         for (level = 1; level <= max_level; level++) {
2441                 struct intel_wm_level *wm = &merged->wm[level];
2442
2443                 ilk_merge_wm_level(dev, level, wm);
2444
2445                 if (level > last_enabled_level)
2446                         wm->enable = false;
2447                 else if (!ilk_validate_wm_level(level, max, wm))
2448                         /* make sure all following levels get disabled */
2449                         last_enabled_level = level - 1;
2450
2451                 /*
2452                  * The spec says it is preferred to disable
2453                  * FBC WMs instead of disabling a WM level.
2454                  */
2455                 if (wm->fbc_val > max->fbc) {
2456                         if (wm->enable)
2457                                 merged->fbc_wm_enabled = false;
2458                         wm->fbc_val = 0;
2459                 }
2460         }
2461
2462         /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2463         /*
2464          * FIXME this is racy. FBC might get enabled later.
2465          * What we should check here is whether FBC can be
2466          * enabled sometime later.
2467          */
2468         if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
2469             intel_fbc_enabled(dev_priv)) {
2470                 for (level = 2; level <= max_level; level++) {
2471                         struct intel_wm_level *wm = &merged->wm[level];
2472
2473                         wm->enable = false;
2474                 }
2475         }
2476 }
2477
2478 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2479 {
2480         /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2481         return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2482 }
2483
2484 /* The value we need to program into the WM_LPx latency field */
2485 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2486 {
2487         struct drm_i915_private *dev_priv = dev->dev_private;
2488
2489         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2490                 return 2 * level;
2491         else
2492                 return dev_priv->wm.pri_latency[level];
2493 }
2494
2495 static void ilk_compute_wm_results(struct drm_device *dev,
2496                                    const struct intel_pipe_wm *merged,
2497                                    enum intel_ddb_partitioning partitioning,
2498                                    struct ilk_wm_values *results)
2499 {
2500         struct intel_crtc *intel_crtc;
2501         int level, wm_lp;
2502
2503         results->enable_fbc_wm = merged->fbc_wm_enabled;
2504         results->partitioning = partitioning;
2505
2506         /* LP1+ register values */
2507         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2508                 const struct intel_wm_level *r;
2509
2510                 level = ilk_wm_lp_to_level(wm_lp, merged);
2511
2512                 r = &merged->wm[level];
2513
2514                 /*
2515                  * Maintain the watermark values even if the level is
2516                  * disabled. Doing otherwise could cause underruns.
2517                  */
2518                 results->wm_lp[wm_lp - 1] =
2519                         (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2520                         (r->pri_val << WM1_LP_SR_SHIFT) |
2521                         r->cur_val;
2522
2523                 if (r->enable)
2524                         results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2525
2526                 if (INTEL_INFO(dev)->gen >= 8)
2527                         results->wm_lp[wm_lp - 1] |=
2528                                 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2529                 else
2530                         results->wm_lp[wm_lp - 1] |=
2531                                 r->fbc_val << WM1_LP_FBC_SHIFT;
2532
2533                 /*
2534                  * Always set WM1S_LP_EN when spr_val != 0, even if the
2535                  * level is disabled. Doing otherwise could cause underruns.
2536                  */
2537                 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2538                         WARN_ON(wm_lp != 1);
2539                         results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2540                 } else
2541                         results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2542         }
2543
2544         /* LP0 register values */
2545         for_each_intel_crtc(dev, intel_crtc) {
2546                 enum pipe pipe = intel_crtc->pipe;
2547                 const struct intel_wm_level *r =
2548                         &intel_crtc->wm.active.wm[0];
2549
2550                 if (WARN_ON(!r->enable))
2551                         continue;
2552
2553                 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
2554
2555                 results->wm_pipe[pipe] =
2556                         (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2557                         (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2558                         r->cur_val;
2559         }
2560 }
2561
2562 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2563  * case both are at the same level. Prefer r1 in case they're the same. */
2564 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2565                                                   struct intel_pipe_wm *r1,
2566                                                   struct intel_pipe_wm *r2)
2567 {
2568         int level, max_level = ilk_wm_max_level(dev);
2569         int level1 = 0, level2 = 0;
2570
2571         for (level = 1; level <= max_level; level++) {
2572                 if (r1->wm[level].enable)
2573                         level1 = level;
2574                 if (r2->wm[level].enable)
2575                         level2 = level;
2576         }
2577
2578         if (level1 == level2) {
2579                 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2580                         return r2;
2581                 else
2582                         return r1;
2583         } else if (level1 > level2) {
2584                 return r1;
2585         } else {
2586                 return r2;
2587         }
2588 }
2589
2590 /* dirty bits used to track which watermarks need changes */
2591 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2592 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2593 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2594 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2595 #define WM_DIRTY_FBC (1 << 24)
2596 #define WM_DIRTY_DDB (1 << 25)
2597
2598 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
2599                                          const struct ilk_wm_values *old,
2600                                          const struct ilk_wm_values *new)
2601 {
2602         unsigned int dirty = 0;
2603         enum pipe pipe;
2604         int wm_lp;
2605
2606         for_each_pipe(dev_priv, pipe) {
2607                 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2608                         dirty |= WM_DIRTY_LINETIME(pipe);
2609                         /* Must disable LP1+ watermarks too */
2610                         dirty |= WM_DIRTY_LP_ALL;
2611                 }
2612
2613                 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2614                         dirty |= WM_DIRTY_PIPE(pipe);
2615                         /* Must disable LP1+ watermarks too */
2616                         dirty |= WM_DIRTY_LP_ALL;
2617                 }
2618         }
2619
2620         if (old->enable_fbc_wm != new->enable_fbc_wm) {
2621                 dirty |= WM_DIRTY_FBC;
2622                 /* Must disable LP1+ watermarks too */
2623                 dirty |= WM_DIRTY_LP_ALL;
2624         }
2625
2626         if (old->partitioning != new->partitioning) {
2627                 dirty |= WM_DIRTY_DDB;
2628                 /* Must disable LP1+ watermarks too */
2629                 dirty |= WM_DIRTY_LP_ALL;
2630         }
2631
2632         /* LP1+ watermarks already deemed dirty, no need to continue */
2633         if (dirty & WM_DIRTY_LP_ALL)
2634                 return dirty;
2635
2636         /* Find the lowest numbered LP1+ watermark in need of an update... */
2637         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2638                 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2639                     old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2640                         break;
2641         }
2642
2643         /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2644         for (; wm_lp <= 3; wm_lp++)
2645                 dirty |= WM_DIRTY_LP(wm_lp);
2646
2647         return dirty;
2648 }
2649
2650 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2651                                unsigned int dirty)
2652 {
2653         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2654         bool changed = false;
2655
2656         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2657                 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2658                 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2659                 changed = true;
2660         }
2661         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2662                 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2663                 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2664                 changed = true;
2665         }
2666         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2667                 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2668                 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2669                 changed = true;
2670         }
2671
2672         /*
2673          * Don't touch WM1S_LP_EN here.
2674          * Doing so could cause underruns.
2675          */
2676
2677         return changed;
2678 }
2679
2680 /*
2681  * The spec says we shouldn't write when we don't need, because every write
2682  * causes WMs to be re-evaluated, expending some power.
2683  */
2684 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2685                                 struct ilk_wm_values *results)
2686 {
2687         struct drm_device *dev = dev_priv->dev;
2688         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2689         unsigned int dirty;
2690         uint32_t val;
2691
2692         dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
2693         if (!dirty)
2694                 return;
2695
2696         _ilk_disable_lp_wm(dev_priv, dirty);
2697
2698         if (dirty & WM_DIRTY_PIPE(PIPE_A))
2699                 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2700         if (dirty & WM_DIRTY_PIPE(PIPE_B))
2701                 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2702         if (dirty & WM_DIRTY_PIPE(PIPE_C))
2703                 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2704
2705         if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2706                 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2707         if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2708                 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2709         if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2710                 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2711
2712         if (dirty & WM_DIRTY_DDB) {
2713                 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2714                         val = I915_READ(WM_MISC);
2715                         if (results->partitioning == INTEL_DDB_PART_1_2)
2716                                 val &= ~WM_MISC_DATA_PARTITION_5_6;
2717                         else
2718                                 val |= WM_MISC_DATA_PARTITION_5_6;
2719                         I915_WRITE(WM_MISC, val);
2720                 } else {
2721                         val = I915_READ(DISP_ARB_CTL2);
2722                         if (results->partitioning == INTEL_DDB_PART_1_2)
2723                                 val &= ~DISP_DATA_PARTITION_5_6;
2724                         else
2725                                 val |= DISP_DATA_PARTITION_5_6;
2726                         I915_WRITE(DISP_ARB_CTL2, val);
2727                 }
2728         }
2729
2730         if (dirty & WM_DIRTY_FBC) {
2731                 val = I915_READ(DISP_ARB_CTL);
2732                 if (results->enable_fbc_wm)
2733                         val &= ~DISP_FBC_WM_DIS;
2734                 else
2735                         val |= DISP_FBC_WM_DIS;
2736                 I915_WRITE(DISP_ARB_CTL, val);
2737         }
2738
2739         if (dirty & WM_DIRTY_LP(1) &&
2740             previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2741                 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2742
2743         if (INTEL_INFO(dev)->gen >= 7) {
2744                 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2745                         I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2746                 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2747                         I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2748         }
2749
2750         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2751                 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2752         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2753                 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2754         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2755                 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2756
2757         dev_priv->wm.hw = *results;
2758 }
2759
2760 static bool ilk_disable_lp_wm(struct drm_device *dev)
2761 {
2762         struct drm_i915_private *dev_priv = dev->dev_private;
2763
2764         return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2765 }
2766
2767 /*
2768  * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2769  * different active planes.
2770  */
2771
2772 #define SKL_DDB_SIZE            896     /* in blocks */
2773 #define BXT_DDB_SIZE            512
2774
2775 static void
2776 skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
2777                                    struct drm_crtc *for_crtc,
2778                                    const struct intel_wm_config *config,
2779                                    const struct skl_pipe_wm_parameters *params,
2780                                    struct skl_ddb_entry *alloc /* out */)
2781 {
2782         struct drm_crtc *crtc;
2783         unsigned int pipe_size, ddb_size;
2784         int nth_active_pipe;
2785
2786         if (!params->active) {
2787                 alloc->start = 0;
2788                 alloc->end = 0;
2789                 return;
2790         }
2791
2792         if (IS_BROXTON(dev))
2793                 ddb_size = BXT_DDB_SIZE;
2794         else
2795                 ddb_size = SKL_DDB_SIZE;
2796
2797         ddb_size -= 4; /* 4 blocks for bypass path allocation */
2798
2799         nth_active_pipe = 0;
2800         for_each_crtc(dev, crtc) {
2801                 if (!to_intel_crtc(crtc)->active)
2802                         continue;
2803
2804                 if (crtc == for_crtc)
2805                         break;
2806
2807                 nth_active_pipe++;
2808         }
2809
2810         pipe_size = ddb_size / config->num_pipes_active;
2811         alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active;
2812         alloc->end = alloc->start + pipe_size;
2813 }
2814
2815 static unsigned int skl_cursor_allocation(const struct intel_wm_config *config)
2816 {
2817         if (config->num_pipes_active == 1)
2818                 return 32;
2819
2820         return 8;
2821 }
2822
2823 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2824 {
2825         entry->start = reg & 0x3ff;
2826         entry->end = (reg >> 16) & 0x3ff;
2827         if (entry->end)
2828                 entry->end += 1;
2829 }
2830
2831 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2832                           struct skl_ddb_allocation *ddb /* out */)
2833 {
2834         enum pipe pipe;
2835         int plane;
2836         u32 val;
2837
2838         memset(ddb, 0, sizeof(*ddb));
2839
2840         for_each_pipe(dev_priv, pipe) {
2841                 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe)))
2842                         continue;
2843
2844                 for_each_plane(dev_priv, pipe, plane) {
2845                         val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2846                         skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2847                                                    val);
2848                 }
2849
2850                 val = I915_READ(CUR_BUF_CFG(pipe));
2851                 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
2852                                            val);
2853         }
2854 }
2855
2856 static unsigned int
2857 skl_plane_relative_data_rate(const struct intel_plane_wm_parameters *p, int y)
2858 {
2859
2860         /* for planar format */
2861         if (p->y_bytes_per_pixel) {
2862                 if (y)  /* y-plane data rate */
2863                         return p->horiz_pixels * p->vert_pixels * p->y_bytes_per_pixel;
2864                 else    /* uv-plane data rate */
2865                         return (p->horiz_pixels/2) * (p->vert_pixels/2) * p->bytes_per_pixel;
2866         }
2867
2868         /* for packed formats */
2869         return p->horiz_pixels * p->vert_pixels * p->bytes_per_pixel;
2870 }
2871
2872 /*
2873  * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2874  * a 8192x4096@32bpp framebuffer:
2875  *   3 * 4096 * 8192  * 4 < 2^32
2876  */
2877 static unsigned int
2878 skl_get_total_relative_data_rate(struct intel_crtc *intel_crtc,
2879                                  const struct skl_pipe_wm_parameters *params)
2880 {
2881         unsigned int total_data_rate = 0;
2882         int plane;
2883
2884         for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
2885                 const struct intel_plane_wm_parameters *p;
2886
2887                 p = &params->plane[plane];
2888                 if (!p->enabled)
2889                         continue;
2890
2891                 total_data_rate += skl_plane_relative_data_rate(p, 0); /* packed/uv */
2892                 if (p->y_bytes_per_pixel) {
2893                         total_data_rate += skl_plane_relative_data_rate(p, 1); /* y-plane */
2894                 }
2895         }
2896
2897         return total_data_rate;
2898 }
2899
2900 static void
2901 skl_allocate_pipe_ddb(struct drm_crtc *crtc,
2902                       const struct intel_wm_config *config,
2903                       const struct skl_pipe_wm_parameters *params,
2904                       struct skl_ddb_allocation *ddb /* out */)
2905 {
2906         struct drm_device *dev = crtc->dev;
2907         struct drm_i915_private *dev_priv = dev->dev_private;
2908         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2909         enum pipe pipe = intel_crtc->pipe;
2910         struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
2911         uint16_t alloc_size, start, cursor_blocks;
2912         uint16_t minimum[I915_MAX_PLANES];
2913         uint16_t y_minimum[I915_MAX_PLANES];
2914         unsigned int total_data_rate;
2915         int plane;
2916
2917         skl_ddb_get_pipe_allocation_limits(dev, crtc, config, params, alloc);
2918         alloc_size = skl_ddb_entry_size(alloc);
2919         if (alloc_size == 0) {
2920                 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
2921                 memset(&ddb->plane[pipe][PLANE_CURSOR], 0,
2922                        sizeof(ddb->plane[pipe][PLANE_CURSOR]));
2923                 return;
2924         }
2925
2926         cursor_blocks = skl_cursor_allocation(config);
2927         ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks;
2928         ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
2929
2930         alloc_size -= cursor_blocks;
2931         alloc->end -= cursor_blocks;
2932
2933         /* 1. Allocate the mininum required blocks for each active plane */
2934         for_each_plane(dev_priv, pipe, plane) {
2935                 const struct intel_plane_wm_parameters *p;
2936
2937                 p = &params->plane[plane];
2938                 if (!p->enabled)
2939                         continue;
2940
2941                 minimum[plane] = 8;
2942                 alloc_size -= minimum[plane];
2943                 y_minimum[plane] = p->y_bytes_per_pixel ? 8 : 0;
2944                 alloc_size -= y_minimum[plane];
2945         }
2946
2947         /*
2948          * 2. Distribute the remaining space in proportion to the amount of
2949          * data each plane needs to fetch from memory.
2950          *
2951          * FIXME: we may not allocate every single block here.
2952          */
2953         total_data_rate = skl_get_total_relative_data_rate(intel_crtc, params);
2954
2955         start = alloc->start;
2956         for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
2957                 const struct intel_plane_wm_parameters *p;
2958                 unsigned int data_rate, y_data_rate;
2959                 uint16_t plane_blocks, y_plane_blocks = 0;
2960
2961                 p = &params->plane[plane];
2962                 if (!p->enabled)
2963                         continue;
2964
2965                 data_rate = skl_plane_relative_data_rate(p, 0);
2966
2967                 /*
2968                  * allocation for (packed formats) or (uv-plane part of planar format):
2969                  * promote the expression to 64 bits to avoid overflowing, the
2970                  * result is < available as data_rate / total_data_rate < 1
2971                  */
2972                 plane_blocks = minimum[plane];
2973                 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
2974                                         total_data_rate);
2975
2976                 ddb->plane[pipe][plane].start = start;
2977                 ddb->plane[pipe][plane].end = start + plane_blocks;
2978
2979                 start += plane_blocks;
2980
2981                 /*
2982                  * allocation for y_plane part of planar format:
2983                  */
2984                 if (p->y_bytes_per_pixel) {
2985                         y_data_rate = skl_plane_relative_data_rate(p, 1);
2986                         y_plane_blocks = y_minimum[plane];
2987                         y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
2988                                                 total_data_rate);
2989
2990                         ddb->y_plane[pipe][plane].start = start;
2991                         ddb->y_plane[pipe][plane].end = start + y_plane_blocks;
2992
2993                         start += y_plane_blocks;
2994                 }
2995
2996         }
2997
2998 }
2999
3000 static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
3001 {
3002         /* TODO: Take into account the scalers once we support them */
3003         return config->base.adjusted_mode.crtc_clock;
3004 }
3005
3006 /*
3007  * The max latency should be 257 (max the punit can code is 255 and we add 2us
3008  * for the read latency) and bytes_per_pixel should always be <= 8, so that
3009  * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3010  * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3011 */
3012 static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
3013                                uint32_t latency)
3014 {
3015         uint32_t wm_intermediate_val, ret;
3016
3017         if (latency == 0)
3018                 return UINT_MAX;
3019
3020         wm_intermediate_val = latency * pixel_rate * bytes_per_pixel / 512;
3021         ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3022
3023         return ret;
3024 }
3025
3026 static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
3027                                uint32_t horiz_pixels, uint8_t bytes_per_pixel,
3028                                uint64_t tiling, uint32_t latency)
3029 {
3030         uint32_t ret;
3031         uint32_t plane_bytes_per_line, plane_blocks_per_line;
3032         uint32_t wm_intermediate_val;
3033
3034         if (latency == 0)
3035                 return UINT_MAX;
3036
3037         plane_bytes_per_line = horiz_pixels * bytes_per_pixel;
3038
3039         if (tiling == I915_FORMAT_MOD_Y_TILED ||
3040             tiling == I915_FORMAT_MOD_Yf_TILED) {
3041                 plane_bytes_per_line *= 4;
3042                 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3043                 plane_blocks_per_line /= 4;
3044         } else {
3045                 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3046         }
3047
3048         wm_intermediate_val = latency * pixel_rate;
3049         ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
3050                                 plane_blocks_per_line;
3051
3052         return ret;
3053 }
3054
3055 static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
3056                                        const struct intel_crtc *intel_crtc)
3057 {
3058         struct drm_device *dev = intel_crtc->base.dev;
3059         struct drm_i915_private *dev_priv = dev->dev_private;
3060         const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
3061         enum pipe pipe = intel_crtc->pipe;
3062
3063         if (memcmp(new_ddb->plane[pipe], cur_ddb->plane[pipe],
3064                    sizeof(new_ddb->plane[pipe])))
3065                 return true;
3066
3067         if (memcmp(&new_ddb->plane[pipe][PLANE_CURSOR], &cur_ddb->plane[pipe][PLANE_CURSOR],
3068                     sizeof(new_ddb->plane[pipe][PLANE_CURSOR])))
3069                 return true;
3070
3071         return false;
3072 }
3073
3074 static void skl_compute_wm_global_parameters(struct drm_device *dev,
3075                                              struct intel_wm_config *config)
3076 {
3077         struct drm_crtc *crtc;
3078         struct drm_plane *plane;
3079
3080         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3081                 config->num_pipes_active += to_intel_crtc(crtc)->active;
3082
3083         /* FIXME: I don't think we need those two global parameters on SKL */
3084         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
3085                 struct intel_plane *intel_plane = to_intel_plane(plane);
3086
3087                 config->sprites_enabled |= intel_plane->wm.enabled;
3088                 config->sprites_scaled |= intel_plane->wm.scaled;
3089         }
3090 }
3091
3092 static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
3093                                            struct skl_pipe_wm_parameters *p)
3094 {
3095         struct drm_device *dev = crtc->dev;
3096         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3097         enum pipe pipe = intel_crtc->pipe;
3098         struct drm_plane *plane;
3099         struct drm_framebuffer *fb;
3100         int i = 1; /* Index for sprite planes start */
3101
3102         p->active = intel_crtc->active;
3103         if (p->active) {
3104                 p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
3105                 p->pixel_rate = skl_pipe_pixel_rate(intel_crtc->config);
3106
3107                 fb = crtc->primary->state->fb;
3108                 /* For planar: Bpp is for uv plane, y_Bpp is for y plane */
3109                 if (fb) {
3110                         p->plane[0].enabled = true;
3111                         p->plane[0].bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ?
3112                                 drm_format_plane_cpp(fb->pixel_format, 1) :
3113                                 drm_format_plane_cpp(fb->pixel_format, 0);
3114                         p->plane[0].y_bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ?
3115                                 drm_format_plane_cpp(fb->pixel_format, 0) : 0;
3116                         p->plane[0].tiling = fb->modifier[0];
3117                 } else {
3118                         p->plane[0].enabled = false;
3119                         p->plane[0].bytes_per_pixel = 0;
3120                         p->plane[0].y_bytes_per_pixel = 0;
3121                         p->plane[0].tiling = DRM_FORMAT_MOD_NONE;
3122                 }
3123                 p->plane[0].horiz_pixels = intel_crtc->config->pipe_src_w;
3124                 p->plane[0].vert_pixels = intel_crtc->config->pipe_src_h;
3125                 p->plane[0].rotation = crtc->primary->state->rotation;
3126
3127                 fb = crtc->cursor->state->fb;
3128                 p->plane[PLANE_CURSOR].y_bytes_per_pixel = 0;
3129                 if (fb) {
3130                         p->plane[PLANE_CURSOR].enabled = true;
3131                         p->plane[PLANE_CURSOR].bytes_per_pixel = fb->bits_per_pixel / 8;
3132                         p->plane[PLANE_CURSOR].horiz_pixels = crtc->cursor->state->crtc_w;
3133                         p->plane[PLANE_CURSOR].vert_pixels = crtc->cursor->state->crtc_h;
3134                 } else {
3135                         p->plane[PLANE_CURSOR].enabled = false;
3136                         p->plane[PLANE_CURSOR].bytes_per_pixel = 0;
3137                         p->plane[PLANE_CURSOR].horiz_pixels = 64;
3138                         p->plane[PLANE_CURSOR].vert_pixels = 64;
3139                 }
3140         }
3141
3142         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
3143                 struct intel_plane *intel_plane = to_intel_plane(plane);
3144
3145                 if (intel_plane->pipe == pipe &&
3146                         plane->type == DRM_PLANE_TYPE_OVERLAY)
3147                         p->plane[i++] = intel_plane->wm;
3148         }
3149 }
3150
3151 static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3152                                  struct skl_pipe_wm_parameters *p,
3153                                  struct intel_plane_wm_parameters *p_params,
3154                                  uint16_t ddb_allocation,
3155                                  int level,
3156                                  uint16_t *out_blocks, /* out */
3157                                  uint8_t *out_lines /* out */)
3158 {
3159         uint32_t latency = dev_priv->wm.skl_latency[level];
3160         uint32_t method1, method2;
3161         uint32_t plane_bytes_per_line, plane_blocks_per_line;
3162         uint32_t res_blocks, res_lines;
3163         uint32_t selected_result;
3164         uint8_t bytes_per_pixel;
3165
3166         if (latency == 0 || !p->active || !p_params->enabled)
3167                 return false;
3168
3169         bytes_per_pixel = p_params->y_bytes_per_pixel ?
3170                 p_params->y_bytes_per_pixel :
3171                 p_params->bytes_per_pixel;
3172         method1 = skl_wm_method1(p->pixel_rate,
3173                                  bytes_per_pixel,
3174                                  latency);
3175         method2 = skl_wm_method2(p->pixel_rate,
3176                                  p->pipe_htotal,
3177                                  p_params->horiz_pixels,
3178                                  bytes_per_pixel,
3179                                  p_params->tiling,
3180                                  latency);
3181
3182         plane_bytes_per_line = p_params->horiz_pixels * bytes_per_pixel;
3183         plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3184
3185         if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
3186             p_params->tiling == I915_FORMAT_MOD_Yf_TILED) {
3187                 uint32_t min_scanlines = 4;
3188                 uint32_t y_tile_minimum;
3189                 if (intel_rotation_90_or_270(p_params->rotation)) {
3190                         switch (p_params->bytes_per_pixel) {
3191                         case 1:
3192                                 min_scanlines = 16;
3193                                 break;
3194                         case 2:
3195                                 min_scanlines = 8;
3196                                 break;
3197                         case 8:
3198                                 WARN(1, "Unsupported pixel depth for rotation");
3199                         }
3200                 }
3201                 y_tile_minimum = plane_blocks_per_line * min_scanlines;
3202                 selected_result = max(method2, y_tile_minimum);
3203         } else {
3204                 if ((ddb_allocation / plane_blocks_per_line) >= 1)
3205                         selected_result = min(method1, method2);
3206                 else
3207                         selected_result = method1;
3208         }
3209
3210         res_blocks = selected_result + 1;
3211         res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
3212
3213         if (level >= 1 && level <= 7) {
3214                 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
3215                     p_params->tiling == I915_FORMAT_MOD_Yf_TILED)
3216                         res_lines += 4;
3217                 else
3218                         res_blocks++;
3219         }
3220
3221         if (res_blocks >= ddb_allocation || res_lines > 31)
3222                 return false;
3223
3224         *out_blocks = res_blocks;
3225         *out_lines = res_lines;
3226
3227         return true;
3228 }
3229
3230 static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3231                                  struct skl_ddb_allocation *ddb,
3232                                  struct skl_pipe_wm_parameters *p,
3233                                  enum pipe pipe,
3234                                  int level,
3235                                  int num_planes,
3236                                  struct skl_wm_level *result)
3237 {
3238         uint16_t ddb_blocks;
3239         int i;
3240
3241         for (i = 0; i < num_planes; i++) {
3242                 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3243
3244                 result->plane_en[i] = skl_compute_plane_wm(dev_priv,
3245                                                 p, &p->plane[i],
3246                                                 ddb_blocks,
3247                                                 level,
3248                                                 &result->plane_res_b[i],
3249                                                 &result->plane_res_l[i]);
3250         }
3251
3252         ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][PLANE_CURSOR]);
3253         result->plane_en[PLANE_CURSOR] = skl_compute_plane_wm(dev_priv, p,
3254                                                  &p->plane[PLANE_CURSOR],
3255                                                  ddb_blocks, level,
3256                                                  &result->plane_res_b[PLANE_CURSOR],
3257                                                  &result->plane_res_l[PLANE_CURSOR]);
3258 }
3259
3260 static uint32_t
3261 skl_compute_linetime_wm(struct drm_crtc *crtc, struct skl_pipe_wm_parameters *p)
3262 {
3263         if (!to_intel_crtc(crtc)->active)
3264                 return 0;
3265
3266         if (WARN_ON(p->pixel_rate == 0))
3267                 return 0;
3268
3269         return DIV_ROUND_UP(8 * p->pipe_htotal * 1000, p->pixel_rate);
3270 }
3271
3272 static void skl_compute_transition_wm(struct drm_crtc *crtc,
3273                                       struct skl_pipe_wm_parameters *params,
3274                                       struct skl_wm_level *trans_wm /* out */)
3275 {
3276         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3277         int i;
3278
3279         if (!params->active)
3280                 return;
3281
3282         /* Until we know more, just disable transition WMs */
3283         for (i = 0; i < intel_num_planes(intel_crtc); i++)
3284                 trans_wm->plane_en[i] = false;
3285         trans_wm->plane_en[PLANE_CURSOR] = false;
3286 }
3287
3288 static void skl_compute_pipe_wm(struct drm_crtc *crtc,
3289                                 struct skl_ddb_allocation *ddb,
3290                                 struct skl_pipe_wm_parameters *params,
3291                                 struct skl_pipe_wm *pipe_wm)
3292 {
3293         struct drm_device *dev = crtc->dev;
3294         const struct drm_i915_private *dev_priv = dev->dev_private;
3295         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3296         int level, max_level = ilk_wm_max_level(dev);
3297
3298         for (level = 0; level <= max_level; level++) {
3299                 skl_compute_wm_level(dev_priv, ddb, params, intel_crtc->pipe,
3300                                      level, intel_num_planes(intel_crtc),
3301                                      &pipe_wm->wm[level]);
3302         }
3303         pipe_wm->linetime = skl_compute_linetime_wm(crtc, params);
3304
3305         skl_compute_transition_wm(crtc, params, &pipe_wm->trans_wm);
3306 }
3307
3308 static void skl_compute_wm_results(struct drm_device *dev,
3309                                    struct skl_pipe_wm_parameters *p,
3310                                    struct skl_pipe_wm *p_wm,
3311                                    struct skl_wm_values *r,
3312                                    struct intel_crtc *intel_crtc)
3313 {
3314         int level, max_level = ilk_wm_max_level(dev);
3315         enum pipe pipe = intel_crtc->pipe;
3316         uint32_t temp;
3317         int i;
3318
3319         for (level = 0; level <= max_level; level++) {
3320                 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3321                         temp = 0;
3322
3323                         temp |= p_wm->wm[level].plane_res_l[i] <<
3324                                         PLANE_WM_LINES_SHIFT;
3325                         temp |= p_wm->wm[level].plane_res_b[i];
3326                         if (p_wm->wm[level].plane_en[i])
3327                                 temp |= PLANE_WM_EN;
3328
3329                         r->plane[pipe][i][level] = temp;
3330                 }
3331
3332                 temp = 0;
3333
3334                 temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3335                 temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR];
3336
3337                 if (p_wm->wm[level].plane_en[PLANE_CURSOR])
3338                         temp |= PLANE_WM_EN;
3339
3340                 r->plane[pipe][PLANE_CURSOR][level] = temp;
3341
3342         }
3343
3344         /* transition WMs */
3345         for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3346                 temp = 0;
3347                 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3348                 temp |= p_wm->trans_wm.plane_res_b[i];
3349                 if (p_wm->trans_wm.plane_en[i])
3350                         temp |= PLANE_WM_EN;
3351
3352                 r->plane_trans[pipe][i] = temp;
3353         }
3354
3355         temp = 0;
3356         temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3357         temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR];
3358         if (p_wm->trans_wm.plane_en[PLANE_CURSOR])
3359                 temp |= PLANE_WM_EN;
3360
3361         r->plane_trans[pipe][PLANE_CURSOR] = temp;
3362
3363         r->wm_linetime[pipe] = p_wm->linetime;
3364 }
3365
3366 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, uint32_t reg,
3367                                 const struct skl_ddb_entry *entry)
3368 {
3369         if (entry->end)
3370                 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3371         else
3372                 I915_WRITE(reg, 0);
3373 }
3374
3375 static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3376                                 const struct skl_wm_values *new)
3377 {
3378         struct drm_device *dev = dev_priv->dev;
3379         struct intel_crtc *crtc;
3380
3381         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
3382                 int i, level, max_level = ilk_wm_max_level(dev);
3383                 enum pipe pipe = crtc->pipe;
3384
3385                 if (!new->dirty[pipe])
3386                         continue;
3387
3388                 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
3389
3390                 for (level = 0; level <= max_level; level++) {
3391                         for (i = 0; i < intel_num_planes(crtc); i++)
3392                                 I915_WRITE(PLANE_WM(pipe, i, level),
3393                                            new->plane[pipe][i][level]);
3394                         I915_WRITE(CUR_WM(pipe, level),
3395                                    new->plane[pipe][PLANE_CURSOR][level]);
3396                 }
3397                 for (i = 0; i < intel_num_planes(crtc); i++)
3398                         I915_WRITE(PLANE_WM_TRANS(pipe, i),
3399                                    new->plane_trans[pipe][i]);
3400                 I915_WRITE(CUR_WM_TRANS(pipe),
3401                            new->plane_trans[pipe][PLANE_CURSOR]);
3402
3403                 for (i = 0; i < intel_num_planes(crtc); i++) {
3404                         skl_ddb_entry_write(dev_priv,
3405                                             PLANE_BUF_CFG(pipe, i),
3406                                             &new->ddb.plane[pipe][i]);
3407                         skl_ddb_entry_write(dev_priv,
3408                                             PLANE_NV12_BUF_CFG(pipe, i),
3409                                             &new->ddb.y_plane[pipe][i]);
3410                 }
3411
3412                 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3413                                     &new->ddb.plane[pipe][PLANE_CURSOR]);
3414         }
3415 }
3416
3417 /*
3418  * When setting up a new DDB allocation arrangement, we need to correctly
3419  * sequence the times at which the new allocations for the pipes are taken into
3420  * account or we'll have pipes fetching from space previously allocated to
3421  * another pipe.
3422  *
3423  * Roughly the sequence looks like:
3424  *  1. re-allocate the pipe(s) with the allocation being reduced and not
3425  *     overlapping with a previous light-up pipe (another way to put it is:
3426  *     pipes with their new allocation strickly included into their old ones).
3427  *  2. re-allocate the other pipes that get their allocation reduced
3428  *  3. allocate the pipes having their allocation increased
3429  *
3430  * Steps 1. and 2. are here to take care of the following case:
3431  * - Initially DDB looks like this:
3432  *     |   B    |   C    |
3433  * - enable pipe A.
3434  * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3435  *   allocation
3436  *     |  A  |  B  |  C  |
3437  *
3438  * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3439  */
3440
3441 static void
3442 skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
3443 {
3444         int plane;
3445
3446         DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3447
3448         for_each_plane(dev_priv, pipe, plane) {
3449                 I915_WRITE(PLANE_SURF(pipe, plane),
3450                            I915_READ(PLANE_SURF(pipe, plane)));
3451         }
3452         I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3453 }
3454
3455 static bool
3456 skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3457                             const struct skl_ddb_allocation *new,
3458                             enum pipe pipe)
3459 {
3460         uint16_t old_size, new_size;
3461
3462         old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3463         new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3464
3465         return old_size != new_size &&
3466                new->pipe[pipe].start >= old->pipe[pipe].start &&
3467                new->pipe[pipe].end <= old->pipe[pipe].end;
3468 }
3469
3470 static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3471                                 struct skl_wm_values *new_values)
3472 {
3473         struct drm_device *dev = dev_priv->dev;
3474         struct skl_ddb_allocation *cur_ddb, *new_ddb;
3475         bool reallocated[I915_MAX_PIPES] = {};
3476         struct intel_crtc *crtc;
3477         enum pipe pipe;
3478
3479         new_ddb = &new_values->ddb;
3480         cur_ddb = &dev_priv->wm.skl_hw.ddb;
3481
3482         /*
3483          * First pass: flush the pipes with the new allocation contained into
3484          * the old space.
3485          *
3486          * We'll wait for the vblank on those pipes to ensure we can safely
3487          * re-allocate the freed space without this pipe fetching from it.
3488          */
3489         for_each_intel_crtc(dev, crtc) {
3490                 if (!crtc->active)
3491                         continue;
3492
3493                 pipe = crtc->pipe;
3494
3495                 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3496                         continue;
3497
3498                 skl_wm_flush_pipe(dev_priv, pipe, 1);
3499                 intel_wait_for_vblank(dev, pipe);
3500
3501                 reallocated[pipe] = true;
3502         }
3503
3504
3505         /*
3506          * Second pass: flush the pipes that are having their allocation
3507          * reduced, but overlapping with a previous allocation.
3508          *
3509          * Here as well we need to wait for the vblank to make sure the freed
3510          * space is not used anymore.
3511          */
3512         for_each_intel_crtc(dev, crtc) {
3513                 if (!crtc->active)
3514                         continue;
3515
3516                 pipe = crtc->pipe;
3517
3518                 if (reallocated[pipe])
3519                         continue;
3520
3521                 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3522                     skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
3523                         skl_wm_flush_pipe(dev_priv, pipe, 2);
3524                         intel_wait_for_vblank(dev, pipe);
3525                         reallocated[pipe] = true;
3526                 }
3527         }
3528
3529         /*
3530          * Third pass: flush the pipes that got more space allocated.
3531          *
3532          * We don't need to actively wait for the update here, next vblank
3533          * will just get more DDB space with the correct WM values.
3534          */
3535         for_each_intel_crtc(dev, crtc) {
3536                 if (!crtc->active)
3537                         continue;
3538
3539                 pipe = crtc->pipe;
3540
3541                 /*
3542                  * At this point, only the pipes more space than before are
3543                  * left to re-allocate.
3544                  */
3545                 if (reallocated[pipe])
3546                         continue;
3547
3548                 skl_wm_flush_pipe(dev_priv, pipe, 3);
3549         }
3550 }
3551
3552 static bool skl_update_pipe_wm(struct drm_crtc *crtc,
3553                                struct skl_pipe_wm_parameters *params,
3554                                struct intel_wm_config *config,
3555                                struct skl_ddb_allocation *ddb, /* out */
3556                                struct skl_pipe_wm *pipe_wm /* out */)
3557 {
3558         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3559
3560         skl_compute_wm_pipe_parameters(crtc, params);
3561         skl_allocate_pipe_ddb(crtc, config, params, ddb);
3562         skl_compute_pipe_wm(crtc, ddb, params, pipe_wm);
3563
3564         if (!memcmp(&intel_crtc->wm.skl_active, pipe_wm, sizeof(*pipe_wm)))
3565                 return false;
3566
3567         intel_crtc->wm.skl_active = *pipe_wm;
3568
3569         return true;
3570 }
3571
3572 static void skl_update_other_pipe_wm(struct drm_device *dev,
3573                                      struct drm_crtc *crtc,
3574                                      struct intel_wm_config *config,
3575                                      struct skl_wm_values *r)
3576 {
3577         struct intel_crtc *intel_crtc;
3578         struct intel_crtc *this_crtc = to_intel_crtc(crtc);
3579
3580         /*
3581          * If the WM update hasn't changed the allocation for this_crtc (the
3582          * crtc we are currently computing the new WM values for), other
3583          * enabled crtcs will keep the same allocation and we don't need to
3584          * recompute anything for them.
3585          */
3586         if (!skl_ddb_allocation_changed(&r->ddb, this_crtc))
3587                 return;
3588
3589         /*
3590          * Otherwise, because of this_crtc being freshly enabled/disabled, the
3591          * other active pipes need new DDB allocation and WM values.
3592          */
3593         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
3594                                 base.head) {
3595                 struct skl_pipe_wm_parameters params = {};
3596                 struct skl_pipe_wm pipe_wm = {};
3597                 bool wm_changed;
3598
3599                 if (this_crtc->pipe == intel_crtc->pipe)
3600                         continue;
3601
3602                 if (!intel_crtc->active)
3603                         continue;
3604
3605                 wm_changed = skl_update_pipe_wm(&intel_crtc->base,
3606                                                 &params, config,
3607                                                 &r->ddb, &pipe_wm);
3608
3609                 /*
3610                  * If we end up re-computing the other pipe WM values, it's
3611                  * because it was really needed, so we expect the WM values to
3612                  * be different.
3613                  */
3614                 WARN_ON(!wm_changed);
3615
3616                 skl_compute_wm_results(dev, &params, &pipe_wm, r, intel_crtc);
3617                 r->dirty[intel_crtc->pipe] = true;
3618         }
3619 }
3620
3621 static void skl_clear_wm(struct skl_wm_values *watermarks, enum pipe pipe)
3622 {
3623         watermarks->wm_linetime[pipe] = 0;
3624         memset(watermarks->plane[pipe], 0,
3625                sizeof(uint32_t) * 8 * I915_MAX_PLANES);
3626         memset(watermarks->plane_trans[pipe],
3627                0, sizeof(uint32_t) * I915_MAX_PLANES);
3628         watermarks->plane_trans[pipe][PLANE_CURSOR] = 0;
3629
3630         /* Clear ddb entries for pipe */
3631         memset(&watermarks->ddb.pipe[pipe], 0, sizeof(struct skl_ddb_entry));
3632         memset(&watermarks->ddb.plane[pipe], 0,
3633                sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
3634         memset(&watermarks->ddb.y_plane[pipe], 0,
3635                sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
3636         memset(&watermarks->ddb.plane[pipe][PLANE_CURSOR], 0,
3637                sizeof(struct skl_ddb_entry));
3638
3639 }
3640
3641 static void skl_update_wm(struct drm_crtc *crtc)
3642 {
3643         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3644         struct drm_device *dev = crtc->dev;
3645         struct drm_i915_private *dev_priv = dev->dev_private;
3646         struct skl_pipe_wm_parameters params = {};
3647         struct skl_wm_values *results = &dev_priv->wm.skl_results;
3648         struct skl_pipe_wm pipe_wm = {};
3649         struct intel_wm_config config = {};
3650
3651
3652         /* Clear all dirty flags */
3653         memset(results->dirty, 0, sizeof(bool) * I915_MAX_PIPES);
3654
3655         skl_clear_wm(results, intel_crtc->pipe);
3656
3657         skl_compute_wm_global_parameters(dev, &config);
3658
3659         if (!skl_update_pipe_wm(crtc, &params, &config,
3660                                 &results->ddb, &pipe_wm))
3661                 return;
3662
3663         skl_compute_wm_results(dev, &params, &pipe_wm, results, intel_crtc);
3664         results->dirty[intel_crtc->pipe] = true;
3665
3666         skl_update_other_pipe_wm(dev, crtc, &config, results);
3667         skl_write_wm_values(dev_priv, results);
3668         skl_flush_wm_values(dev_priv, results);
3669
3670         /* store the new configuration */
3671         dev_priv->wm.skl_hw = *results;
3672 }
3673
3674 static void
3675 skl_update_sprite_wm(struct drm_plane *plane, struct drm_crtc *crtc,
3676                      uint32_t sprite_width, uint32_t sprite_height,
3677                      int pixel_size, bool enabled, bool scaled)
3678 {
3679         struct intel_plane *intel_plane = to_intel_plane(plane);
3680         struct drm_framebuffer *fb = plane->state->fb;
3681
3682         intel_plane->wm.enabled = enabled;
3683         intel_plane->wm.scaled = scaled;
3684         intel_plane->wm.horiz_pixels = sprite_width;
3685         intel_plane->wm.vert_pixels = sprite_height;
3686         intel_plane->wm.tiling = DRM_FORMAT_MOD_NONE;
3687
3688         /* For planar: Bpp is for UV plane, y_Bpp is for Y plane */
3689         intel_plane->wm.bytes_per_pixel =
3690                 (fb && fb->pixel_format == DRM_FORMAT_NV12) ?
3691                 drm_format_plane_cpp(plane->state->fb->pixel_format, 1) : pixel_size;
3692         intel_plane->wm.y_bytes_per_pixel =
3693                 (fb && fb->pixel_format == DRM_FORMAT_NV12) ?
3694                 drm_format_plane_cpp(plane->state->fb->pixel_format, 0) : 0;
3695
3696         /*
3697          * Framebuffer can be NULL on plane disable, but it does not
3698          * matter for watermarks if we assume no tiling in that case.
3699          */
3700         if (fb)
3701                 intel_plane->wm.tiling = fb->modifier[0];
3702         intel_plane->wm.rotation = plane->state->rotation;
3703
3704         skl_update_wm(crtc);
3705 }
3706
3707 static void ilk_update_wm(struct drm_crtc *crtc)
3708 {
3709         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3710         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3711         struct drm_device *dev = crtc->dev;
3712         struct drm_i915_private *dev_priv = dev->dev_private;
3713         struct ilk_wm_maximums max;
3714         struct ilk_wm_values results = {};
3715         enum intel_ddb_partitioning partitioning;
3716         struct intel_pipe_wm pipe_wm = {};
3717         struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
3718         struct intel_wm_config config = {};
3719
3720         WARN_ON(cstate->base.active != intel_crtc->active);
3721
3722         intel_compute_pipe_wm(cstate, &pipe_wm);
3723
3724         if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
3725                 return;
3726
3727         intel_crtc->wm.active = pipe_wm;
3728
3729         ilk_compute_wm_config(dev, &config);
3730
3731         ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
3732         ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
3733
3734         /* 5/6 split only in single pipe config on IVB+ */
3735         if (INTEL_INFO(dev)->gen >= 7 &&
3736             config.num_pipes_active == 1 && config.sprites_enabled) {
3737                 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
3738                 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
3739
3740                 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
3741         } else {
3742                 best_lp_wm = &lp_wm_1_2;
3743         }
3744
3745         partitioning = (best_lp_wm == &lp_wm_1_2) ?
3746                        INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
3747
3748         ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
3749
3750         ilk_write_wm_values(dev_priv, &results);
3751 }
3752
3753 static void
3754 ilk_update_sprite_wm(struct drm_plane *plane,
3755                      struct drm_crtc *crtc,
3756                      uint32_t sprite_width, uint32_t sprite_height,
3757                      int pixel_size, bool enabled, bool scaled)
3758 {
3759         struct drm_device *dev = plane->dev;
3760         struct intel_plane *intel_plane = to_intel_plane(plane);
3761
3762         /*
3763          * IVB workaround: must disable low power watermarks for at least
3764          * one frame before enabling scaling.  LP watermarks can be re-enabled
3765          * when scaling is disabled.
3766          *
3767          * WaCxSRDisabledForSpriteScaling:ivb
3768          */
3769         if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
3770                 intel_wait_for_vblank(dev, intel_plane->pipe);
3771
3772         ilk_update_wm(crtc);
3773 }
3774
3775 static void skl_pipe_wm_active_state(uint32_t val,
3776                                      struct skl_pipe_wm *active,
3777                                      bool is_transwm,
3778                                      bool is_cursor,
3779                                      int i,
3780                                      int level)
3781 {
3782         bool is_enabled = (val & PLANE_WM_EN) != 0;
3783
3784         if (!is_transwm) {
3785                 if (!is_cursor) {
3786                         active->wm[level].plane_en[i] = is_enabled;
3787                         active->wm[level].plane_res_b[i] =
3788                                         val & PLANE_WM_BLOCKS_MASK;
3789                         active->wm[level].plane_res_l[i] =
3790                                         (val >> PLANE_WM_LINES_SHIFT) &
3791                                                 PLANE_WM_LINES_MASK;
3792                 } else {
3793                         active->wm[level].plane_en[PLANE_CURSOR] = is_enabled;
3794                         active->wm[level].plane_res_b[PLANE_CURSOR] =
3795                                         val & PLANE_WM_BLOCKS_MASK;
3796                         active->wm[level].plane_res_l[PLANE_CURSOR] =
3797                                         (val >> PLANE_WM_LINES_SHIFT) &
3798                                                 PLANE_WM_LINES_MASK;
3799                 }
3800         } else {
3801                 if (!is_cursor) {
3802                         active->trans_wm.plane_en[i] = is_enabled;
3803                         active->trans_wm.plane_res_b[i] =
3804                                         val & PLANE_WM_BLOCKS_MASK;
3805                         active->trans_wm.plane_res_l[i] =
3806                                         (val >> PLANE_WM_LINES_SHIFT) &
3807                                                 PLANE_WM_LINES_MASK;
3808                 } else {
3809                         active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled;
3810                         active->trans_wm.plane_res_b[PLANE_CURSOR] =
3811                                         val & PLANE_WM_BLOCKS_MASK;
3812                         active->trans_wm.plane_res_l[PLANE_CURSOR] =
3813                                         (val >> PLANE_WM_LINES_SHIFT) &
3814                                                 PLANE_WM_LINES_MASK;
3815                 }
3816         }
3817 }
3818
3819 static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3820 {
3821         struct drm_device *dev = crtc->dev;
3822         struct drm_i915_private *dev_priv = dev->dev_private;
3823         struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
3824         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3825         struct skl_pipe_wm *active = &intel_crtc->wm.skl_active;
3826         enum pipe pipe = intel_crtc->pipe;
3827         int level, i, max_level;
3828         uint32_t temp;
3829
3830         max_level = ilk_wm_max_level(dev);
3831
3832         hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3833
3834         for (level = 0; level <= max_level; level++) {
3835                 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3836                         hw->plane[pipe][i][level] =
3837                                         I915_READ(PLANE_WM(pipe, i, level));
3838                 hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level));
3839         }
3840
3841         for (i = 0; i < intel_num_planes(intel_crtc); i++)
3842                 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
3843         hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe));
3844
3845         if (!intel_crtc->active)
3846                 return;
3847
3848         hw->dirty[pipe] = true;
3849
3850         active->linetime = hw->wm_linetime[pipe];
3851
3852         for (level = 0; level <= max_level; level++) {
3853                 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3854                         temp = hw->plane[pipe][i][level];
3855                         skl_pipe_wm_active_state(temp, active, false,
3856                                                 false, i, level);
3857                 }
3858                 temp = hw->plane[pipe][PLANE_CURSOR][level];
3859                 skl_pipe_wm_active_state(temp, active, false, true, i, level);
3860         }
3861
3862         for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3863                 temp = hw->plane_trans[pipe][i];
3864                 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
3865         }
3866
3867         temp = hw->plane_trans[pipe][PLANE_CURSOR];
3868         skl_pipe_wm_active_state(temp, active, true, true, i, 0);
3869 }
3870
3871 void skl_wm_get_hw_state(struct drm_device *dev)
3872 {
3873         struct drm_i915_private *dev_priv = dev->dev_private;
3874         struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3875         struct drm_crtc *crtc;
3876
3877         skl_ddb_get_hw_state(dev_priv, ddb);
3878         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3879                 skl_pipe_wm_get_hw_state(crtc);
3880 }
3881
3882 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3883 {
3884         struct drm_device *dev = crtc->dev;
3885         struct drm_i915_private *dev_priv = dev->dev_private;
3886         struct ilk_wm_values *hw = &dev_priv->wm.hw;
3887         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3888         struct intel_pipe_wm *active = &intel_crtc->wm.active;
3889         enum pipe pipe = intel_crtc->pipe;
3890         static const unsigned int wm0_pipe_reg[] = {
3891                 [PIPE_A] = WM0_PIPEA_ILK,
3892                 [PIPE_B] = WM0_PIPEB_ILK,
3893                 [PIPE_C] = WM0_PIPEC_IVB,
3894         };
3895
3896         hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
3897         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3898                 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3899
3900         memset(active, 0, sizeof(*active));
3901
3902         active->pipe_enabled = intel_crtc->active;
3903
3904         if (active->pipe_enabled) {
3905                 u32 tmp = hw->wm_pipe[pipe];
3906
3907                 /*
3908                  * For active pipes LP0 watermark is marked as
3909                  * enabled, and LP1+ watermaks as disabled since
3910                  * we can't really reverse compute them in case
3911                  * multiple pipes are active.
3912                  */
3913                 active->wm[0].enable = true;
3914                 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3915                 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3916                 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3917                 active->linetime = hw->wm_linetime[pipe];
3918         } else {
3919                 int level, max_level = ilk_wm_max_level(dev);
3920
3921                 /*
3922                  * For inactive pipes, all watermark levels
3923                  * should be marked as enabled but zeroed,
3924                  * which is what we'd compute them to.
3925                  */
3926                 for (level = 0; level <= max_level; level++)
3927                         active->wm[level].enable = true;
3928         }
3929 }
3930
3931 #define _FW_WM(value, plane) \
3932         (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
3933 #define _FW_WM_VLV(value, plane) \
3934         (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
3935
3936 static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
3937                                struct vlv_wm_values *wm)
3938 {
3939         enum pipe pipe;
3940         uint32_t tmp;
3941
3942         for_each_pipe(dev_priv, pipe) {
3943                 tmp = I915_READ(VLV_DDL(pipe));
3944
3945                 wm->ddl[pipe].primary =
3946                         (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3947                 wm->ddl[pipe].cursor =
3948                         (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3949                 wm->ddl[pipe].sprite[0] =
3950                         (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3951                 wm->ddl[pipe].sprite[1] =
3952                         (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3953         }
3954
3955         tmp = I915_READ(DSPFW1);
3956         wm->sr.plane = _FW_WM(tmp, SR);
3957         wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
3958         wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
3959         wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
3960
3961         tmp = I915_READ(DSPFW2);
3962         wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
3963         wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
3964         wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
3965
3966         tmp = I915_READ(DSPFW3);
3967         wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
3968
3969         if (IS_CHERRYVIEW(dev_priv)) {
3970                 tmp = I915_READ(DSPFW7_CHV);
3971                 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
3972                 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
3973
3974                 tmp = I915_READ(DSPFW8_CHV);
3975                 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
3976                 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
3977
3978                 tmp = I915_READ(DSPFW9_CHV);
3979                 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
3980                 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
3981
3982                 tmp = I915_READ(DSPHOWM);
3983                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
3984                 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
3985                 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
3986                 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
3987                 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
3988                 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
3989                 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
3990                 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
3991                 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
3992                 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
3993         } else {
3994                 tmp = I915_READ(DSPFW7);
3995                 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
3996                 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
3997
3998                 tmp = I915_READ(DSPHOWM);
3999                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4000                 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4001                 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4002                 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4003                 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4004                 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4005                 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4006         }
4007 }
4008
4009 #undef _FW_WM
4010 #undef _FW_WM_VLV
4011
4012 void vlv_wm_get_hw_state(struct drm_device *dev)
4013 {
4014         struct drm_i915_private *dev_priv = to_i915(dev);
4015         struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4016         struct intel_plane *plane;
4017         enum pipe pipe;
4018         u32 val;
4019
4020         vlv_read_wm_values(dev_priv, wm);
4021
4022         for_each_intel_plane(dev, plane) {
4023                 switch (plane->base.type) {
4024                         int sprite;
4025                 case DRM_PLANE_TYPE_CURSOR:
4026                         plane->wm.fifo_size = 63;
4027                         break;
4028                 case DRM_PLANE_TYPE_PRIMARY:
4029                         plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
4030                         break;
4031                 case DRM_PLANE_TYPE_OVERLAY:
4032                         sprite = plane->plane;
4033                         plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
4034                         break;
4035                 }
4036         }
4037
4038         wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4039         wm->level = VLV_WM_LEVEL_PM2;
4040
4041         if (IS_CHERRYVIEW(dev_priv)) {
4042                 mutex_lock(&dev_priv->rps.hw_lock);
4043
4044                 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4045                 if (val & DSP_MAXFIFO_PM5_ENABLE)
4046                         wm->level = VLV_WM_LEVEL_PM5;
4047
4048                 /*
4049                  * If DDR DVFS is disabled in the BIOS, Punit
4050                  * will never ack the request. So if that happens
4051                  * assume we don't have to enable/disable DDR DVFS
4052                  * dynamically. To test that just set the REQ_ACK
4053                  * bit to poke the Punit, but don't change the
4054                  * HIGH/LOW bits so that we don't actually change
4055                  * the current state.
4056                  */
4057                 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4058                 val |= FORCE_DDR_FREQ_REQ_ACK;
4059                 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4060
4061                 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4062                               FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4063                         DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4064                                       "assuming DDR DVFS is disabled\n");
4065                         dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4066                 } else {
4067                         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4068                         if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4069                                 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4070                 }
4071
4072                 mutex_unlock(&dev_priv->rps.hw_lock);
4073         }
4074
4075         for_each_pipe(dev_priv, pipe)
4076                 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4077                               pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4078                               wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4079
4080         DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4081                       wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4082 }
4083
4084 void ilk_wm_get_hw_state(struct drm_device *dev)
4085 {
4086         struct drm_i915_private *dev_priv = dev->dev_private;
4087         struct ilk_wm_values *hw = &dev_priv->wm.hw;
4088         struct drm_crtc *crtc;
4089
4090         for_each_crtc(dev, crtc)
4091                 ilk_pipe_wm_get_hw_state(crtc);
4092
4093         hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4094         hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4095         hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4096
4097         hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
4098         if (INTEL_INFO(dev)->gen >= 7) {
4099                 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4100                 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4101         }
4102
4103         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4104                 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4105                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4106         else if (IS_IVYBRIDGE(dev))
4107                 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4108                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4109
4110         hw->enable_fbc_wm =
4111                 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4112 }
4113
4114 /**
4115  * intel_update_watermarks - update FIFO watermark values based on current modes
4116  *
4117  * Calculate watermark values for the various WM regs based on current mode
4118  * and plane configuration.
4119  *
4120  * There are several cases to deal with here:
4121  *   - normal (i.e. non-self-refresh)
4122  *   - self-refresh (SR) mode
4123  *   - lines are large relative to FIFO size (buffer can hold up to 2)
4124  *   - lines are small relative to FIFO size (buffer can hold more than 2
4125  *     lines), so need to account for TLB latency
4126  *
4127  *   The normal calculation is:
4128  *     watermark = dotclock * bytes per pixel * latency
4129  *   where latency is platform & configuration dependent (we assume pessimal
4130  *   values here).
4131  *
4132  *   The SR calculation is:
4133  *     watermark = (trunc(latency/line time)+1) * surface width *
4134  *       bytes per pixel
4135  *   where
4136  *     line time = htotal / dotclock
4137  *     surface width = hdisplay for normal plane and 64 for cursor
4138  *   and latency is assumed to be high, as above.
4139  *
4140  * The final value programmed to the register should always be rounded up,
4141  * and include an extra 2 entries to account for clock crossings.
4142  *
4143  * We don't use the sprite, so we can ignore that.  And on Crestline we have
4144  * to set the non-SR watermarks to 8.
4145  */
4146 void intel_update_watermarks(struct drm_crtc *crtc)
4147 {
4148         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4149
4150         if (dev_priv->display.update_wm)
4151                 dev_priv->display.update_wm(crtc);
4152 }
4153
4154 void intel_update_sprite_watermarks(struct drm_plane *plane,
4155                                     struct drm_crtc *crtc,
4156                                     uint32_t sprite_width,
4157                                     uint32_t sprite_height,
4158                                     int pixel_size,
4159                                     bool enabled, bool scaled)
4160 {
4161         struct drm_i915_private *dev_priv = plane->dev->dev_private;
4162
4163         if (dev_priv->display.update_sprite_wm)
4164                 dev_priv->display.update_sprite_wm(plane, crtc,
4165                                                    sprite_width, sprite_height,
4166                                                    pixel_size, enabled, scaled);
4167 }
4168
4169 /**
4170  * Lock protecting IPS related data structures
4171  */
4172 DEFINE_SPINLOCK(mchdev_lock);
4173
4174 /* Global for IPS driver to get at the current i915 device. Protected by
4175  * mchdev_lock. */
4176 static struct drm_i915_private *i915_mch_dev;
4177
4178 bool ironlake_set_drps(struct drm_device *dev, u8 val)
4179 {
4180         struct drm_i915_private *dev_priv = dev->dev_private;
4181         u16 rgvswctl;
4182
4183         assert_spin_locked(&mchdev_lock);
4184
4185         rgvswctl = I915_READ16(MEMSWCTL);
4186         if (rgvswctl & MEMCTL_CMD_STS) {
4187                 DRM_DEBUG("gpu busy, RCS change rejected\n");
4188                 return false; /* still busy with another command */
4189         }
4190
4191         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4192                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4193         I915_WRITE16(MEMSWCTL, rgvswctl);
4194         POSTING_READ16(MEMSWCTL);
4195
4196         rgvswctl |= MEMCTL_CMD_STS;
4197         I915_WRITE16(MEMSWCTL, rgvswctl);
4198
4199         return true;
4200 }
4201
4202 static void ironlake_enable_drps(struct drm_device *dev)
4203 {
4204         struct drm_i915_private *dev_priv = dev->dev_private;
4205         u32 rgvmodectl = I915_READ(MEMMODECTL);
4206         u8 fmax, fmin, fstart, vstart;
4207
4208         spin_lock_irq(&mchdev_lock);
4209
4210         /* Enable temp reporting */
4211         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4212         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4213
4214         /* 100ms RC evaluation intervals */
4215         I915_WRITE(RCUPEI, 100000);
4216         I915_WRITE(RCDNEI, 100000);
4217
4218         /* Set max/min thresholds to 90ms and 80ms respectively */
4219         I915_WRITE(RCBMAXAVG, 90000);
4220         I915_WRITE(RCBMINAVG, 80000);
4221
4222         I915_WRITE(MEMIHYST, 1);
4223
4224         /* Set up min, max, and cur for interrupt handling */
4225         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4226         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4227         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4228                 MEMMODE_FSTART_SHIFT;
4229
4230         vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
4231                 PXVFREQ_PX_SHIFT;
4232
4233         dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4234         dev_priv->ips.fstart = fstart;
4235
4236         dev_priv->ips.max_delay = fstart;
4237         dev_priv->ips.min_delay = fmin;
4238         dev_priv->ips.cur_delay = fstart;
4239
4240         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4241                          fmax, fmin, fstart);
4242
4243         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4244
4245         /*
4246          * Interrupts will be enabled in ironlake_irq_postinstall
4247          */
4248
4249         I915_WRITE(VIDSTART, vstart);
4250         POSTING_READ(VIDSTART);
4251
4252         rgvmodectl |= MEMMODE_SWMODE_EN;
4253         I915_WRITE(MEMMODECTL, rgvmodectl);
4254
4255         if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
4256                 DRM_ERROR("stuck trying to change perf mode\n");
4257         mdelay(1);
4258
4259         ironlake_set_drps(dev, fstart);
4260
4261         dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4262                 I915_READ(DDREC) + I915_READ(CSIEC);
4263         dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
4264         dev_priv->ips.last_count2 = I915_READ(GFXEC);
4265         dev_priv->ips.last_time2 = ktime_get_raw_ns();
4266
4267         spin_unlock_irq(&mchdev_lock);
4268 }
4269
4270 static void ironlake_disable_drps(struct drm_device *dev)
4271 {
4272         struct drm_i915_private *dev_priv = dev->dev_private;
4273         u16 rgvswctl;
4274
4275         spin_lock_irq(&mchdev_lock);
4276
4277         rgvswctl = I915_READ16(MEMSWCTL);
4278
4279         /* Ack interrupts, disable EFC interrupt */
4280         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4281         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4282         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4283         I915_WRITE(DEIIR, DE_PCU_EVENT);
4284         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4285
4286         /* Go back to the starting frequency */
4287         ironlake_set_drps(dev, dev_priv->ips.fstart);
4288         mdelay(1);
4289         rgvswctl |= MEMCTL_CMD_STS;
4290         I915_WRITE(MEMSWCTL, rgvswctl);
4291         mdelay(1);
4292
4293         spin_unlock_irq(&mchdev_lock);
4294 }
4295
4296 /* There's a funny hw issue where the hw returns all 0 when reading from
4297  * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4298  * ourselves, instead of doing a rmw cycle (which might result in us clearing
4299  * all limits and the gpu stuck at whatever frequency it is at atm).
4300  */
4301 static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
4302 {
4303         u32 limits;
4304
4305         /* Only set the down limit when we've reached the lowest level to avoid
4306          * getting more interrupts, otherwise leave this clear. This prevents a
4307          * race in the hw when coming out of rc6: There's a tiny window where
4308          * the hw runs at the minimal clock before selecting the desired
4309          * frequency, if the down threshold expires in that window we will not
4310          * receive a down interrupt. */
4311         if (IS_GEN9(dev_priv->dev)) {
4312                 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4313                 if (val <= dev_priv->rps.min_freq_softlimit)
4314                         limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4315         } else {
4316                 limits = dev_priv->rps.max_freq_softlimit << 24;
4317                 if (val <= dev_priv->rps.min_freq_softlimit)
4318                         limits |= dev_priv->rps.min_freq_softlimit << 16;
4319         }
4320
4321         return limits;
4322 }
4323
4324 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4325 {
4326         int new_power;
4327         u32 threshold_up = 0, threshold_down = 0; /* in % */
4328         u32 ei_up = 0, ei_down = 0;
4329
4330         new_power = dev_priv->rps.power;
4331         switch (dev_priv->rps.power) {
4332         case LOW_POWER:
4333                 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
4334                         new_power = BETWEEN;
4335                 break;
4336
4337         case BETWEEN:
4338                 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
4339                         new_power = LOW_POWER;
4340                 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
4341                         new_power = HIGH_POWER;
4342                 break;
4343
4344         case HIGH_POWER:
4345                 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
4346                         new_power = BETWEEN;
4347                 break;
4348         }
4349         /* Max/min bins are special */
4350         if (val <= dev_priv->rps.min_freq_softlimit)
4351                 new_power = LOW_POWER;
4352         if (val >= dev_priv->rps.max_freq_softlimit)
4353                 new_power = HIGH_POWER;
4354         if (new_power == dev_priv->rps.power)
4355                 return;
4356
4357         /* Note the units here are not exactly 1us, but 1280ns. */
4358         switch (new_power) {
4359         case LOW_POWER:
4360                 /* Upclock if more than 95% busy over 16ms */
4361                 ei_up = 16000;
4362                 threshold_up = 95;
4363
4364                 /* Downclock if less than 85% busy over 32ms */
4365                 ei_down = 32000;
4366                 threshold_down = 85;
4367                 break;
4368
4369         case BETWEEN:
4370                 /* Upclock if more than 90% busy over 13ms */
4371                 ei_up = 13000;
4372                 threshold_up = 90;
4373
4374                 /* Downclock if less than 75% busy over 32ms */
4375                 ei_down = 32000;
4376                 threshold_down = 75;
4377                 break;
4378
4379         case HIGH_POWER:
4380                 /* Upclock if more than 85% busy over 10ms */
4381                 ei_up = 10000;
4382                 threshold_up = 85;
4383
4384                 /* Downclock if less than 60% busy over 32ms */
4385                 ei_down = 32000;
4386                 threshold_down = 60;
4387                 break;
4388         }
4389
4390         /* When byt can survive without system hang with dynamic
4391          * sw freq adjustments, this restriction can be lifted.
4392          */
4393         if (IS_VALLEYVIEW(dev_priv))
4394                 goto skip_hw_write;
4395
4396         I915_WRITE(GEN6_RP_UP_EI,
4397                 GT_INTERVAL_FROM_US(dev_priv, ei_up));
4398         I915_WRITE(GEN6_RP_UP_THRESHOLD,
4399                 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100)));
4400
4401         I915_WRITE(GEN6_RP_DOWN_EI,
4402                 GT_INTERVAL_FROM_US(dev_priv, ei_down));
4403         I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4404                 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100)));
4405
4406          I915_WRITE(GEN6_RP_CONTROL,
4407                     GEN6_RP_MEDIA_TURBO |
4408                     GEN6_RP_MEDIA_HW_NORMAL_MODE |
4409                     GEN6_RP_MEDIA_IS_GFX |
4410                     GEN6_RP_ENABLE |
4411                     GEN6_RP_UP_BUSY_AVG |
4412                     GEN6_RP_DOWN_IDLE_AVG);
4413
4414 skip_hw_write:
4415         dev_priv->rps.power = new_power;
4416         dev_priv->rps.up_threshold = threshold_up;
4417         dev_priv->rps.down_threshold = threshold_down;
4418         dev_priv->rps.last_adj = 0;
4419 }
4420
4421 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4422 {
4423         u32 mask = 0;
4424
4425         /* We use UP_EI_EXPIRED interupts for both up/down in manual mode */
4426         if (val > dev_priv->rps.min_freq_softlimit)
4427                 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
4428         if (val < dev_priv->rps.max_freq_softlimit)
4429                 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
4430
4431         mask &= dev_priv->pm_rps_events;
4432
4433         return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
4434 }
4435
4436 /* gen6_set_rps is called to update the frequency request, but should also be
4437  * called when the range (min_delay and max_delay) is modified so that we can
4438  * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
4439 static void gen6_set_rps(struct drm_device *dev, u8 val)
4440 {
4441         struct drm_i915_private *dev_priv = dev->dev_private;
4442
4443         /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4444         if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0))
4445                 return;
4446
4447         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4448         WARN_ON(val > dev_priv->rps.max_freq);
4449         WARN_ON(val < dev_priv->rps.min_freq);
4450
4451         /* min/max delay may still have been modified so be sure to
4452          * write the limits value.
4453          */
4454         if (val != dev_priv->rps.cur_freq) {
4455                 gen6_set_rps_thresholds(dev_priv, val);
4456
4457                 if (IS_GEN9(dev))
4458                         I915_WRITE(GEN6_RPNSWREQ,
4459                                    GEN9_FREQUENCY(val));
4460                 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4461                         I915_WRITE(GEN6_RPNSWREQ,
4462                                    HSW_FREQUENCY(val));
4463                 else
4464                         I915_WRITE(GEN6_RPNSWREQ,
4465                                    GEN6_FREQUENCY(val) |
4466                                    GEN6_OFFSET(0) |
4467                                    GEN6_AGGRESSIVE_TURBO);
4468         }
4469
4470         /* Make sure we continue to get interrupts
4471          * until we hit the minimum or maximum frequencies.
4472          */
4473         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
4474         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4475
4476         POSTING_READ(GEN6_RPNSWREQ);
4477
4478         dev_priv->rps.cur_freq = val;
4479         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4480 }
4481
4482 static void valleyview_set_rps(struct drm_device *dev, u8 val)
4483 {
4484         struct drm_i915_private *dev_priv = dev->dev_private;
4485
4486         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4487         WARN_ON(val > dev_priv->rps.max_freq);
4488         WARN_ON(val < dev_priv->rps.min_freq);
4489
4490         if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
4491                       "Odd GPU freq value\n"))
4492                 val &= ~1;
4493
4494         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4495
4496         if (val != dev_priv->rps.cur_freq) {
4497                 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
4498                 if (!IS_CHERRYVIEW(dev_priv))
4499                         gen6_set_rps_thresholds(dev_priv, val);
4500         }
4501
4502         dev_priv->rps.cur_freq = val;
4503         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4504 }
4505
4506 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
4507  *
4508  * * If Gfx is Idle, then
4509  * 1. Forcewake Media well.
4510  * 2. Request idle freq.
4511  * 3. Release Forcewake of Media well.
4512 */
4513 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4514 {
4515         u32 val = dev_priv->rps.idle_freq;
4516
4517         if (dev_priv->rps.cur_freq <= val)
4518                 return;
4519
4520         /* Wake up the media well, as that takes a lot less
4521          * power than the Render well. */
4522         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
4523         valleyview_set_rps(dev_priv->dev, val);
4524         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
4525 }
4526
4527 void gen6_rps_busy(struct drm_i915_private *dev_priv)
4528 {
4529         mutex_lock(&dev_priv->rps.hw_lock);
4530         if (dev_priv->rps.enabled) {
4531                 if (dev_priv->pm_rps_events & GEN6_PM_RP_UP_EI_EXPIRED)
4532                         gen6_rps_reset_ei(dev_priv);
4533                 I915_WRITE(GEN6_PMINTRMSK,
4534                            gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
4535         }
4536         mutex_unlock(&dev_priv->rps.hw_lock);
4537 }
4538
4539 void gen6_rps_idle(struct drm_i915_private *dev_priv)
4540 {
4541         struct drm_device *dev = dev_priv->dev;
4542
4543         mutex_lock(&dev_priv->rps.hw_lock);
4544         if (dev_priv->rps.enabled) {
4545                 if (IS_VALLEYVIEW(dev))
4546                         vlv_set_rps_idle(dev_priv);
4547                 else
4548                         gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
4549                 dev_priv->rps.last_adj = 0;
4550                 I915_WRITE(GEN6_PMINTRMSK,
4551                            gen6_sanitize_rps_pm_mask(dev_priv, ~0));
4552         }
4553         mutex_unlock(&dev_priv->rps.hw_lock);
4554
4555         spin_lock(&dev_priv->rps.client_lock);
4556         while (!list_empty(&dev_priv->rps.clients))
4557                 list_del_init(dev_priv->rps.clients.next);
4558         spin_unlock(&dev_priv->rps.client_lock);
4559 }
4560
4561 void gen6_rps_boost(struct drm_i915_private *dev_priv,
4562                     struct intel_rps_client *rps,
4563                     unsigned long submitted)
4564 {
4565         /* This is intentionally racy! We peek at the state here, then
4566          * validate inside the RPS worker.
4567          */
4568         if (!(dev_priv->mm.busy &&
4569               dev_priv->rps.enabled &&
4570               dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit))
4571                 return;
4572
4573         /* Force a RPS boost (and don't count it against the client) if
4574          * the GPU is severely congested.
4575          */
4576         if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
4577                 rps = NULL;
4578
4579         spin_lock(&dev_priv->rps.client_lock);
4580         if (rps == NULL || list_empty(&rps->link)) {
4581                 spin_lock_irq(&dev_priv->irq_lock);
4582                 if (dev_priv->rps.interrupts_enabled) {
4583                         dev_priv->rps.client_boost = true;
4584                         queue_work(dev_priv->wq, &dev_priv->rps.work);
4585                 }
4586                 spin_unlock_irq(&dev_priv->irq_lock);
4587
4588                 if (rps != NULL) {
4589                         list_add(&rps->link, &dev_priv->rps.clients);
4590                         rps->boosts++;
4591                 } else
4592                         dev_priv->rps.boosts++;
4593         }
4594         spin_unlock(&dev_priv->rps.client_lock);
4595 }
4596
4597 void intel_set_rps(struct drm_device *dev, u8 val)
4598 {
4599         if (IS_VALLEYVIEW(dev))
4600                 valleyview_set_rps(dev, val);
4601         else
4602                 gen6_set_rps(dev, val);
4603 }
4604
4605 static void gen9_disable_rps(struct drm_device *dev)
4606 {
4607         struct drm_i915_private *dev_priv = dev->dev_private;
4608
4609         I915_WRITE(GEN6_RC_CONTROL, 0);
4610         I915_WRITE(GEN9_PG_ENABLE, 0);
4611 }
4612
4613 static void gen6_disable_rps(struct drm_device *dev)
4614 {
4615         struct drm_i915_private *dev_priv = dev->dev_private;
4616
4617         I915_WRITE(GEN6_RC_CONTROL, 0);
4618         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
4619 }
4620
4621 static void cherryview_disable_rps(struct drm_device *dev)
4622 {
4623         struct drm_i915_private *dev_priv = dev->dev_private;
4624
4625         I915_WRITE(GEN6_RC_CONTROL, 0);
4626 }
4627
4628 static void valleyview_disable_rps(struct drm_device *dev)
4629 {
4630         struct drm_i915_private *dev_priv = dev->dev_private;
4631
4632         /* we're doing forcewake before Disabling RC6,
4633          * This what the BIOS expects when going into suspend */
4634         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4635
4636         I915_WRITE(GEN6_RC_CONTROL, 0);
4637
4638         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4639 }
4640
4641 static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
4642 {
4643         if (IS_VALLEYVIEW(dev)) {
4644                 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4645                         mode = GEN6_RC_CTL_RC6_ENABLE;
4646                 else
4647                         mode = 0;
4648         }
4649         if (HAS_RC6p(dev))
4650                 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
4651                               (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
4652                               (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
4653                               (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
4654
4655         else
4656                 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
4657                               (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");
4658 }
4659
4660 static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
4661 {
4662         /* No RC6 before Ironlake and code is gone for ilk. */
4663         if (INTEL_INFO(dev)->gen < 6)
4664                 return 0;
4665
4666         /* Respect the kernel parameter if it is set */
4667         if (enable_rc6 >= 0) {
4668                 int mask;
4669
4670                 if (HAS_RC6p(dev))
4671                         mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
4672                                INTEL_RC6pp_ENABLE;
4673                 else
4674                         mask = INTEL_RC6_ENABLE;
4675
4676                 if ((enable_rc6 & mask) != enable_rc6)
4677                         DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
4678                                       enable_rc6 & mask, enable_rc6, mask);
4679
4680                 return enable_rc6 & mask;
4681         }
4682
4683         if (IS_IVYBRIDGE(dev))
4684                 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
4685
4686         return INTEL_RC6_ENABLE;
4687 }
4688
4689 int intel_enable_rc6(const struct drm_device *dev)
4690 {
4691         return i915.enable_rc6;
4692 }
4693
4694 static void gen6_init_rps_frequencies(struct drm_device *dev)
4695 {
4696         struct drm_i915_private *dev_priv = dev->dev_private;
4697         uint32_t rp_state_cap;
4698         u32 ddcc_status = 0;
4699         int ret;
4700
4701         /* All of these values are in units of 50MHz */
4702         dev_priv->rps.cur_freq          = 0;
4703         /* static values from HW: RP0 > RP1 > RPn (min_freq) */
4704         if (IS_BROXTON(dev)) {
4705                 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
4706                 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
4707                 dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
4708                 dev_priv->rps.min_freq = (rp_state_cap >>  0) & 0xff;
4709         } else {
4710                 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4711                 dev_priv->rps.rp0_freq = (rp_state_cap >>  0) & 0xff;
4712                 dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
4713                 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
4714         }
4715
4716         /* hw_max = RP0 until we check for overclocking */
4717         dev_priv->rps.max_freq          = dev_priv->rps.rp0_freq;
4718
4719         dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
4720         if (IS_HASWELL(dev) || IS_BROADWELL(dev) || IS_SKYLAKE(dev)) {
4721                 ret = sandybridge_pcode_read(dev_priv,
4722                                         HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
4723                                         &ddcc_status);
4724                 if (0 == ret)
4725                         dev_priv->rps.efficient_freq =
4726                                 clamp_t(u8,
4727                                         ((ddcc_status >> 8) & 0xff),
4728                                         dev_priv->rps.min_freq,
4729                                         dev_priv->rps.max_freq);
4730         }
4731
4732         if (IS_SKYLAKE(dev)) {
4733                 /* Store the frequency values in 16.66 MHZ units, which is
4734                    the natural hardware unit for SKL */
4735                 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
4736                 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
4737                 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
4738                 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
4739                 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
4740         }
4741
4742         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4743
4744         /* Preserve min/max settings in case of re-init */
4745         if (dev_priv->rps.max_freq_softlimit == 0)
4746                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4747
4748         if (dev_priv->rps.min_freq_softlimit == 0) {
4749                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4750                         dev_priv->rps.min_freq_softlimit =
4751                                 max_t(int, dev_priv->rps.efficient_freq,
4752                                       intel_freq_opcode(dev_priv, 450));
4753                 else
4754                         dev_priv->rps.min_freq_softlimit =
4755                                 dev_priv->rps.min_freq;
4756         }
4757 }
4758
4759 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
4760 static void gen9_enable_rps(struct drm_device *dev)
4761 {
4762         struct drm_i915_private *dev_priv = dev->dev_private;
4763
4764         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4765
4766         gen6_init_rps_frequencies(dev);
4767
4768         /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4769         if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) {
4770                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4771                 return;
4772         }
4773
4774         /* Program defaults and thresholds for RPS*/
4775         I915_WRITE(GEN6_RC_VIDEO_FREQ,
4776                 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
4777
4778         /* 1 second timeout*/
4779         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
4780                 GT_INTERVAL_FROM_US(dev_priv, 1000000));
4781
4782         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
4783
4784         /* Leaning on the below call to gen6_set_rps to program/setup the
4785          * Up/Down EI & threshold registers, as well as the RP_CONTROL,
4786          * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
4787         dev_priv->rps.power = HIGH_POWER; /* force a reset */
4788         gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
4789
4790         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4791 }
4792
4793 static void gen9_enable_rc6(struct drm_device *dev)
4794 {
4795         struct drm_i915_private *dev_priv = dev->dev_private;
4796         struct intel_engine_cs *ring;
4797         uint32_t rc6_mask = 0;
4798         int unused;
4799
4800         /* 1a: Software RC state - RC0 */
4801         I915_WRITE(GEN6_RC_STATE, 0);
4802
4803         /* 1b: Get forcewake during program sequence. Although the driver
4804          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4805         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4806
4807         /* 2a: Disable RC states. */
4808         I915_WRITE(GEN6_RC_CONTROL, 0);
4809
4810         /* 2b: Program RC6 thresholds.*/
4811
4812         /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
4813         if (IS_SKYLAKE(dev))
4814                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
4815         else
4816                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
4817         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4818         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4819         for_each_ring(ring, dev_priv, unused)
4820                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4821
4822         if (HAS_GUC_UCODE(dev))
4823                 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
4824
4825         I915_WRITE(GEN6_RC_SLEEP, 0);
4826
4827         /* 2c: Program Coarse Power Gating Policies. */
4828         I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
4829         I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
4830
4831         /* 3a: Enable RC6 */
4832         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4833                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4834         DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4835                         "on" : "off");
4836         /* WaRsUseTimeoutMode */
4837         if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_D0) ||
4838             (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_A0)) {
4839                 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
4840                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4841                            GEN7_RC_CTL_TO_MODE |
4842                            rc6_mask);
4843         } else {
4844                 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
4845                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4846                            GEN6_RC_CTL_EI_MODE(1) |
4847                            rc6_mask);
4848         }
4849
4850         /*
4851          * 3b: Enable Coarse Power Gating only when RC6 is enabled.
4852          * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
4853          */
4854         if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) ||
4855             ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && (INTEL_REVID(dev) <= SKL_REVID_F0)))
4856                 I915_WRITE(GEN9_PG_ENABLE, 0);
4857         else
4858                 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4859                                 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
4860
4861         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4862
4863 }
4864
4865 static void gen8_enable_rps(struct drm_device *dev)
4866 {
4867         struct drm_i915_private *dev_priv = dev->dev_private;
4868         struct intel_engine_cs *ring;
4869         uint32_t rc6_mask = 0;
4870         int unused;
4871
4872         /* 1a: Software RC state - RC0 */
4873         I915_WRITE(GEN6_RC_STATE, 0);
4874
4875         /* 1c & 1d: Get forcewake during program sequence. Although the driver
4876          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4877         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4878
4879         /* 2a: Disable RC states. */
4880         I915_WRITE(GEN6_RC_CONTROL, 0);
4881
4882         /* Initialize rps frequencies */
4883         gen6_init_rps_frequencies(dev);
4884
4885         /* 2b: Program RC6 thresholds.*/
4886         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4887         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4888         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4889         for_each_ring(ring, dev_priv, unused)
4890                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4891         I915_WRITE(GEN6_RC_SLEEP, 0);
4892         if (IS_BROADWELL(dev))
4893                 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
4894         else
4895                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
4896
4897         /* 3: Enable RC6 */
4898         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4899                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4900         intel_print_rc6_info(dev, rc6_mask);
4901         if (IS_BROADWELL(dev))
4902                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4903                                 GEN7_RC_CTL_TO_MODE |
4904                                 rc6_mask);
4905         else
4906                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4907                                 GEN6_RC_CTL_EI_MODE(1) |
4908                                 rc6_mask);
4909
4910         /* 4 Program defaults and thresholds for RPS*/
4911         I915_WRITE(GEN6_RPNSWREQ,
4912                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4913         I915_WRITE(GEN6_RC_VIDEO_FREQ,
4914                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4915         /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
4916         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
4917
4918         /* Docs recommend 900MHz, and 300 MHz respectively */
4919         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
4920                    dev_priv->rps.max_freq_softlimit << 24 |
4921                    dev_priv->rps.min_freq_softlimit << 16);
4922
4923         I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
4924         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
4925         I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
4926         I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
4927
4928         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4929
4930         /* 5: Enable RPS */
4931         I915_WRITE(GEN6_RP_CONTROL,
4932                    GEN6_RP_MEDIA_TURBO |
4933                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
4934                    GEN6_RP_MEDIA_IS_GFX |
4935                    GEN6_RP_ENABLE |
4936                    GEN6_RP_UP_BUSY_AVG |
4937                    GEN6_RP_DOWN_IDLE_AVG);
4938
4939         /* 6: Ring frequency + overclocking (our driver does this later */
4940
4941         dev_priv->rps.power = HIGH_POWER; /* force a reset */
4942         gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
4943
4944         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4945 }
4946
4947 static void gen6_enable_rps(struct drm_device *dev)
4948 {
4949         struct drm_i915_private *dev_priv = dev->dev_private;
4950         struct intel_engine_cs *ring;
4951         u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
4952         u32 gtfifodbg;
4953         int rc6_mode;
4954         int i, ret;
4955
4956         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4957
4958         /* Here begins a magic sequence of register writes to enable
4959          * auto-downclocking.
4960          *
4961          * Perhaps there might be some value in exposing these to
4962          * userspace...
4963          */
4964         I915_WRITE(GEN6_RC_STATE, 0);
4965
4966         /* Clear the DBG now so we don't confuse earlier errors */
4967         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4968                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
4969                 I915_WRITE(GTFIFODBG, gtfifodbg);
4970         }
4971
4972         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4973
4974         /* Initialize rps frequencies */
4975         gen6_init_rps_frequencies(dev);
4976
4977         /* disable the counters and set deterministic thresholds */
4978         I915_WRITE(GEN6_RC_CONTROL, 0);
4979
4980         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
4981         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
4982         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
4983         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4984         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4985
4986         for_each_ring(ring, dev_priv, i)
4987                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4988
4989         I915_WRITE(GEN6_RC_SLEEP, 0);
4990         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
4991         if (IS_IVYBRIDGE(dev))
4992                 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
4993         else
4994                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
4995         I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
4996         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
4997
4998         /* Check if we are enabling RC6 */
4999         rc6_mode = intel_enable_rc6(dev_priv->dev);
5000         if (rc6_mode & INTEL_RC6_ENABLE)
5001                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
5002
5003         /* We don't use those on Haswell */
5004         if (!IS_HASWELL(dev)) {
5005                 if (rc6_mode & INTEL_RC6p_ENABLE)
5006                         rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
5007
5008                 if (rc6_mode & INTEL_RC6pp_ENABLE)
5009                         rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
5010         }
5011
5012         intel_print_rc6_info(dev, rc6_mask);
5013
5014         I915_WRITE(GEN6_RC_CONTROL,
5015                    rc6_mask |
5016                    GEN6_RC_CTL_EI_MODE(1) |
5017                    GEN6_RC_CTL_HW_ENABLE);
5018
5019         /* Power down if completely idle for over 50ms */
5020         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
5021         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5022
5023         ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
5024         if (ret)
5025                 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
5026
5027         ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
5028         if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
5029                 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
5030                                  (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
5031                                  (pcu_mbox & 0xff) * 50);
5032                 dev_priv->rps.max_freq = pcu_mbox & 0xff;
5033         }
5034
5035         dev_priv->rps.power = HIGH_POWER; /* force a reset */
5036         gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
5037
5038         rc6vids = 0;
5039         ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
5040         if (IS_GEN6(dev) && ret) {
5041                 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
5042         } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
5043                 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5044                           GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5045                 rc6vids &= 0xffff00;
5046                 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5047                 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5048                 if (ret)
5049                         DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5050         }
5051
5052         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5053 }
5054
5055 static void __gen6_update_ring_freq(struct drm_device *dev)
5056 {
5057         struct drm_i915_private *dev_priv = dev->dev_private;
5058         int min_freq = 15;
5059         unsigned int gpu_freq;
5060         unsigned int max_ia_freq, min_ring_freq;
5061         unsigned int max_gpu_freq, min_gpu_freq;
5062         int scaling_factor = 180;
5063         struct cpufreq_policy *policy;
5064
5065         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5066
5067         policy = cpufreq_cpu_get(0);
5068         if (policy) {
5069                 max_ia_freq = policy->cpuinfo.max_freq;
5070                 cpufreq_cpu_put(policy);
5071         } else {
5072                 /*
5073                  * Default to measured freq if none found, PCU will ensure we
5074                  * don't go over
5075                  */
5076                 max_ia_freq = tsc_khz;
5077         }
5078
5079         /* Convert from kHz to MHz */
5080         max_ia_freq /= 1000;
5081
5082         min_ring_freq = I915_READ(DCLK) & 0xf;
5083         /* convert DDR frequency from units of 266.6MHz to bandwidth */
5084         min_ring_freq = mult_frac(min_ring_freq, 8, 3);
5085
5086         if (IS_SKYLAKE(dev)) {
5087                 /* Convert GT frequency to 50 HZ units */
5088                 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5089                 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5090         } else {
5091                 min_gpu_freq = dev_priv->rps.min_freq;
5092                 max_gpu_freq = dev_priv->rps.max_freq;
5093         }
5094
5095         /*
5096          * For each potential GPU frequency, load a ring frequency we'd like
5097          * to use for memory access.  We do this by specifying the IA frequency
5098          * the PCU should use as a reference to determine the ring frequency.
5099          */
5100         for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5101                 int diff = max_gpu_freq - gpu_freq;
5102                 unsigned int ia_freq = 0, ring_freq = 0;
5103
5104                 if (IS_SKYLAKE(dev)) {
5105                         /*
5106                          * ring_freq = 2 * GT. ring_freq is in 100MHz units
5107                          * No floor required for ring frequency on SKL.
5108                          */
5109                         ring_freq = gpu_freq;
5110                 } else if (INTEL_INFO(dev)->gen >= 8) {
5111                         /* max(2 * GT, DDR). NB: GT is 50MHz units */
5112                         ring_freq = max(min_ring_freq, gpu_freq);
5113                 } else if (IS_HASWELL(dev)) {
5114                         ring_freq = mult_frac(gpu_freq, 5, 4);
5115                         ring_freq = max(min_ring_freq, ring_freq);
5116                         /* leave ia_freq as the default, chosen by cpufreq */
5117                 } else {
5118                         /* On older processors, there is no separate ring
5119                          * clock domain, so in order to boost the bandwidth
5120                          * of the ring, we need to upclock the CPU (ia_freq).
5121                          *
5122                          * For GPU frequencies less than 750MHz,
5123                          * just use the lowest ring freq.
5124                          */
5125                         if (gpu_freq < min_freq)
5126                                 ia_freq = 800;
5127                         else
5128                                 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5129                         ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5130                 }
5131
5132                 sandybridge_pcode_write(dev_priv,
5133                                         GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
5134                                         ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5135                                         ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5136                                         gpu_freq);
5137         }
5138 }
5139
5140 void gen6_update_ring_freq(struct drm_device *dev)
5141 {
5142         struct drm_i915_private *dev_priv = dev->dev_private;
5143
5144         if (!HAS_CORE_RING_FREQ(dev))
5145                 return;
5146
5147         mutex_lock(&dev_priv->rps.hw_lock);
5148         __gen6_update_ring_freq(dev);
5149         mutex_unlock(&dev_priv->rps.hw_lock);
5150 }
5151
5152 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
5153 {
5154         struct drm_device *dev = dev_priv->dev;
5155         u32 val, rp0;
5156
5157         val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5158
5159         switch (INTEL_INFO(dev)->eu_total) {
5160         case 8:
5161                 /* (2 * 4) config */
5162                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5163                 break;
5164         case 12:
5165                 /* (2 * 6) config */
5166                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5167                 break;
5168         case 16:
5169                 /* (2 * 8) config */
5170         default:
5171                 /* Setting (2 * 8) Min RP0 for any other combination */
5172                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5173                 break;
5174         }
5175
5176         rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5177
5178         return rp0;
5179 }
5180
5181 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5182 {
5183         u32 val, rpe;
5184
5185         val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5186         rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5187
5188         return rpe;
5189 }
5190
5191 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5192 {
5193         u32 val, rp1;
5194
5195         val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5196         rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5197
5198         return rp1;
5199 }
5200
5201 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5202 {
5203         u32 val, rp1;
5204
5205         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5206
5207         rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5208
5209         return rp1;
5210 }
5211
5212 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
5213 {
5214         u32 val, rp0;
5215
5216         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5217
5218         rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5219         /* Clamp to max */
5220         rp0 = min_t(u32, rp0, 0xea);
5221
5222         return rp0;
5223 }
5224
5225 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5226 {
5227         u32 val, rpe;
5228
5229         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
5230         rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
5231         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
5232         rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5233
5234         return rpe;
5235 }
5236
5237 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
5238 {
5239         return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5240 }
5241
5242 /* Check that the pctx buffer wasn't move under us. */
5243 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5244 {
5245         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5246
5247         WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5248                              dev_priv->vlv_pctx->stolen->start);
5249 }
5250
5251
5252 /* Check that the pcbr address is not empty. */
5253 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5254 {
5255         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5256
5257         WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5258 }
5259
5260 static void cherryview_setup_pctx(struct drm_device *dev)
5261 {
5262         struct drm_i915_private *dev_priv = dev->dev_private;
5263         unsigned long pctx_paddr, paddr;
5264         struct i915_gtt *gtt = &dev_priv->gtt;
5265         u32 pcbr;
5266         int pctx_size = 32*1024;
5267
5268         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
5269
5270         pcbr = I915_READ(VLV_PCBR);
5271         if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
5272                 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5273                 paddr = (dev_priv->mm.stolen_base +
5274                          (gtt->stolen_size - pctx_size));
5275
5276                 pctx_paddr = (paddr & (~4095));
5277                 I915_WRITE(VLV_PCBR, pctx_paddr);
5278         }
5279
5280         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5281 }
5282
5283 static void valleyview_setup_pctx(struct drm_device *dev)
5284 {
5285         struct drm_i915_private *dev_priv = dev->dev_private;
5286         struct drm_i915_gem_object *pctx;
5287         unsigned long pctx_paddr;
5288         u32 pcbr;
5289         int pctx_size = 24*1024;
5290
5291         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
5292
5293         pcbr = I915_READ(VLV_PCBR);
5294         if (pcbr) {
5295                 /* BIOS set it up already, grab the pre-alloc'd space */
5296                 int pcbr_offset;
5297
5298                 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5299                 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
5300                                                                       pcbr_offset,
5301                                                                       I915_GTT_OFFSET_NONE,
5302                                                                       pctx_size);
5303                 goto out;
5304         }
5305
5306         DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5307
5308         /*
5309          * From the Gunit register HAS:
5310          * The Gfx driver is expected to program this register and ensure
5311          * proper allocation within Gfx stolen memory.  For example, this
5312          * register should be programmed such than the PCBR range does not
5313          * overlap with other ranges, such as the frame buffer, protected
5314          * memory, or any other relevant ranges.
5315          */
5316         pctx = i915_gem_object_create_stolen(dev, pctx_size);
5317         if (!pctx) {
5318                 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5319                 return;
5320         }
5321
5322         pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5323         I915_WRITE(VLV_PCBR, pctx_paddr);
5324
5325 out:
5326         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5327         dev_priv->vlv_pctx = pctx;
5328 }
5329
5330 static void valleyview_cleanup_pctx(struct drm_device *dev)
5331 {
5332         struct drm_i915_private *dev_priv = dev->dev_private;
5333
5334         if (WARN_ON(!dev_priv->vlv_pctx))
5335                 return;
5336
5337         drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
5338         dev_priv->vlv_pctx = NULL;
5339 }
5340
5341 static void valleyview_init_gt_powersave(struct drm_device *dev)
5342 {
5343         struct drm_i915_private *dev_priv = dev->dev_private;
5344         u32 val;
5345
5346         valleyview_setup_pctx(dev);
5347
5348         mutex_lock(&dev_priv->rps.hw_lock);
5349
5350         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5351         switch ((val >> 6) & 3) {
5352         case 0:
5353         case 1:
5354                 dev_priv->mem_freq = 800;
5355                 break;
5356         case 2:
5357                 dev_priv->mem_freq = 1066;
5358                 break;
5359         case 3:
5360                 dev_priv->mem_freq = 1333;
5361                 break;
5362         }
5363         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5364
5365         dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5366         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5367         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5368                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5369                          dev_priv->rps.max_freq);
5370
5371         dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5372         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5373                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5374                          dev_priv->rps.efficient_freq);
5375
5376         dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5377         DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
5378                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5379                          dev_priv->rps.rp1_freq);
5380
5381         dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5382         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5383                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5384                          dev_priv->rps.min_freq);
5385
5386         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5387
5388         /* Preserve min/max settings in case of re-init */
5389         if (dev_priv->rps.max_freq_softlimit == 0)
5390                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5391
5392         if (dev_priv->rps.min_freq_softlimit == 0)
5393                 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5394
5395         mutex_unlock(&dev_priv->rps.hw_lock);
5396 }
5397
5398 static void cherryview_init_gt_powersave(struct drm_device *dev)
5399 {
5400         struct drm_i915_private *dev_priv = dev->dev_private;
5401         u32 val;
5402
5403         cherryview_setup_pctx(dev);
5404
5405         mutex_lock(&dev_priv->rps.hw_lock);
5406
5407         mutex_lock(&dev_priv->sb_lock);
5408         val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
5409         mutex_unlock(&dev_priv->sb_lock);
5410
5411         switch ((val >> 2) & 0x7) {
5412         case 3:
5413                 dev_priv->mem_freq = 2000;
5414                 break;
5415         default:
5416                 dev_priv->mem_freq = 1600;
5417                 break;
5418         }
5419         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5420
5421         dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5422         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5423         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5424                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5425                          dev_priv->rps.max_freq);
5426
5427         dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5428         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5429                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5430                          dev_priv->rps.efficient_freq);
5431
5432         dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5433         DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
5434                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5435                          dev_priv->rps.rp1_freq);
5436
5437         /* PUnit validated range is only [RPe, RP0] */
5438         dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
5439         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5440                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5441                          dev_priv->rps.min_freq);
5442
5443         WARN_ONCE((dev_priv->rps.max_freq |
5444                    dev_priv->rps.efficient_freq |
5445                    dev_priv->rps.rp1_freq |
5446                    dev_priv->rps.min_freq) & 1,
5447                   "Odd GPU freq values\n");
5448
5449         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5450
5451         /* Preserve min/max settings in case of re-init */
5452         if (dev_priv->rps.max_freq_softlimit == 0)
5453                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5454
5455         if (dev_priv->rps.min_freq_softlimit == 0)
5456                 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5457
5458         mutex_unlock(&dev_priv->rps.hw_lock);
5459 }
5460
5461 static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
5462 {
5463         valleyview_cleanup_pctx(dev);
5464 }
5465
5466 static void cherryview_enable_rps(struct drm_device *dev)
5467 {
5468         struct drm_i915_private *dev_priv = dev->dev_private;
5469         struct intel_engine_cs *ring;
5470         u32 gtfifodbg, val, rc6_mode = 0, pcbr;
5471         int i;
5472
5473         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5474
5475         gtfifodbg = I915_READ(GTFIFODBG);
5476         if (gtfifodbg) {
5477                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5478                                  gtfifodbg);
5479                 I915_WRITE(GTFIFODBG, gtfifodbg);
5480         }
5481
5482         cherryview_check_pctx(dev_priv);
5483
5484         /* 1a & 1b: Get forcewake during program sequence. Although the driver
5485          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5486         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5487
5488         /*  Disable RC states. */
5489         I915_WRITE(GEN6_RC_CONTROL, 0);
5490
5491         /* 2a: Program RC6 thresholds.*/
5492         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5493         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5494         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5495
5496         for_each_ring(ring, dev_priv, i)
5497                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5498         I915_WRITE(GEN6_RC_SLEEP, 0);
5499
5500         /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5501         I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
5502
5503         /* allows RC6 residency counter to work */
5504         I915_WRITE(VLV_COUNTER_CONTROL,
5505                    _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5506                                       VLV_MEDIA_RC6_COUNT_EN |
5507                                       VLV_RENDER_RC6_COUNT_EN));
5508
5509         /* For now we assume BIOS is allocating and populating the PCBR  */
5510         pcbr = I915_READ(VLV_PCBR);
5511
5512         /* 3: Enable RC6 */
5513         if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
5514                                                 (pcbr >> VLV_PCBR_ADDR_SHIFT))
5515                 rc6_mode = GEN7_RC_CTL_TO_MODE;
5516
5517         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5518
5519         /* 4 Program defaults and thresholds for RPS*/
5520         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5521         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5522         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5523         I915_WRITE(GEN6_RP_UP_EI, 66000);
5524         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5525
5526         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5527
5528         /* 5: Enable RPS */
5529         I915_WRITE(GEN6_RP_CONTROL,
5530                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
5531                    GEN6_RP_MEDIA_IS_GFX |
5532                    GEN6_RP_ENABLE |
5533                    GEN6_RP_UP_BUSY_AVG |
5534                    GEN6_RP_DOWN_IDLE_AVG);
5535
5536         /* Setting Fixed Bias */
5537         val = VLV_OVERRIDE_EN |
5538                   VLV_SOC_TDP_EN |
5539                   CHV_BIAS_CPU_50_SOC_50;
5540         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5541
5542         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5543
5544         /* RPS code assumes GPLL is used */
5545         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5546
5547         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
5548         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5549
5550         dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5551         DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5552                          intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5553                          dev_priv->rps.cur_freq);
5554
5555         DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5556                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5557                          dev_priv->rps.efficient_freq);
5558
5559         valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5560
5561         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5562 }
5563
5564 static void valleyview_enable_rps(struct drm_device *dev)
5565 {
5566         struct drm_i915_private *dev_priv = dev->dev_private;
5567         struct intel_engine_cs *ring;
5568         u32 gtfifodbg, val, rc6_mode = 0;
5569         int i;
5570
5571         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5572
5573         valleyview_check_pctx(dev_priv);
5574
5575         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
5576                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5577                                  gtfifodbg);
5578                 I915_WRITE(GTFIFODBG, gtfifodbg);
5579         }
5580
5581         /* If VLV, Forcewake all wells, else re-direct to regular path */
5582         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5583
5584         /*  Disable RC states. */
5585         I915_WRITE(GEN6_RC_CONTROL, 0);
5586
5587         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5588         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5589         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5590         I915_WRITE(GEN6_RP_UP_EI, 66000);
5591         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5592
5593         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5594
5595         I915_WRITE(GEN6_RP_CONTROL,
5596                    GEN6_RP_MEDIA_TURBO |
5597                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
5598                    GEN6_RP_MEDIA_IS_GFX |
5599                    GEN6_RP_ENABLE |
5600                    GEN6_RP_UP_BUSY_AVG |
5601                    GEN6_RP_DOWN_IDLE_CONT);
5602
5603         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5604         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5605         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5606
5607         for_each_ring(ring, dev_priv, i)
5608                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5609
5610         I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
5611
5612         /* allows RC6 residency counter to work */
5613         I915_WRITE(VLV_COUNTER_CONTROL,
5614                    _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5615                                       VLV_RENDER_RC0_COUNT_EN |
5616                                       VLV_MEDIA_RC6_COUNT_EN |
5617                                       VLV_RENDER_RC6_COUNT_EN));
5618
5619         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
5620                 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
5621
5622         intel_print_rc6_info(dev, rc6_mode);
5623
5624         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5625
5626         /* Setting Fixed Bias */
5627         val = VLV_OVERRIDE_EN |
5628                   VLV_SOC_TDP_EN |
5629                   VLV_BIAS_CPU_125_SOC_875;
5630         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5631
5632         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5633
5634         /* RPS code assumes GPLL is used */
5635         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5636
5637         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
5638         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5639
5640         dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5641         DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5642                          intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5643                          dev_priv->rps.cur_freq);
5644
5645         DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5646                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5647                          dev_priv->rps.efficient_freq);
5648
5649         valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5650
5651         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5652 }
5653
5654 static unsigned long intel_pxfreq(u32 vidfreq)
5655 {
5656         unsigned long freq;
5657         int div = (vidfreq & 0x3f0000) >> 16;
5658         int post = (vidfreq & 0x3000) >> 12;
5659         int pre = (vidfreq & 0x7);
5660
5661         if (!pre)
5662                 return 0;
5663
5664         freq = ((div * 133333) / ((1<<post) * pre));
5665
5666         return freq;
5667 }
5668
5669 static const struct cparams {
5670         u16 i;
5671         u16 t;
5672         u16 m;
5673         u16 c;
5674 } cparams[] = {
5675         { 1, 1333, 301, 28664 },
5676         { 1, 1066, 294, 24460 },
5677         { 1, 800, 294, 25192 },
5678         { 0, 1333, 276, 27605 },
5679         { 0, 1066, 276, 27605 },
5680         { 0, 800, 231, 23784 },
5681 };
5682
5683 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
5684 {
5685         u64 total_count, diff, ret;
5686         u32 count1, count2, count3, m = 0, c = 0;
5687         unsigned long now = jiffies_to_msecs(jiffies), diff1;
5688         int i;
5689
5690         assert_spin_locked(&mchdev_lock);
5691
5692         diff1 = now - dev_priv->ips.last_time1;
5693
5694         /* Prevent division-by-zero if we are asking too fast.
5695          * Also, we don't get interesting results if we are polling
5696          * faster than once in 10ms, so just return the saved value
5697          * in such cases.
5698          */
5699         if (diff1 <= 10)
5700                 return dev_priv->ips.chipset_power;
5701
5702         count1 = I915_READ(DMIEC);
5703         count2 = I915_READ(DDREC);
5704         count3 = I915_READ(CSIEC);
5705
5706         total_count = count1 + count2 + count3;
5707
5708         /* FIXME: handle per-counter overflow */
5709         if (total_count < dev_priv->ips.last_count1) {
5710                 diff = ~0UL - dev_priv->ips.last_count1;
5711                 diff += total_count;
5712         } else {
5713                 diff = total_count - dev_priv->ips.last_count1;
5714         }
5715
5716         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
5717                 if (cparams[i].i == dev_priv->ips.c_m &&
5718                     cparams[i].t == dev_priv->ips.r_t) {
5719                         m = cparams[i].m;
5720                         c = cparams[i].c;
5721                         break;
5722                 }
5723         }
5724
5725         diff = div_u64(diff, diff1);
5726         ret = ((m * diff) + c);
5727         ret = div_u64(ret, 10);
5728
5729         dev_priv->ips.last_count1 = total_count;
5730         dev_priv->ips.last_time1 = now;
5731
5732         dev_priv->ips.chipset_power = ret;
5733
5734         return ret;
5735 }
5736
5737 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
5738 {
5739         struct drm_device *dev = dev_priv->dev;
5740         unsigned long val;
5741
5742         if (INTEL_INFO(dev)->gen != 5)
5743                 return 0;
5744
5745         spin_lock_irq(&mchdev_lock);
5746
5747         val = __i915_chipset_val(dev_priv);
5748
5749         spin_unlock_irq(&mchdev_lock);
5750
5751         return val;
5752 }
5753
5754 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
5755 {
5756         unsigned long m, x, b;
5757         u32 tsfs;
5758
5759         tsfs = I915_READ(TSFS);
5760
5761         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
5762         x = I915_READ8(TR1);
5763
5764         b = tsfs & TSFS_INTR_MASK;
5765
5766         return ((m * x) / 127) - b;
5767 }
5768
5769 static int _pxvid_to_vd(u8 pxvid)
5770 {
5771         if (pxvid == 0)
5772                 return 0;
5773
5774         if (pxvid >= 8 && pxvid < 31)
5775                 pxvid = 31;
5776
5777         return (pxvid + 2) * 125;
5778 }
5779
5780 static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
5781 {
5782         struct drm_device *dev = dev_priv->dev;
5783         const int vd = _pxvid_to_vd(pxvid);
5784         const int vm = vd - 1125;
5785
5786         if (INTEL_INFO(dev)->is_mobile)
5787                 return vm > 0 ? vm : 0;
5788
5789         return vd;
5790 }
5791
5792 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
5793 {
5794         u64 now, diff, diffms;
5795         u32 count;
5796
5797         assert_spin_locked(&mchdev_lock);
5798
5799         now = ktime_get_raw_ns();
5800         diffms = now - dev_priv->ips.last_time2;
5801         do_div(diffms, NSEC_PER_MSEC);
5802
5803         /* Don't divide by 0 */
5804         if (!diffms)
5805                 return;
5806
5807         count = I915_READ(GFXEC);
5808
5809         if (count < dev_priv->ips.last_count2) {
5810                 diff = ~0UL - dev_priv->ips.last_count2;
5811                 diff += count;
5812         } else {
5813                 diff = count - dev_priv->ips.last_count2;
5814         }
5815
5816         dev_priv->ips.last_count2 = count;
5817         dev_priv->ips.last_time2 = now;
5818
5819         /* More magic constants... */
5820         diff = diff * 1181;
5821         diff = div_u64(diff, diffms * 10);
5822         dev_priv->ips.gfx_power = diff;
5823 }
5824
5825 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
5826 {
5827         struct drm_device *dev = dev_priv->dev;
5828
5829         if (INTEL_INFO(dev)->gen != 5)
5830                 return;
5831
5832         spin_lock_irq(&mchdev_lock);
5833
5834         __i915_update_gfx_val(dev_priv);
5835
5836         spin_unlock_irq(&mchdev_lock);
5837 }
5838
5839 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
5840 {
5841         unsigned long t, corr, state1, corr2, state2;
5842         u32 pxvid, ext_v;
5843
5844         assert_spin_locked(&mchdev_lock);
5845
5846         pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
5847         pxvid = (pxvid >> 24) & 0x7f;
5848         ext_v = pvid_to_extvid(dev_priv, pxvid);
5849
5850         state1 = ext_v;
5851
5852         t = i915_mch_val(dev_priv);
5853
5854         /* Revel in the empirically derived constants */
5855
5856         /* Correction factor in 1/100000 units */
5857         if (t > 80)
5858                 corr = ((t * 2349) + 135940);
5859         else if (t >= 50)
5860                 corr = ((t * 964) + 29317);
5861         else /* < 50 */
5862                 corr = ((t * 301) + 1004);
5863
5864         corr = corr * ((150142 * state1) / 10000 - 78642);
5865         corr /= 100000;
5866         corr2 = (corr * dev_priv->ips.corr);
5867
5868         state2 = (corr2 * state1) / 10000;
5869         state2 /= 100; /* convert to mW */
5870
5871         __i915_update_gfx_val(dev_priv);
5872
5873         return dev_priv->ips.gfx_power + state2;
5874 }
5875
5876 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
5877 {
5878         struct drm_device *dev = dev_priv->dev;
5879         unsigned long val;
5880
5881         if (INTEL_INFO(dev)->gen != 5)
5882                 return 0;
5883
5884         spin_lock_irq(&mchdev_lock);
5885
5886         val = __i915_gfx_val(dev_priv);
5887
5888         spin_unlock_irq(&mchdev_lock);
5889
5890         return val;
5891 }
5892
5893 /**
5894  * i915_read_mch_val - return value for IPS use
5895  *
5896  * Calculate and return a value for the IPS driver to use when deciding whether
5897  * we have thermal and power headroom to increase CPU or GPU power budget.
5898  */
5899 unsigned long i915_read_mch_val(void)
5900 {
5901         struct drm_i915_private *dev_priv;
5902         unsigned long chipset_val, graphics_val, ret = 0;
5903
5904         spin_lock_irq(&mchdev_lock);
5905         if (!i915_mch_dev)
5906                 goto out_unlock;
5907         dev_priv = i915_mch_dev;
5908
5909         chipset_val = __i915_chipset_val(dev_priv);
5910         graphics_val = __i915_gfx_val(dev_priv);
5911
5912         ret = chipset_val + graphics_val;
5913
5914 out_unlock:
5915         spin_unlock_irq(&mchdev_lock);
5916
5917         return ret;
5918 }
5919 EXPORT_SYMBOL_GPL(i915_read_mch_val);
5920
5921 /**
5922  * i915_gpu_raise - raise GPU frequency limit
5923  *
5924  * Raise the limit; IPS indicates we have thermal headroom.
5925  */
5926 bool i915_gpu_raise(void)
5927 {
5928         struct drm_i915_private *dev_priv;
5929         bool ret = true;
5930
5931         spin_lock_irq(&mchdev_lock);
5932         if (!i915_mch_dev) {
5933                 ret = false;
5934                 goto out_unlock;
5935         }
5936         dev_priv = i915_mch_dev;
5937
5938         if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
5939                 dev_priv->ips.max_delay--;
5940
5941 out_unlock:
5942         spin_unlock_irq(&mchdev_lock);
5943
5944         return ret;
5945 }
5946 EXPORT_SYMBOL_GPL(i915_gpu_raise);
5947
5948 /**
5949  * i915_gpu_lower - lower GPU frequency limit
5950  *
5951  * IPS indicates we're close to a thermal limit, so throttle back the GPU
5952  * frequency maximum.
5953  */
5954 bool i915_gpu_lower(void)
5955 {
5956         struct drm_i915_private *dev_priv;
5957         bool ret = true;
5958
5959         spin_lock_irq(&mchdev_lock);
5960         if (!i915_mch_dev) {
5961                 ret = false;
5962                 goto out_unlock;
5963         }
5964         dev_priv = i915_mch_dev;
5965
5966         if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
5967                 dev_priv->ips.max_delay++;
5968
5969 out_unlock:
5970         spin_unlock_irq(&mchdev_lock);
5971
5972         return ret;
5973 }
5974 EXPORT_SYMBOL_GPL(i915_gpu_lower);
5975
5976 /**
5977  * i915_gpu_busy - indicate GPU business to IPS
5978  *
5979  * Tell the IPS driver whether or not the GPU is busy.
5980  */
5981 bool i915_gpu_busy(void)
5982 {
5983         struct drm_i915_private *dev_priv;
5984         struct intel_engine_cs *ring;
5985         bool ret = false;
5986         int i;
5987
5988         spin_lock_irq(&mchdev_lock);
5989         if (!i915_mch_dev)
5990                 goto out_unlock;
5991         dev_priv = i915_mch_dev;
5992
5993         for_each_ring(ring, dev_priv, i)
5994                 ret |= !list_empty(&ring->request_list);
5995
5996 out_unlock:
5997         spin_unlock_irq(&mchdev_lock);
5998
5999         return ret;
6000 }
6001 EXPORT_SYMBOL_GPL(i915_gpu_busy);
6002
6003 /**
6004  * i915_gpu_turbo_disable - disable graphics turbo
6005  *
6006  * Disable graphics turbo by resetting the max frequency and setting the
6007  * current frequency to the default.
6008  */
6009 bool i915_gpu_turbo_disable(void)
6010 {
6011         struct drm_i915_private *dev_priv;
6012         bool ret = true;
6013
6014         spin_lock_irq(&mchdev_lock);
6015         if (!i915_mch_dev) {
6016                 ret = false;
6017                 goto out_unlock;
6018         }
6019         dev_priv = i915_mch_dev;
6020
6021         dev_priv->ips.max_delay = dev_priv->ips.fstart;
6022
6023         if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
6024                 ret = false;
6025
6026 out_unlock:
6027         spin_unlock_irq(&mchdev_lock);
6028
6029         return ret;
6030 }
6031 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6032
6033 /**
6034  * Tells the intel_ips driver that the i915 driver is now loaded, if
6035  * IPS got loaded first.
6036  *
6037  * This awkward dance is so that neither module has to depend on the
6038  * other in order for IPS to do the appropriate communication of
6039  * GPU turbo limits to i915.
6040  */
6041 static void
6042 ips_ping_for_i915_load(void)
6043 {
6044         void (*link)(void);
6045
6046         link = symbol_get(ips_link_to_i915_driver);
6047         if (link) {
6048                 link();
6049                 symbol_put(ips_link_to_i915_driver);
6050         }
6051 }
6052
6053 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6054 {
6055         /* We only register the i915 ips part with intel-ips once everything is
6056          * set up, to avoid intel-ips sneaking in and reading bogus values. */
6057         spin_lock_irq(&mchdev_lock);
6058         i915_mch_dev = dev_priv;
6059         spin_unlock_irq(&mchdev_lock);
6060
6061         ips_ping_for_i915_load();
6062 }
6063
6064 void intel_gpu_ips_teardown(void)
6065 {
6066         spin_lock_irq(&mchdev_lock);
6067         i915_mch_dev = NULL;
6068         spin_unlock_irq(&mchdev_lock);
6069 }
6070
6071 static void intel_init_emon(struct drm_device *dev)
6072 {
6073         struct drm_i915_private *dev_priv = dev->dev_private;
6074         u32 lcfuse;
6075         u8 pxw[16];
6076         int i;
6077
6078         /* Disable to program */
6079         I915_WRITE(ECR, 0);
6080         POSTING_READ(ECR);
6081
6082         /* Program energy weights for various events */
6083         I915_WRITE(SDEW, 0x15040d00);
6084         I915_WRITE(CSIEW0, 0x007f0000);
6085         I915_WRITE(CSIEW1, 0x1e220004);
6086         I915_WRITE(CSIEW2, 0x04000004);
6087
6088         for (i = 0; i < 5; i++)
6089                 I915_WRITE(PEW(i), 0);
6090         for (i = 0; i < 3; i++)
6091                 I915_WRITE(DEW(i), 0);
6092
6093         /* Program P-state weights to account for frequency power adjustment */
6094         for (i = 0; i < 16; i++) {
6095                 u32 pxvidfreq = I915_READ(PXVFREQ(i));
6096                 unsigned long freq = intel_pxfreq(pxvidfreq);
6097                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6098                         PXVFREQ_PX_SHIFT;
6099                 unsigned long val;
6100
6101                 val = vid * vid;
6102                 val *= (freq / 1000);
6103                 val *= 255;
6104                 val /= (127*127*900);
6105                 if (val > 0xff)
6106                         DRM_ERROR("bad pxval: %ld\n", val);
6107                 pxw[i] = val;
6108         }
6109         /* Render standby states get 0 weight */
6110         pxw[14] = 0;
6111         pxw[15] = 0;
6112
6113         for (i = 0; i < 4; i++) {
6114                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6115                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6116                 I915_WRITE(PXW(i), val);
6117         }
6118
6119         /* Adjust magic regs to magic values (more experimental results) */
6120         I915_WRITE(OGW0, 0);
6121         I915_WRITE(OGW1, 0);
6122         I915_WRITE(EG0, 0x00007f00);
6123         I915_WRITE(EG1, 0x0000000e);
6124         I915_WRITE(EG2, 0x000e0000);
6125         I915_WRITE(EG3, 0x68000300);
6126         I915_WRITE(EG4, 0x42000000);
6127         I915_WRITE(EG5, 0x00140031);
6128         I915_WRITE(EG6, 0);
6129         I915_WRITE(EG7, 0);
6130
6131         for (i = 0; i < 8; i++)
6132                 I915_WRITE(PXWL(i), 0);
6133
6134         /* Enable PMON + select events */
6135         I915_WRITE(ECR, 0x80000019);
6136
6137         lcfuse = I915_READ(LCFUSE02);
6138
6139         dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
6140 }
6141
6142 void intel_init_gt_powersave(struct drm_device *dev)
6143 {
6144         i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
6145
6146         if (IS_CHERRYVIEW(dev))
6147                 cherryview_init_gt_powersave(dev);
6148         else if (IS_VALLEYVIEW(dev))
6149                 valleyview_init_gt_powersave(dev);
6150 }
6151
6152 void intel_cleanup_gt_powersave(struct drm_device *dev)
6153 {
6154         if (IS_CHERRYVIEW(dev))
6155                 return;
6156         else if (IS_VALLEYVIEW(dev))
6157                 valleyview_cleanup_gt_powersave(dev);
6158 }
6159
6160 static void gen6_suspend_rps(struct drm_device *dev)
6161 {
6162         struct drm_i915_private *dev_priv = dev->dev_private;
6163
6164         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
6165
6166         gen6_disable_rps_interrupts(dev);
6167 }
6168
6169 /**
6170  * intel_suspend_gt_powersave - suspend PM work and helper threads
6171  * @dev: drm device
6172  *
6173  * We don't want to disable RC6 or other features here, we just want
6174  * to make sure any work we've queued has finished and won't bother
6175  * us while we're suspended.
6176  */
6177 void intel_suspend_gt_powersave(struct drm_device *dev)
6178 {
6179         struct drm_i915_private *dev_priv = dev->dev_private;
6180
6181         if (INTEL_INFO(dev)->gen < 6)
6182                 return;
6183
6184         gen6_suspend_rps(dev);
6185
6186         /* Force GPU to min freq during suspend */
6187         gen6_rps_idle(dev_priv);
6188 }
6189
6190 void intel_disable_gt_powersave(struct drm_device *dev)
6191 {
6192         struct drm_i915_private *dev_priv = dev->dev_private;
6193
6194         if (IS_IRONLAKE_M(dev)) {
6195                 ironlake_disable_drps(dev);
6196         } else if (INTEL_INFO(dev)->gen >= 6) {
6197                 intel_suspend_gt_powersave(dev);
6198
6199                 mutex_lock(&dev_priv->rps.hw_lock);
6200                 if (INTEL_INFO(dev)->gen >= 9)
6201                         gen9_disable_rps(dev);
6202                 else if (IS_CHERRYVIEW(dev))
6203                         cherryview_disable_rps(dev);
6204                 else if (IS_VALLEYVIEW(dev))
6205                         valleyview_disable_rps(dev);
6206                 else
6207                         gen6_disable_rps(dev);
6208
6209                 dev_priv->rps.enabled = false;
6210                 mutex_unlock(&dev_priv->rps.hw_lock);
6211         }
6212 }
6213
6214 static void intel_gen6_powersave_work(struct work_struct *work)
6215 {
6216         struct drm_i915_private *dev_priv =
6217                 container_of(work, struct drm_i915_private,
6218                              rps.delayed_resume_work.work);
6219         struct drm_device *dev = dev_priv->dev;
6220
6221         mutex_lock(&dev_priv->rps.hw_lock);
6222
6223         gen6_reset_rps_interrupts(dev);
6224
6225         if (IS_CHERRYVIEW(dev)) {
6226                 cherryview_enable_rps(dev);
6227         } else if (IS_VALLEYVIEW(dev)) {
6228                 valleyview_enable_rps(dev);
6229         } else if (INTEL_INFO(dev)->gen >= 9) {
6230                 gen9_enable_rc6(dev);
6231                 gen9_enable_rps(dev);
6232                 if (IS_SKYLAKE(dev))
6233                         __gen6_update_ring_freq(dev);
6234         } else if (IS_BROADWELL(dev)) {
6235                 gen8_enable_rps(dev);
6236                 __gen6_update_ring_freq(dev);
6237         } else {
6238                 gen6_enable_rps(dev);
6239                 __gen6_update_ring_freq(dev);
6240         }
6241
6242         WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6243         WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6244
6245         WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6246         WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6247
6248         dev_priv->rps.enabled = true;
6249
6250         gen6_enable_rps_interrupts(dev);
6251
6252         mutex_unlock(&dev_priv->rps.hw_lock);
6253
6254         intel_runtime_pm_put(dev_priv);
6255 }
6256
6257 void intel_enable_gt_powersave(struct drm_device *dev)
6258 {
6259         struct drm_i915_private *dev_priv = dev->dev_private;
6260
6261         /* Powersaving is controlled by the host when inside a VM */
6262         if (intel_vgpu_active(dev))
6263                 return;
6264
6265         if (IS_IRONLAKE_M(dev)) {
6266                 mutex_lock(&dev->struct_mutex);
6267                 ironlake_enable_drps(dev);
6268                 intel_init_emon(dev);
6269                 mutex_unlock(&dev->struct_mutex);
6270         } else if (INTEL_INFO(dev)->gen >= 6) {
6271                 /*
6272                  * PCU communication is slow and this doesn't need to be
6273                  * done at any specific time, so do this out of our fast path
6274                  * to make resume and init faster.
6275                  *
6276                  * We depend on the HW RC6 power context save/restore
6277                  * mechanism when entering D3 through runtime PM suspend. So
6278                  * disable RPM until RPS/RC6 is properly setup. We can only
6279                  * get here via the driver load/system resume/runtime resume
6280                  * paths, so the _noresume version is enough (and in case of
6281                  * runtime resume it's necessary).
6282                  */
6283                 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
6284                                            round_jiffies_up_relative(HZ)))
6285                         intel_runtime_pm_get_noresume(dev_priv);
6286         }
6287 }
6288
6289 void intel_reset_gt_powersave(struct drm_device *dev)
6290 {
6291         struct drm_i915_private *dev_priv = dev->dev_private;
6292
6293         if (INTEL_INFO(dev)->gen < 6)
6294                 return;
6295
6296         gen6_suspend_rps(dev);
6297         dev_priv->rps.enabled = false;
6298 }
6299
6300 static void ibx_init_clock_gating(struct drm_device *dev)
6301 {
6302         struct drm_i915_private *dev_priv = dev->dev_private;
6303
6304         /*
6305          * On Ibex Peak and Cougar Point, we need to disable clock
6306          * gating for the panel power sequencer or it will fail to
6307          * start up when no ports are active.
6308          */
6309         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6310 }
6311
6312 static void g4x_disable_trickle_feed(struct drm_device *dev)
6313 {
6314         struct drm_i915_private *dev_priv = dev->dev_private;
6315         enum pipe pipe;
6316
6317         for_each_pipe(dev_priv, pipe) {
6318                 I915_WRITE(DSPCNTR(pipe),
6319                            I915_READ(DSPCNTR(pipe)) |
6320                            DISPPLANE_TRICKLE_FEED_DISABLE);
6321
6322                 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6323                 POSTING_READ(DSPSURF(pipe));
6324         }
6325 }
6326
6327 static void ilk_init_lp_watermarks(struct drm_device *dev)
6328 {
6329         struct drm_i915_private *dev_priv = dev->dev_private;
6330
6331         I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6332         I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6333         I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6334
6335         /*
6336          * Don't touch WM1S_LP_EN here.
6337          * Doing so could cause underruns.
6338          */
6339 }
6340
6341 static void ironlake_init_clock_gating(struct drm_device *dev)
6342 {
6343         struct drm_i915_private *dev_priv = dev->dev_private;
6344         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6345
6346         /*
6347          * Required for FBC
6348          * WaFbcDisableDpfcClockGating:ilk
6349          */
6350         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6351                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6352                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6353
6354         I915_WRITE(PCH_3DCGDIS0,
6355                    MARIUNIT_CLOCK_GATE_DISABLE |
6356                    SVSMUNIT_CLOCK_GATE_DISABLE);
6357         I915_WRITE(PCH_3DCGDIS1,
6358                    VFMUNIT_CLOCK_GATE_DISABLE);
6359
6360         /*
6361          * According to the spec the following bits should be set in
6362          * order to enable memory self-refresh
6363          * The bit 22/21 of 0x42004
6364          * The bit 5 of 0x42020
6365          * The bit 15 of 0x45000
6366          */
6367         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6368                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
6369                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
6370         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6371         I915_WRITE(DISP_ARB_CTL,
6372                    (I915_READ(DISP_ARB_CTL) |
6373                     DISP_FBC_WM_DIS));
6374
6375         ilk_init_lp_watermarks(dev);
6376
6377         /*
6378          * Based on the document from hardware guys the following bits
6379          * should be set unconditionally in order to enable FBC.
6380          * The bit 22 of 0x42000
6381          * The bit 22 of 0x42004
6382          * The bit 7,8,9 of 0x42020.
6383          */
6384         if (IS_IRONLAKE_M(dev)) {
6385                 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6386                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6387                            I915_READ(ILK_DISPLAY_CHICKEN1) |
6388                            ILK_FBCQ_DIS);
6389                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6390                            I915_READ(ILK_DISPLAY_CHICKEN2) |
6391                            ILK_DPARB_GATE);
6392         }
6393
6394         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6395
6396         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6397                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6398                    ILK_ELPIN_409_SELECT);
6399         I915_WRITE(_3D_CHICKEN2,
6400                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6401                    _3D_CHICKEN2_WM_READ_PIPELINED);
6402
6403         /* WaDisableRenderCachePipelinedFlush:ilk */
6404         I915_WRITE(CACHE_MODE_0,
6405                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6406
6407         /* WaDisable_RenderCache_OperationalFlush:ilk */
6408         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6409
6410         g4x_disable_trickle_feed(dev);
6411
6412         ibx_init_clock_gating(dev);
6413 }
6414
6415 static void cpt_init_clock_gating(struct drm_device *dev)
6416 {
6417         struct drm_i915_private *dev_priv = dev->dev_private;
6418         int pipe;
6419         uint32_t val;
6420
6421         /*
6422          * On Ibex Peak and Cougar Point, we need to disable clock
6423          * gating for the panel power sequencer or it will fail to
6424          * start up when no ports are active.
6425          */
6426         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6427                    PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6428                    PCH_CPUNIT_CLOCK_GATE_DISABLE);
6429         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6430                    DPLS_EDP_PPS_FIX_DIS);
6431         /* The below fixes the weird display corruption, a few pixels shifted
6432          * downward, on (only) LVDS of some HP laptops with IVY.
6433          */
6434         for_each_pipe(dev_priv, pipe) {
6435                 val = I915_READ(TRANS_CHICKEN2(pipe));
6436                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6437                 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6438                 if (dev_priv->vbt.fdi_rx_polarity_inverted)
6439                         val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6440                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6441                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6442                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
6443                 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6444         }
6445         /* WADP0ClockGatingDisable */
6446         for_each_pipe(dev_priv, pipe) {
6447                 I915_WRITE(TRANS_CHICKEN1(pipe),
6448                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6449         }
6450 }
6451
6452 static void gen6_check_mch_setup(struct drm_device *dev)
6453 {
6454         struct drm_i915_private *dev_priv = dev->dev_private;
6455         uint32_t tmp;
6456
6457         tmp = I915_READ(MCH_SSKPD);
6458         if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6459                 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6460                               tmp);
6461 }
6462
6463 static void gen6_init_clock_gating(struct drm_device *dev)
6464 {
6465         struct drm_i915_private *dev_priv = dev->dev_private;
6466         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6467
6468         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6469
6470         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6471                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6472                    ILK_ELPIN_409_SELECT);
6473
6474         /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
6475         I915_WRITE(_3D_CHICKEN,
6476                    _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6477
6478         /* WaDisable_RenderCache_OperationalFlush:snb */
6479         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6480
6481         /*
6482          * BSpec recoomends 8x4 when MSAA is used,
6483          * however in practice 16x4 seems fastest.
6484          *
6485          * Note that PS/WM thread counts depend on the WIZ hashing
6486          * disable bit, which we don't touch here, but it's good
6487          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6488          */
6489         I915_WRITE(GEN6_GT_MODE,
6490                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6491
6492         ilk_init_lp_watermarks(dev);
6493
6494         I915_WRITE(CACHE_MODE_0,
6495                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6496
6497         I915_WRITE(GEN6_UCGCTL1,
6498                    I915_READ(GEN6_UCGCTL1) |
6499                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6500                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6501
6502         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6503          * gating disable must be set.  Failure to set it results in
6504          * flickering pixels due to Z write ordering failures after
6505          * some amount of runtime in the Mesa "fire" demo, and Unigine
6506          * Sanctuary and Tropics, and apparently anything else with
6507          * alpha test or pixel discard.
6508          *
6509          * According to the spec, bit 11 (RCCUNIT) must also be set,
6510          * but we didn't debug actual testcases to find it out.
6511          *
6512          * WaDisableRCCUnitClockGating:snb
6513          * WaDisableRCPBUnitClockGating:snb
6514          */
6515         I915_WRITE(GEN6_UCGCTL2,
6516                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6517                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6518
6519         /* WaStripsFansDisableFastClipPerformanceFix:snb */
6520         I915_WRITE(_3D_CHICKEN3,
6521                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6522
6523         /*
6524          * Bspec says:
6525          * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6526          * 3DSTATE_SF number of SF output attributes is more than 16."
6527          */
6528         I915_WRITE(_3D_CHICKEN3,
6529                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6530
6531         /*
6532          * According to the spec the following bits should be
6533          * set in order to enable memory self-refresh and fbc:
6534          * The bit21 and bit22 of 0x42000
6535          * The bit21 and bit22 of 0x42004
6536          * The bit5 and bit7 of 0x42020
6537          * The bit14 of 0x70180
6538          * The bit14 of 0x71180
6539          *
6540          * WaFbcAsynchFlipDisableFbcQueue:snb
6541          */
6542         I915_WRITE(ILK_DISPLAY_CHICKEN1,
6543                    I915_READ(ILK_DISPLAY_CHICKEN1) |
6544                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6545         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6546                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6547                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
6548         I915_WRITE(ILK_DSPCLK_GATE_D,
6549                    I915_READ(ILK_DSPCLK_GATE_D) |
6550                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
6551                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6552
6553         g4x_disable_trickle_feed(dev);
6554
6555         cpt_init_clock_gating(dev);
6556
6557         gen6_check_mch_setup(dev);
6558 }
6559
6560 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6561 {
6562         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6563
6564         /*
6565          * WaVSThreadDispatchOverride:ivb,vlv
6566          *
6567          * This actually overrides the dispatch
6568          * mode for all thread types.
6569          */
6570         reg &= ~GEN7_FF_SCHED_MASK;
6571         reg |= GEN7_FF_TS_SCHED_HW;
6572         reg |= GEN7_FF_VS_SCHED_HW;
6573         reg |= GEN7_FF_DS_SCHED_HW;
6574
6575         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6576 }
6577
6578 static void lpt_init_clock_gating(struct drm_device *dev)
6579 {
6580         struct drm_i915_private *dev_priv = dev->dev_private;
6581
6582         /*
6583          * TODO: this bit should only be enabled when really needed, then
6584          * disabled when not needed anymore in order to save power.
6585          */
6586         if (HAS_PCH_LPT_LP(dev))
6587                 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6588                            I915_READ(SOUTH_DSPCLK_GATE_D) |
6589                            PCH_LP_PARTITION_LEVEL_DISABLE);
6590
6591         /* WADPOClockGatingDisable:hsw */
6592         I915_WRITE(TRANS_CHICKEN1(PIPE_A),
6593                    I915_READ(TRANS_CHICKEN1(PIPE_A)) |
6594                    TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6595 }
6596
6597 static void lpt_suspend_hw(struct drm_device *dev)
6598 {
6599         struct drm_i915_private *dev_priv = dev->dev_private;
6600
6601         if (HAS_PCH_LPT_LP(dev)) {
6602                 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
6603
6604                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6605                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6606         }
6607 }
6608
6609 static void broadwell_init_clock_gating(struct drm_device *dev)
6610 {
6611         struct drm_i915_private *dev_priv = dev->dev_private;
6612         enum pipe pipe;
6613         uint32_t misccpctl;
6614
6615         ilk_init_lp_watermarks(dev);
6616
6617         /* WaSwitchSolVfFArbitrationPriority:bdw */
6618         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6619
6620         /* WaPsrDPAMaskVBlankInSRD:bdw */
6621         I915_WRITE(CHICKEN_PAR1_1,
6622                    I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
6623
6624         /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
6625         for_each_pipe(dev_priv, pipe) {
6626                 I915_WRITE(CHICKEN_PIPESL_1(pipe),
6627                            I915_READ(CHICKEN_PIPESL_1(pipe)) |
6628                            BDW_DPRS_MASK_VBLANK_SRD);
6629         }
6630
6631         /* WaVSRefCountFullforceMissDisable:bdw */
6632         /* WaDSRefCountFullforceMissDisable:bdw */
6633         I915_WRITE(GEN7_FF_THREAD_MODE,
6634                    I915_READ(GEN7_FF_THREAD_MODE) &
6635                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
6636
6637         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6638                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
6639
6640         /* WaDisableSDEUnitClockGating:bdw */
6641         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6642                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6643
6644         /*
6645          * WaProgramL3SqcReg1Default:bdw
6646          * WaTempDisableDOPClkGating:bdw
6647          */
6648         misccpctl = I915_READ(GEN7_MISCCPCTL);
6649         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
6650         I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
6651         /*
6652          * Wait at least 100 clocks before re-enabling clock gating. See
6653          * the definition of L3SQCREG1 in BSpec.
6654          */
6655         POSTING_READ(GEN8_L3SQCREG1);
6656         udelay(1);
6657         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
6658
6659         /*
6660          * WaGttCachingOffByDefault:bdw
6661          * GTT cache may not work with big pages, so if those
6662          * are ever enabled GTT cache may need to be disabled.
6663          */
6664         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6665
6666         lpt_init_clock_gating(dev);
6667 }
6668
6669 static void haswell_init_clock_gating(struct drm_device *dev)
6670 {
6671         struct drm_i915_private *dev_priv = dev->dev_private;
6672
6673         ilk_init_lp_watermarks(dev);
6674
6675         /* L3 caching of data atomics doesn't work -- disable it. */
6676         I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
6677         I915_WRITE(HSW_ROW_CHICKEN3,
6678                    _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
6679
6680         /* This is required by WaCatErrorRejectionIssue:hsw */
6681         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6682                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6683                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6684
6685         /* WaVSRefCountFullforceMissDisable:hsw */
6686         I915_WRITE(GEN7_FF_THREAD_MODE,
6687                    I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
6688
6689         /* WaDisable_RenderCache_OperationalFlush:hsw */
6690         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6691
6692         /* enable HiZ Raw Stall Optimization */
6693         I915_WRITE(CACHE_MODE_0_GEN7,
6694                    _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6695
6696         /* WaDisable4x2SubspanOptimization:hsw */
6697         I915_WRITE(CACHE_MODE_1,
6698                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6699
6700         /*
6701          * BSpec recommends 8x4 when MSAA is used,
6702          * however in practice 16x4 seems fastest.
6703          *
6704          * Note that PS/WM thread counts depend on the WIZ hashing
6705          * disable bit, which we don't touch here, but it's good
6706          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6707          */
6708         I915_WRITE(GEN7_GT_MODE,
6709                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6710
6711         /* WaSampleCChickenBitEnable:hsw */
6712         I915_WRITE(HALF_SLICE_CHICKEN3,
6713                    _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
6714
6715         /* WaSwitchSolVfFArbitrationPriority:hsw */
6716         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6717
6718         /* WaRsPkgCStateDisplayPMReq:hsw */
6719         I915_WRITE(CHICKEN_PAR1_1,
6720                    I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
6721
6722         lpt_init_clock_gating(dev);
6723 }
6724
6725 static void ivybridge_init_clock_gating(struct drm_device *dev)
6726 {
6727         struct drm_i915_private *dev_priv = dev->dev_private;
6728         uint32_t snpcr;
6729
6730         ilk_init_lp_watermarks(dev);
6731
6732         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6733
6734         /* WaDisableEarlyCull:ivb */
6735         I915_WRITE(_3D_CHICKEN3,
6736                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6737
6738         /* WaDisableBackToBackFlipFix:ivb */
6739         I915_WRITE(IVB_CHICKEN3,
6740                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6741                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
6742
6743         /* WaDisablePSDDualDispatchEnable:ivb */
6744         if (IS_IVB_GT1(dev))
6745                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6746                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
6747
6748         /* WaDisable_RenderCache_OperationalFlush:ivb */
6749         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6750
6751         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6752         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
6753                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
6754
6755         /* WaApplyL3ControlAndL3ChickenMode:ivb */
6756         I915_WRITE(GEN7_L3CNTLREG1,
6757                         GEN7_WA_FOR_GEN7_L3_CONTROL);
6758         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
6759                    GEN7_WA_L3_CHICKEN_MODE);
6760         if (IS_IVB_GT1(dev))
6761                 I915_WRITE(GEN7_ROW_CHICKEN2,
6762                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6763         else {
6764                 /* must write both registers */
6765                 I915_WRITE(GEN7_ROW_CHICKEN2,
6766                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6767                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
6768                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6769         }
6770
6771         /* WaForceL3Serialization:ivb */
6772         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6773                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6774
6775         /*
6776          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6777          * This implements the WaDisableRCZUnitClockGating:ivb workaround.
6778          */
6779         I915_WRITE(GEN6_UCGCTL2,
6780                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
6781
6782         /* This is required by WaCatErrorRejectionIssue:ivb */
6783         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6784                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6785                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6786
6787         g4x_disable_trickle_feed(dev);
6788
6789         gen7_setup_fixed_func_scheduler(dev_priv);
6790
6791         if (0) { /* causes HiZ corruption on ivb:gt1 */
6792                 /* enable HiZ Raw Stall Optimization */
6793                 I915_WRITE(CACHE_MODE_0_GEN7,
6794                            _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6795         }
6796
6797         /* WaDisable4x2SubspanOptimization:ivb */
6798         I915_WRITE(CACHE_MODE_1,
6799                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6800
6801         /*
6802          * BSpec recommends 8x4 when MSAA is used,
6803          * however in practice 16x4 seems fastest.
6804          *
6805          * Note that PS/WM thread counts depend on the WIZ hashing
6806          * disable bit, which we don't touch here, but it's good
6807          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6808          */
6809         I915_WRITE(GEN7_GT_MODE,
6810                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6811
6812         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
6813         snpcr &= ~GEN6_MBC_SNPCR_MASK;
6814         snpcr |= GEN6_MBC_SNPCR_MED;
6815         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
6816
6817         if (!HAS_PCH_NOP(dev))
6818                 cpt_init_clock_gating(dev);
6819
6820         gen6_check_mch_setup(dev);
6821 }
6822
6823 static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
6824 {
6825         u32 val;
6826
6827         /*
6828         * On driver load, a pipe may be active and driving a DSI display.
6829         * Preserve DPOUNIT_CLOCK_GATE_DISABLE to avoid the pipe getting stuck
6830         * (and never recovering) in this case. intel_dsi_post_disable() will
6831         * clear it when we turn off the display.
6832         */
6833         val = I915_READ(DSPCLK_GATE_D);
6834         val &= DPOUNIT_CLOCK_GATE_DISABLE;
6835         val |= VRHUNIT_CLOCK_GATE_DISABLE;
6836         I915_WRITE(DSPCLK_GATE_D, val);
6837
6838         /*
6839          * Disable trickle feed and enable pnd deadline calculation
6840          */
6841         I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6842         I915_WRITE(CBR1_VLV, 0);
6843 }
6844
6845 static void valleyview_init_clock_gating(struct drm_device *dev)
6846 {
6847         struct drm_i915_private *dev_priv = dev->dev_private;
6848
6849         vlv_init_display_clock_gating(dev_priv);
6850
6851         /* WaDisableEarlyCull:vlv */
6852         I915_WRITE(_3D_CHICKEN3,
6853                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6854
6855         /* WaDisableBackToBackFlipFix:vlv */
6856         I915_WRITE(IVB_CHICKEN3,
6857                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6858                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
6859
6860         /* WaPsdDispatchEnable:vlv */
6861         /* WaDisablePSDDualDispatchEnable:vlv */
6862         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6863                    _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
6864                                       GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
6865
6866         /* WaDisable_RenderCache_OperationalFlush:vlv */
6867         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6868
6869         /* WaForceL3Serialization:vlv */
6870         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6871                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6872
6873         /* WaDisableDopClockGating:vlv */
6874         I915_WRITE(GEN7_ROW_CHICKEN2,
6875                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6876
6877         /* This is required by WaCatErrorRejectionIssue:vlv */
6878         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6879                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6880                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6881
6882         gen7_setup_fixed_func_scheduler(dev_priv);
6883
6884         /*
6885          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6886          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
6887          */
6888         I915_WRITE(GEN6_UCGCTL2,
6889                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
6890
6891         /* WaDisableL3Bank2xClockGate:vlv
6892          * Disabling L3 clock gating- MMIO 940c[25] = 1
6893          * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6894         I915_WRITE(GEN7_UCGCTL4,
6895                    I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
6896
6897         /*
6898          * BSpec says this must be set, even though
6899          * WaDisable4x2SubspanOptimization isn't listed for VLV.
6900          */
6901         I915_WRITE(CACHE_MODE_1,
6902                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6903
6904         /*
6905          * BSpec recommends 8x4 when MSAA is used,
6906          * however in practice 16x4 seems fastest.
6907          *
6908          * Note that PS/WM thread counts depend on the WIZ hashing
6909          * disable bit, which we don't touch here, but it's good
6910          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6911          */
6912         I915_WRITE(GEN7_GT_MODE,
6913                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6914
6915         /*
6916          * WaIncreaseL3CreditsForVLVB0:vlv
6917          * This is the hardware default actually.
6918          */
6919         I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
6920
6921         /*
6922          * WaDisableVLVClockGating_VBIIssue:vlv
6923          * Disable clock gating on th GCFG unit to prevent a delay
6924          * in the reporting of vblank events.
6925          */
6926         I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6927 }
6928
6929 static void cherryview_init_clock_gating(struct drm_device *dev)
6930 {
6931         struct drm_i915_private *dev_priv = dev->dev_private;
6932
6933         vlv_init_display_clock_gating(dev_priv);
6934
6935         /* WaVSRefCountFullforceMissDisable:chv */
6936         /* WaDSRefCountFullforceMissDisable:chv */
6937         I915_WRITE(GEN7_FF_THREAD_MODE,
6938                    I915_READ(GEN7_FF_THREAD_MODE) &
6939                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
6940
6941         /* WaDisableSemaphoreAndSyncFlipWait:chv */
6942         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6943                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
6944
6945         /* WaDisableCSUnitClockGating:chv */
6946         I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6947                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6948
6949         /* WaDisableSDEUnitClockGating:chv */
6950         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6951                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6952
6953         /*
6954          * GTT cache may not work with big pages, so if those
6955          * are ever enabled GTT cache may need to be disabled.
6956          */
6957         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6958 }
6959
6960 static void g4x_init_clock_gating(struct drm_device *dev)
6961 {
6962         struct drm_i915_private *dev_priv = dev->dev_private;
6963         uint32_t dspclk_gate;
6964
6965         I915_WRITE(RENCLK_GATE_D1, 0);
6966         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6967                    GS_UNIT_CLOCK_GATE_DISABLE |
6968                    CL_UNIT_CLOCK_GATE_DISABLE);
6969         I915_WRITE(RAMCLK_GATE_D, 0);
6970         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6971                 OVRUNIT_CLOCK_GATE_DISABLE |
6972                 OVCUNIT_CLOCK_GATE_DISABLE;
6973         if (IS_GM45(dev))
6974                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
6975         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
6976
6977         /* WaDisableRenderCachePipelinedFlush */
6978         I915_WRITE(CACHE_MODE_0,
6979                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6980
6981         /* WaDisable_RenderCache_OperationalFlush:g4x */
6982         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6983
6984         g4x_disable_trickle_feed(dev);
6985 }
6986
6987 static void crestline_init_clock_gating(struct drm_device *dev)
6988 {
6989         struct drm_i915_private *dev_priv = dev->dev_private;
6990
6991         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
6992         I915_WRITE(RENCLK_GATE_D2, 0);
6993         I915_WRITE(DSPCLK_GATE_D, 0);
6994         I915_WRITE(RAMCLK_GATE_D, 0);
6995         I915_WRITE16(DEUC, 0);
6996         I915_WRITE(MI_ARB_STATE,
6997                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6998
6999         /* WaDisable_RenderCache_OperationalFlush:gen4 */
7000         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7001 }
7002
7003 static void broadwater_init_clock_gating(struct drm_device *dev)
7004 {
7005         struct drm_i915_private *dev_priv = dev->dev_private;
7006
7007         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7008                    I965_RCC_CLOCK_GATE_DISABLE |
7009                    I965_RCPB_CLOCK_GATE_DISABLE |
7010                    I965_ISC_CLOCK_GATE_DISABLE |
7011                    I965_FBC_CLOCK_GATE_DISABLE);
7012         I915_WRITE(RENCLK_GATE_D2, 0);
7013         I915_WRITE(MI_ARB_STATE,
7014                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7015
7016         /* WaDisable_RenderCache_OperationalFlush:gen4 */
7017         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7018 }
7019
7020 static void gen3_init_clock_gating(struct drm_device *dev)
7021 {
7022         struct drm_i915_private *dev_priv = dev->dev_private;
7023         u32 dstate = I915_READ(D_STATE);
7024
7025         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7026                 DSTATE_DOT_CLOCK_GATING;
7027         I915_WRITE(D_STATE, dstate);
7028
7029         if (IS_PINEVIEW(dev))
7030                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
7031
7032         /* IIR "flip pending" means done if this bit is set */
7033         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
7034
7035         /* interrupts should cause a wake up from C3 */
7036         I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
7037
7038         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7039         I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
7040
7041         I915_WRITE(MI_ARB_STATE,
7042                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
7043 }
7044
7045 static void i85x_init_clock_gating(struct drm_device *dev)
7046 {
7047         struct drm_i915_private *dev_priv = dev->dev_private;
7048
7049         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7050
7051         /* interrupts should cause a wake up from C3 */
7052         I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7053                    _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
7054
7055         I915_WRITE(MEM_MODE,
7056                    _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
7057 }
7058
7059 static void i830_init_clock_gating(struct drm_device *dev)
7060 {
7061         struct drm_i915_private *dev_priv = dev->dev_private;
7062
7063         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
7064
7065         I915_WRITE(MEM_MODE,
7066                    _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7067                    _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
7068 }
7069
7070 void intel_init_clock_gating(struct drm_device *dev)
7071 {
7072         struct drm_i915_private *dev_priv = dev->dev_private;
7073
7074         if (dev_priv->display.init_clock_gating)
7075                 dev_priv->display.init_clock_gating(dev);
7076 }
7077
7078 void intel_suspend_hw(struct drm_device *dev)
7079 {
7080         if (HAS_PCH_LPT(dev))
7081                 lpt_suspend_hw(dev);
7082 }
7083
7084 /* Set up chip specific power management-related functions */
7085 void intel_init_pm(struct drm_device *dev)
7086 {
7087         struct drm_i915_private *dev_priv = dev->dev_private;
7088         gdev = dev;
7089
7090         intel_fbc_init(dev_priv);
7091
7092         /* For cxsr */
7093         if (IS_PINEVIEW(dev))
7094                 i915_pineview_get_mem_freq(dev);
7095         else if (IS_GEN5(dev))
7096                 i915_ironlake_get_mem_freq(dev);
7097
7098         /* For FIFO watermark updates */
7099         if (INTEL_INFO(dev)->gen >= 9) {
7100                 skl_setup_wm_latency(dev);
7101
7102                 if (IS_BROXTON(dev))
7103                         dev_priv->display.init_clock_gating =
7104                                 bxt_init_clock_gating;
7105                 dev_priv->display.update_wm = skl_update_wm;
7106                 dev_priv->display.update_sprite_wm = skl_update_sprite_wm;
7107         } else if (HAS_PCH_SPLIT(dev)) {
7108                 ilk_setup_wm_latency(dev);
7109
7110                 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7111                      dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7112                     (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7113                      dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7114                         dev_priv->display.update_wm = ilk_update_wm;
7115                         dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
7116                 } else {
7117                         DRM_DEBUG_KMS("Failed to read display plane latency. "
7118                                       "Disable CxSR\n");
7119                 }
7120
7121                 if (IS_GEN5(dev))
7122                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7123                 else if (IS_GEN6(dev))
7124                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7125                 else if (IS_IVYBRIDGE(dev))
7126                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7127                 else if (IS_HASWELL(dev))
7128                         dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7129                 else if (INTEL_INFO(dev)->gen == 8)
7130                         dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7131         } else if (IS_CHERRYVIEW(dev)) {
7132                 vlv_setup_wm_latency(dev);
7133
7134                 dev_priv->display.update_wm = vlv_update_wm;
7135                 dev_priv->display.init_clock_gating =
7136                         cherryview_init_clock_gating;
7137         } else if (IS_VALLEYVIEW(dev)) {
7138                 vlv_setup_wm_latency(dev);
7139
7140                 dev_priv->display.update_wm = vlv_update_wm;
7141                 dev_priv->display.init_clock_gating =
7142                         valleyview_init_clock_gating;
7143         } else if (IS_PINEVIEW(dev)) {
7144                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7145                                             dev_priv->is_ddr3,
7146                                             dev_priv->fsb_freq,
7147                                             dev_priv->mem_freq)) {
7148                         DRM_INFO("failed to find known CxSR latency "
7149                                  "(found ddr%s fsb freq %d, mem freq %d), "
7150                                  "disabling CxSR\n",
7151                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
7152                                  dev_priv->fsb_freq, dev_priv->mem_freq);
7153                         /* Disable CxSR and never update its watermark again */
7154                         intel_set_memory_cxsr(dev_priv, false);
7155                         dev_priv->display.update_wm = NULL;
7156                 } else
7157                         dev_priv->display.update_wm = pineview_update_wm;
7158                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7159         } else if (IS_G4X(dev)) {
7160                 dev_priv->display.update_wm = g4x_update_wm;
7161                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7162         } else if (IS_GEN4(dev)) {
7163                 dev_priv->display.update_wm = i965_update_wm;
7164                 if (IS_CRESTLINE(dev))
7165                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7166                 else if (IS_BROADWATER(dev))
7167                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7168         } else if (IS_GEN3(dev)) {
7169                 dev_priv->display.update_wm = i9xx_update_wm;
7170                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7171                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7172         } else if (IS_GEN2(dev)) {
7173                 if (INTEL_INFO(dev)->num_pipes == 1) {
7174                         dev_priv->display.update_wm = i845_update_wm;
7175                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
7176                 } else {
7177                         dev_priv->display.update_wm = i9xx_update_wm;
7178                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
7179                 }
7180
7181                 if (IS_I85X(dev) || IS_I865G(dev))
7182                         dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7183                 else
7184                         dev_priv->display.init_clock_gating = i830_init_clock_gating;
7185         } else {
7186                 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7187         }
7188 }
7189
7190 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
7191 {
7192         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7193
7194         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7195                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7196                 return -EAGAIN;
7197         }
7198
7199         I915_WRITE(GEN6_PCODE_DATA, *val);
7200         I915_WRITE(GEN6_PCODE_DATA1, 0);
7201         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7202
7203         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7204                      500)) {
7205                 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7206                 return -ETIMEDOUT;
7207         }
7208
7209         *val = I915_READ(GEN6_PCODE_DATA);
7210         I915_WRITE(GEN6_PCODE_DATA, 0);
7211
7212         return 0;
7213 }
7214
7215 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
7216 {
7217         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7218
7219         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7220                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7221                 return -EAGAIN;
7222         }
7223
7224         I915_WRITE(GEN6_PCODE_DATA, val);
7225         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7226
7227         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7228                      500)) {
7229                 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7230                 return -ETIMEDOUT;
7231         }
7232
7233         I915_WRITE(GEN6_PCODE_DATA, 0);
7234
7235         return 0;
7236 }
7237
7238 static int vlv_gpu_freq_div(unsigned int czclk_freq)
7239 {
7240         switch (czclk_freq) {
7241         case 200:
7242                 return 10;
7243         case 267:
7244                 return 12;
7245         case 320:
7246         case 333:
7247                 return 16;
7248         case 400:
7249                 return 20;
7250         default:
7251                 return -1;
7252         }
7253 }
7254
7255 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7256 {
7257         int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7258
7259         div = vlv_gpu_freq_div(czclk_freq);
7260         if (div < 0)
7261                 return div;
7262
7263         return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div);
7264 }
7265
7266 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
7267 {
7268         int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7269
7270         mul = vlv_gpu_freq_div(czclk_freq);
7271         if (mul < 0)
7272                 return mul;
7273
7274         return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6;
7275 }
7276
7277 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7278 {
7279         int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7280
7281         div = vlv_gpu_freq_div(czclk_freq) / 2;
7282         if (div < 0)
7283                 return div;
7284
7285         return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2;
7286 }
7287
7288 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7289 {
7290         int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7291
7292         mul = vlv_gpu_freq_div(czclk_freq) / 2;
7293         if (mul < 0)
7294                 return mul;
7295
7296         /* CHV needs even values */
7297         return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2;
7298 }
7299
7300 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
7301 {
7302         if (IS_GEN9(dev_priv->dev))
7303                 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
7304                                          GEN9_FREQ_SCALER);
7305         else if (IS_CHERRYVIEW(dev_priv->dev))
7306                 return chv_gpu_freq(dev_priv, val);
7307         else if (IS_VALLEYVIEW(dev_priv->dev))
7308                 return byt_gpu_freq(dev_priv, val);
7309         else
7310                 return val * GT_FREQUENCY_MULTIPLIER;
7311 }
7312
7313 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7314 {
7315         if (IS_GEN9(dev_priv->dev))
7316                 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
7317                                          GT_FREQUENCY_MULTIPLIER);
7318         else if (IS_CHERRYVIEW(dev_priv->dev))
7319                 return chv_freq_opcode(dev_priv, val);
7320         else if (IS_VALLEYVIEW(dev_priv->dev))
7321                 return byt_freq_opcode(dev_priv, val);
7322         else
7323                 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
7324 }
7325
7326 struct request_boost {
7327         struct work_struct work;
7328         struct drm_i915_gem_request *req;
7329 };
7330
7331 static void __intel_rps_boost_work(struct work_struct *work)
7332 {
7333         struct request_boost *boost = container_of(work, struct request_boost, work);
7334         struct drm_i915_gem_request *req = boost->req;
7335
7336         if (!i915_gem_request_completed(req, true))
7337                 gen6_rps_boost(to_i915(req->ring->dev), NULL,
7338                                req->emitted_jiffies);
7339
7340         i915_gem_request_unreference__unlocked(req);
7341         kfree(boost);
7342 }
7343
7344 void intel_queue_rps_boost_for_request(struct drm_device *dev,
7345                                        struct drm_i915_gem_request *req)
7346 {
7347         struct request_boost *boost;
7348
7349         if (req == NULL || INTEL_INFO(dev)->gen < 6)
7350                 return;
7351
7352         if (i915_gem_request_completed(req, true))
7353                 return;
7354
7355         boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7356         if (boost == NULL)
7357                 return;
7358
7359         i915_gem_request_reference(req);
7360         boost->req = req;
7361
7362         INIT_WORK(&boost->work, __intel_rps_boost_work);
7363         queue_work(to_i915(dev)->wq, &boost->work);
7364 }
7365
7366 void intel_pm_setup(struct drm_device *dev)
7367 {
7368         struct drm_i915_private *dev_priv = dev->dev_private;
7369
7370         mutex_init(&dev_priv->rps.hw_lock);
7371         spin_lock_init(&dev_priv->rps.client_lock);
7372
7373         INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7374                           intel_gen6_powersave_work);
7375         INIT_LIST_HEAD(&dev_priv->rps.clients);
7376         INIT_LIST_HEAD(&dev_priv->rps.semaphores.link);
7377         INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link);
7378
7379         dev_priv->pm.suspended = false;
7380 }
7381
7382 bool ospm_power_is_hw_on(int hw_islands)
7383 {
7384 #if 0
7385         struct drm_device *drm_dev = gdev;
7386         unsigned long flags;
7387         bool ret = false;
7388         struct drm_i915_private *dev_priv = drm_dev->dev_private;
7389         u32 data = vlv_punit_read(dev_priv, VLV_IOSFSB_PWRGT_STATUS);
7390
7391         if ((VLV_POWER_GATE_DISPLAY_MASK & data)
7392                         == VLV_POWER_GATE_DISPLAY_MASK) {
7393                 DRM_ERROR("Display Island not ON\n");
7394                 return false;
7395         } else {
7396                 return true;
7397         }
7398 #endif
7399         return true;
7400 }
7401 EXPORT_SYMBOL(ospm_power_is_hw_on);
7402
7403 /* Dummy Function for HDMI Audio Power management.
7404  * Will be updated once S0iX code is integrated
7405  */
7406 bool ospm_power_using_hw_begin(int hw_island, UHBUsage usage)
7407 {
7408         struct drm_device *drm_dev = gdev;
7409
7410         i915_rpm_get_disp(drm_dev);
7411         return i915_is_device_active(drm_dev);
7412 }
7413 EXPORT_SYMBOL(ospm_power_using_hw_begin);
7414
7415 void ospm_power_using_hw_end(int hw_island)
7416 {
7417         struct drm_device *drm_dev = gdev;
7418
7419         i915_rpm_put_disp(drm_dev);
7420 }
7421 EXPORT_SYMBOL(ospm_power_using_hw_end);