1 // SPDX-License-Identifier: GPL-2.0
3 * PCI Bus Services, see include/linux/pci.h for further explanation.
5 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
8 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
11 #include <linux/acpi.h>
12 #include <linux/kernel.h>
13 #include <linux/delay.h>
14 #include <linux/dmi.h>
15 #include <linux/init.h>
17 #include <linux/of_pci.h>
18 #include <linux/pci.h>
20 #include <linux/slab.h>
21 #include <linux/module.h>
22 #include <linux/spinlock.h>
23 #include <linux/string.h>
24 #include <linux/log2.h>
25 #include <linux/logic_pio.h>
26 #include <linux/pci-aspm.h>
27 #include <linux/pm_wakeup.h>
28 #include <linux/interrupt.h>
29 #include <linux/device.h>
30 #include <linux/pm_runtime.h>
31 #include <linux/pci_hotplug.h>
32 #include <linux/vmalloc.h>
33 #include <linux/pci-ats.h>
34 #include <asm/setup.h>
36 #include <linux/aer.h>
39 const char *pci_power_names[] = {
40 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
42 EXPORT_SYMBOL_GPL(pci_power_names);
44 int isa_dma_bridge_buggy;
45 EXPORT_SYMBOL(isa_dma_bridge_buggy);
48 EXPORT_SYMBOL(pci_pci_problems);
50 unsigned int pci_pm_d3_delay;
52 static void pci_pme_list_scan(struct work_struct *work);
54 static LIST_HEAD(pci_pme_list);
55 static DEFINE_MUTEX(pci_pme_list_mutex);
56 static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
58 struct pci_pme_device {
59 struct list_head list;
63 #define PME_TIMEOUT 1000 /* How long between PME checks */
65 static void pci_dev_d3_sleep(struct pci_dev *dev)
67 unsigned int delay = dev->d3_delay;
69 if (delay < pci_pm_d3_delay)
70 delay = pci_pm_d3_delay;
76 #ifdef CONFIG_PCI_DOMAINS
77 int pci_domains_supported = 1;
80 #define DEFAULT_CARDBUS_IO_SIZE (256)
81 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
82 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
83 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
84 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
86 #define DEFAULT_HOTPLUG_IO_SIZE (256)
87 #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
88 /* pci=hpmemsize=nnM,hpiosize=nn can override this */
89 unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
90 unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;
92 #define DEFAULT_HOTPLUG_BUS_SIZE 1
93 unsigned long pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE;
95 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_DEFAULT;
98 * The default CLS is used if arch didn't set CLS explicitly and not
99 * all pci devices agree on the same value. Arch can override either
100 * the dfl or actual value as it sees fit. Don't forget this is
101 * measured in 32-bit words, not bytes.
103 u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2;
104 u8 pci_cache_line_size;
107 * If we set up a device for bus mastering, we need to check the latency
108 * timer as certain BIOSes forget to set it properly.
110 unsigned int pcibios_max_latency = 255;
112 /* If set, the PCIe ARI capability will not be used. */
113 static bool pcie_ari_disabled;
115 /* If set, the PCIe ATS capability will not be used. */
116 static bool pcie_ats_disabled;
118 bool pci_ats_disabled(void)
120 return pcie_ats_disabled;
123 /* Disable bridge_d3 for all PCIe ports */
124 static bool pci_bridge_d3_disable;
125 /* Force bridge_d3 for all PCIe ports */
126 static bool pci_bridge_d3_force;
128 static int __init pcie_port_pm_setup(char *str)
130 if (!strcmp(str, "off"))
131 pci_bridge_d3_disable = true;
132 else if (!strcmp(str, "force"))
133 pci_bridge_d3_force = true;
136 __setup("pcie_port_pm=", pcie_port_pm_setup);
138 /* Time to wait after a reset for device to become responsive */
139 #define PCIE_RESET_READY_POLL_MS 60000
142 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
143 * @bus: pointer to PCI bus structure to search
145 * Given a PCI bus, returns the highest PCI bus number present in the set
146 * including the given PCI bus and its list of child PCI buses.
148 unsigned char pci_bus_max_busnr(struct pci_bus *bus)
151 unsigned char max, n;
153 max = bus->busn_res.end;
154 list_for_each_entry(tmp, &bus->children, node) {
155 n = pci_bus_max_busnr(tmp);
161 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
163 #ifdef CONFIG_HAS_IOMEM
164 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
166 struct resource *res = &pdev->resource[bar];
169 * Make sure the BAR is actually a memory resource, not an IO resource
171 if (res->flags & IORESOURCE_UNSET || !(res->flags & IORESOURCE_MEM)) {
172 pci_warn(pdev, "can't ioremap BAR %d: %pR\n", bar, res);
175 return ioremap_nocache(res->start, resource_size(res));
177 EXPORT_SYMBOL_GPL(pci_ioremap_bar);
179 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar)
182 * Make sure the BAR is actually a memory resource, not an IO resource
184 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
188 return ioremap_wc(pci_resource_start(pdev, bar),
189 pci_resource_len(pdev, bar));
191 EXPORT_SYMBOL_GPL(pci_ioremap_wc_bar);
195 static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
196 u8 pos, int cap, int *ttl)
201 pci_bus_read_config_byte(bus, devfn, pos, &pos);
207 pci_bus_read_config_word(bus, devfn, pos, &ent);
219 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
222 int ttl = PCI_FIND_CAP_TTL;
224 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
227 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
229 return __pci_find_next_cap(dev->bus, dev->devfn,
230 pos + PCI_CAP_LIST_NEXT, cap);
232 EXPORT_SYMBOL_GPL(pci_find_next_capability);
234 static int __pci_bus_find_cap_start(struct pci_bus *bus,
235 unsigned int devfn, u8 hdr_type)
239 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
240 if (!(status & PCI_STATUS_CAP_LIST))
244 case PCI_HEADER_TYPE_NORMAL:
245 case PCI_HEADER_TYPE_BRIDGE:
246 return PCI_CAPABILITY_LIST;
247 case PCI_HEADER_TYPE_CARDBUS:
248 return PCI_CB_CAPABILITY_LIST;
255 * pci_find_capability - query for devices' capabilities
256 * @dev: PCI device to query
257 * @cap: capability code
259 * Tell if a device supports a given PCI capability.
260 * Returns the address of the requested capability structure within the
261 * device's PCI configuration space or 0 in case the device does not
262 * support it. Possible values for @cap:
264 * %PCI_CAP_ID_PM Power Management
265 * %PCI_CAP_ID_AGP Accelerated Graphics Port
266 * %PCI_CAP_ID_VPD Vital Product Data
267 * %PCI_CAP_ID_SLOTID Slot Identification
268 * %PCI_CAP_ID_MSI Message Signalled Interrupts
269 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
270 * %PCI_CAP_ID_PCIX PCI-X
271 * %PCI_CAP_ID_EXP PCI Express
273 int pci_find_capability(struct pci_dev *dev, int cap)
277 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
279 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
283 EXPORT_SYMBOL(pci_find_capability);
286 * pci_bus_find_capability - query for devices' capabilities
287 * @bus: the PCI bus to query
288 * @devfn: PCI device to query
289 * @cap: capability code
291 * Like pci_find_capability() but works for pci devices that do not have a
292 * pci_dev structure set up yet.
294 * Returns the address of the requested capability structure within the
295 * device's PCI configuration space or 0 in case the device does not
298 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
303 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
305 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
307 pos = __pci_find_next_cap(bus, devfn, pos, cap);
311 EXPORT_SYMBOL(pci_bus_find_capability);
314 * pci_find_next_ext_capability - Find an extended capability
315 * @dev: PCI device to query
316 * @start: address at which to start looking (0 to start at beginning of list)
317 * @cap: capability code
319 * Returns the address of the next matching extended capability structure
320 * within the device's PCI configuration space or 0 if the device does
321 * not support it. Some capabilities can occur several times, e.g., the
322 * vendor-specific capability, and this provides a way to find them all.
324 int pci_find_next_ext_capability(struct pci_dev *dev, int start, int cap)
328 int pos = PCI_CFG_SPACE_SIZE;
330 /* minimum 8 bytes per capability */
331 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
333 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
339 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
343 * If we have no capabilities, this is indicated by cap ID,
344 * cap version and next pointer all being 0.
350 if (PCI_EXT_CAP_ID(header) == cap && pos != start)
353 pos = PCI_EXT_CAP_NEXT(header);
354 if (pos < PCI_CFG_SPACE_SIZE)
357 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
363 EXPORT_SYMBOL_GPL(pci_find_next_ext_capability);
366 * pci_find_ext_capability - Find an extended capability
367 * @dev: PCI device to query
368 * @cap: capability code
370 * Returns the address of the requested extended capability structure
371 * within the device's PCI configuration space or 0 if the device does
372 * not support it. Possible values for @cap:
374 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
375 * %PCI_EXT_CAP_ID_VC Virtual Channel
376 * %PCI_EXT_CAP_ID_DSN Device Serial Number
377 * %PCI_EXT_CAP_ID_PWR Power Budgeting
379 int pci_find_ext_capability(struct pci_dev *dev, int cap)
381 return pci_find_next_ext_capability(dev, 0, cap);
383 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
385 static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
387 int rc, ttl = PCI_FIND_CAP_TTL;
390 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
391 mask = HT_3BIT_CAP_MASK;
393 mask = HT_5BIT_CAP_MASK;
395 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
396 PCI_CAP_ID_HT, &ttl);
398 rc = pci_read_config_byte(dev, pos + 3, &cap);
399 if (rc != PCIBIOS_SUCCESSFUL)
402 if ((cap & mask) == ht_cap)
405 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
406 pos + PCI_CAP_LIST_NEXT,
407 PCI_CAP_ID_HT, &ttl);
413 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
414 * @dev: PCI device to query
415 * @pos: Position from which to continue searching
416 * @ht_cap: Hypertransport capability code
418 * To be used in conjunction with pci_find_ht_capability() to search for
419 * all capabilities matching @ht_cap. @pos should always be a value returned
420 * from pci_find_ht_capability().
422 * NB. To be 100% safe against broken PCI devices, the caller should take
423 * steps to avoid an infinite loop.
425 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
427 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
429 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
432 * pci_find_ht_capability - query a device's Hypertransport capabilities
433 * @dev: PCI device to query
434 * @ht_cap: Hypertransport capability code
436 * Tell if a device supports a given Hypertransport capability.
437 * Returns an address within the device's PCI configuration space
438 * or 0 in case the device does not support the request capability.
439 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
440 * which has a Hypertransport capability matching @ht_cap.
442 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
446 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
448 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
452 EXPORT_SYMBOL_GPL(pci_find_ht_capability);
455 * pci_find_parent_resource - return resource region of parent bus of given region
456 * @dev: PCI device structure contains resources to be searched
457 * @res: child resource record for which parent is sought
459 * For given resource region of given device, return the resource
460 * region of parent bus the given region is contained in.
462 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
463 struct resource *res)
465 const struct pci_bus *bus = dev->bus;
469 pci_bus_for_each_resource(bus, r, i) {
472 if (resource_contains(r, res)) {
475 * If the window is prefetchable but the BAR is
476 * not, the allocator made a mistake.
478 if (r->flags & IORESOURCE_PREFETCH &&
479 !(res->flags & IORESOURCE_PREFETCH))
483 * If we're below a transparent bridge, there may
484 * be both a positively-decoded aperture and a
485 * subtractively-decoded region that contain the BAR.
486 * We want the positively-decoded one, so this depends
487 * on pci_bus_for_each_resource() giving us those
495 EXPORT_SYMBOL(pci_find_parent_resource);
498 * pci_find_resource - Return matching PCI device resource
499 * @dev: PCI device to query
500 * @res: Resource to look for
502 * Goes over standard PCI resources (BARs) and checks if the given resource
503 * is partially or fully contained in any of them. In that case the
504 * matching resource is returned, %NULL otherwise.
506 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res)
510 for (i = 0; i < PCI_ROM_RESOURCE; i++) {
511 struct resource *r = &dev->resource[i];
513 if (r->start && resource_contains(r, res))
519 EXPORT_SYMBOL(pci_find_resource);
522 * pci_find_pcie_root_port - return PCIe Root Port
523 * @dev: PCI device to query
525 * Traverse up the parent chain and return the PCIe Root Port PCI Device
526 * for a given PCI Device.
528 struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev)
530 struct pci_dev *bridge, *highest_pcie_bridge = dev;
532 bridge = pci_upstream_bridge(dev);
533 while (bridge && pci_is_pcie(bridge)) {
534 highest_pcie_bridge = bridge;
535 bridge = pci_upstream_bridge(bridge);
538 if (pci_pcie_type(highest_pcie_bridge) != PCI_EXP_TYPE_ROOT_PORT)
541 return highest_pcie_bridge;
543 EXPORT_SYMBOL(pci_find_pcie_root_port);
546 * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos
547 * @dev: the PCI device to operate on
548 * @pos: config space offset of status word
549 * @mask: mask of bit(s) to care about in status word
551 * Return 1 when mask bit(s) in status word clear, 0 otherwise.
553 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask)
557 /* Wait for Transaction Pending bit clean */
558 for (i = 0; i < 4; i++) {
561 msleep((1 << (i - 1)) * 100);
563 pci_read_config_word(dev, pos, &status);
564 if (!(status & mask))
572 * pci_restore_bars - restore a device's BAR values (e.g. after wake-up)
573 * @dev: PCI device to have its BARs restored
575 * Restore the BAR values for a given device, so as to make it
576 * accessible by its driver.
578 static void pci_restore_bars(struct pci_dev *dev)
582 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
583 pci_update_resource(dev, i);
586 static const struct pci_platform_pm_ops *pci_platform_pm;
588 int pci_set_platform_pm(const struct pci_platform_pm_ops *ops)
590 if (!ops->is_manageable || !ops->set_state || !ops->get_state ||
591 !ops->choose_state || !ops->set_wakeup || !ops->need_resume)
593 pci_platform_pm = ops;
597 static inline bool platform_pci_power_manageable(struct pci_dev *dev)
599 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
602 static inline int platform_pci_set_power_state(struct pci_dev *dev,
605 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
608 static inline pci_power_t platform_pci_get_power_state(struct pci_dev *dev)
610 return pci_platform_pm ? pci_platform_pm->get_state(dev) : PCI_UNKNOWN;
613 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
615 return pci_platform_pm ?
616 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
619 static inline int platform_pci_set_wakeup(struct pci_dev *dev, bool enable)
621 return pci_platform_pm ?
622 pci_platform_pm->set_wakeup(dev, enable) : -ENODEV;
625 static inline bool platform_pci_need_resume(struct pci_dev *dev)
627 return pci_platform_pm ? pci_platform_pm->need_resume(dev) : false;
631 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
633 * @dev: PCI device to handle.
634 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
637 * -EINVAL if the requested state is invalid.
638 * -EIO if device does not support PCI PM or its PM capabilities register has a
639 * wrong version, or device doesn't support the requested state.
640 * 0 if device already is in the requested state.
641 * 0 if device's power state has been successfully changed.
643 static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
646 bool need_restore = false;
648 /* Check if we're already there */
649 if (dev->current_state == state)
655 if (state < PCI_D0 || state > PCI_D3hot)
658 /* Validate current state:
659 * Can enter D0 from any state, but if we can only go deeper
660 * to sleep if we're already in a low power state
662 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
663 && dev->current_state > state) {
664 pci_err(dev, "invalid power transition (from state %d to %d)\n",
665 dev->current_state, state);
669 /* check if this device supports the desired state */
670 if ((state == PCI_D1 && !dev->d1_support)
671 || (state == PCI_D2 && !dev->d2_support))
674 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
676 /* If we're (effectively) in D3, force entire word to 0.
677 * This doesn't affect PME_Status, disables PME_En, and
678 * sets PowerState to 0.
680 switch (dev->current_state) {
684 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
689 case PCI_UNKNOWN: /* Boot-up */
690 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
691 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
693 /* Fall-through: force to D0 */
699 /* enter specified state */
700 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
702 /* Mandatory power management transition delays */
703 /* see PCI PM 1.1 5.6.1 table 18 */
704 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
705 pci_dev_d3_sleep(dev);
706 else if (state == PCI_D2 || dev->current_state == PCI_D2)
707 udelay(PCI_PM_D2_DELAY);
709 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
710 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
711 if (dev->current_state != state && printk_ratelimit())
712 pci_info(dev, "Refused to change power state, currently in D%d\n",
716 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
717 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
718 * from D3hot to D0 _may_ perform an internal reset, thereby
719 * going to "D0 Uninitialized" rather than "D0 Initialized".
720 * For example, at least some versions of the 3c905B and the
721 * 3c556B exhibit this behaviour.
723 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
724 * devices in a D3hot state at boot. Consequently, we need to
725 * restore at least the BARs so that the device will be
726 * accessible to its driver.
729 pci_restore_bars(dev);
732 pcie_aspm_pm_state_change(dev->bus->self);
738 * pci_update_current_state - Read power state of given device and cache it
739 * @dev: PCI device to handle.
740 * @state: State to cache in case the device doesn't have the PM capability
742 * The power state is read from the PMCSR register, which however is
743 * inaccessible in D3cold. The platform firmware is therefore queried first
744 * to detect accessibility of the register. In case the platform firmware
745 * reports an incorrect state or the device isn't power manageable by the
746 * platform at all, we try to detect D3cold by testing accessibility of the
747 * vendor ID in config space.
749 void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
751 if (platform_pci_get_power_state(dev) == PCI_D3cold ||
752 !pci_device_is_present(dev)) {
753 dev->current_state = PCI_D3cold;
754 } else if (dev->pm_cap) {
757 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
758 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
760 dev->current_state = state;
765 * pci_power_up - Put the given device into D0 forcibly
766 * @dev: PCI device to power up
768 void pci_power_up(struct pci_dev *dev)
770 if (platform_pci_power_manageable(dev))
771 platform_pci_set_power_state(dev, PCI_D0);
773 pci_raw_set_power_state(dev, PCI_D0);
774 pci_update_current_state(dev, PCI_D0);
778 * pci_platform_power_transition - Use platform to change device power state
779 * @dev: PCI device to handle.
780 * @state: State to put the device into.
782 static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
786 if (platform_pci_power_manageable(dev)) {
787 error = platform_pci_set_power_state(dev, state);
789 pci_update_current_state(dev, state);
793 if (error && !dev->pm_cap) /* Fall back to PCI_D0 */
794 dev->current_state = PCI_D0;
800 * pci_wakeup - Wake up a PCI device
801 * @pci_dev: Device to handle.
802 * @ign: ignored parameter
804 static int pci_wakeup(struct pci_dev *pci_dev, void *ign)
806 pci_wakeup_event(pci_dev);
807 pm_request_resume(&pci_dev->dev);
812 * pci_wakeup_bus - Walk given bus and wake up devices on it
813 * @bus: Top bus of the subtree to walk.
815 void pci_wakeup_bus(struct pci_bus *bus)
818 pci_walk_bus(bus, pci_wakeup, NULL);
822 * __pci_start_power_transition - Start power transition of a PCI device
823 * @dev: PCI device to handle.
824 * @state: State to put the device into.
826 static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
828 if (state == PCI_D0) {
829 pci_platform_power_transition(dev, PCI_D0);
831 * Mandatory power management transition delays, see
832 * PCI Express Base Specification Revision 2.0 Section
833 * 6.6.1: Conventional Reset. Do not delay for
834 * devices powered on/off by corresponding bridge,
835 * because have already delayed for the bridge.
837 if (dev->runtime_d3cold) {
838 if (dev->d3cold_delay)
839 msleep(dev->d3cold_delay);
841 * When powering on a bridge from D3cold, the
842 * whole hierarchy may be powered on into
843 * D0uninitialized state, resume them to give
844 * them a chance to suspend again
846 pci_wakeup_bus(dev->subordinate);
852 * __pci_dev_set_current_state - Set current state of a PCI device
853 * @dev: Device to handle
854 * @data: pointer to state to be set
856 static int __pci_dev_set_current_state(struct pci_dev *dev, void *data)
858 pci_power_t state = *(pci_power_t *)data;
860 dev->current_state = state;
865 * pci_bus_set_current_state - Walk given bus and set current state of devices
866 * @bus: Top bus of the subtree to walk.
867 * @state: state to be set
869 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state)
872 pci_walk_bus(bus, __pci_dev_set_current_state, &state);
876 * __pci_complete_power_transition - Complete power transition of a PCI device
877 * @dev: PCI device to handle.
878 * @state: State to put the device into.
880 * This function should not be called directly by device drivers.
882 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
888 ret = pci_platform_power_transition(dev, state);
889 /* Power off the bridge may power off the whole hierarchy */
890 if (!ret && state == PCI_D3cold)
891 pci_bus_set_current_state(dev->subordinate, PCI_D3cold);
894 EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
897 * pci_set_power_state - Set the power state of a PCI device
898 * @dev: PCI device to handle.
899 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
901 * Transition a device to a new power state, using the platform firmware and/or
902 * the device's PCI PM registers.
905 * -EINVAL if the requested state is invalid.
906 * -EIO if device does not support PCI PM or its PM capabilities register has a
907 * wrong version, or device doesn't support the requested state.
908 * 0 if the transition is to D1 or D2 but D1 and D2 are not supported.
909 * 0 if device already is in the requested state.
910 * 0 if the transition is to D3 but D3 is not supported.
911 * 0 if device's power state has been successfully changed.
913 int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
917 /* bound the state we're entering */
918 if (state > PCI_D3cold)
920 else if (state < PCI_D0)
922 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
924 * If the device or the parent bridge do not support PCI PM,
925 * ignore the request if we're doing anything other than putting
926 * it into D0 (which would only happen on boot).
930 /* Check if we're already there */
931 if (dev->current_state == state)
934 __pci_start_power_transition(dev, state);
936 /* This device is quirked not to be put into D3, so
937 don't put it in D3 */
938 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
942 * To put device in D3cold, we put device into D3hot in native
943 * way, then put device into D3cold with platform ops
945 error = pci_raw_set_power_state(dev, state > PCI_D3hot ?
948 if (!__pci_complete_power_transition(dev, state))
953 EXPORT_SYMBOL(pci_set_power_state);
956 * pci_choose_state - Choose the power state of a PCI device
957 * @dev: PCI device to be suspended
958 * @state: target sleep state for the whole system. This is the value
959 * that is passed to suspend() function.
961 * Returns PCI power state suitable for given device and given system
965 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
972 ret = platform_pci_choose_state(dev);
973 if (ret != PCI_POWER_ERROR)
976 switch (state.event) {
979 case PM_EVENT_FREEZE:
980 case PM_EVENT_PRETHAW:
981 /* REVISIT both freeze and pre-thaw "should" use D0 */
982 case PM_EVENT_SUSPEND:
983 case PM_EVENT_HIBERNATE:
986 pci_info(dev, "unrecognized suspend event %d\n",
992 EXPORT_SYMBOL(pci_choose_state);
994 #define PCI_EXP_SAVE_REGS 7
996 static struct pci_cap_saved_state *_pci_find_saved_cap(struct pci_dev *pci_dev,
997 u16 cap, bool extended)
999 struct pci_cap_saved_state *tmp;
1001 hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) {
1002 if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap)
1008 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap)
1010 return _pci_find_saved_cap(dev, cap, false);
1013 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, u16 cap)
1015 return _pci_find_saved_cap(dev, cap, true);
1018 static int pci_save_pcie_state(struct pci_dev *dev)
1021 struct pci_cap_saved_state *save_state;
1024 if (!pci_is_pcie(dev))
1027 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
1029 pci_err(dev, "buffer not found in %s\n", __func__);
1033 cap = (u16 *)&save_state->cap.data[0];
1034 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]);
1035 pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]);
1036 pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]);
1037 pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]);
1038 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]);
1039 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]);
1040 pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]);
1045 static void pci_restore_pcie_state(struct pci_dev *dev)
1048 struct pci_cap_saved_state *save_state;
1051 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
1055 cap = (u16 *)&save_state->cap.data[0];
1056 pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]);
1057 pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]);
1058 pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]);
1059 pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]);
1060 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]);
1061 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]);
1062 pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
1066 static int pci_save_pcix_state(struct pci_dev *dev)
1069 struct pci_cap_saved_state *save_state;
1071 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1075 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1077 pci_err(dev, "buffer not found in %s\n", __func__);
1081 pci_read_config_word(dev, pos + PCI_X_CMD,
1082 (u16 *)save_state->cap.data);
1087 static void pci_restore_pcix_state(struct pci_dev *dev)
1090 struct pci_cap_saved_state *save_state;
1093 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1094 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1095 if (!save_state || !pos)
1097 cap = (u16 *)&save_state->cap.data[0];
1099 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
1104 * pci_save_state - save the PCI configuration space of a device before suspending
1105 * @dev: - PCI device that we're dealing with
1107 int pci_save_state(struct pci_dev *dev)
1110 /* XXX: 100% dword access ok here? */
1111 for (i = 0; i < 16; i++)
1112 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
1113 dev->state_saved = true;
1115 i = pci_save_pcie_state(dev);
1119 i = pci_save_pcix_state(dev);
1123 return pci_save_vc_state(dev);
1125 EXPORT_SYMBOL(pci_save_state);
1127 static void pci_restore_config_dword(struct pci_dev *pdev, int offset,
1128 u32 saved_val, int retry, bool force)
1132 pci_read_config_dword(pdev, offset, &val);
1133 if (!force && val == saved_val)
1137 pci_dbg(pdev, "restoring config space at offset %#x (was %#x, writing %#x)\n",
1138 offset, val, saved_val);
1139 pci_write_config_dword(pdev, offset, saved_val);
1143 pci_read_config_dword(pdev, offset, &val);
1144 if (val == saved_val)
1151 static void pci_restore_config_space_range(struct pci_dev *pdev,
1152 int start, int end, int retry,
1157 for (index = end; index >= start; index--)
1158 pci_restore_config_dword(pdev, 4 * index,
1159 pdev->saved_config_space[index],
1163 static void pci_restore_config_space(struct pci_dev *pdev)
1165 if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) {
1166 pci_restore_config_space_range(pdev, 10, 15, 0, false);
1167 /* Restore BARs before the command register. */
1168 pci_restore_config_space_range(pdev, 4, 9, 10, false);
1169 pci_restore_config_space_range(pdev, 0, 3, 0, false);
1170 } else if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
1171 pci_restore_config_space_range(pdev, 12, 15, 0, false);
1174 * Force rewriting of prefetch registers to avoid S3 resume
1175 * issues on Intel PCI bridges that occur when these
1176 * registers are not explicitly written.
1178 pci_restore_config_space_range(pdev, 9, 11, 0, true);
1179 pci_restore_config_space_range(pdev, 0, 8, 0, false);
1181 pci_restore_config_space_range(pdev, 0, 15, 0, false);
1185 static void pci_restore_rebar_state(struct pci_dev *pdev)
1187 unsigned int pos, nbars, i;
1190 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR);
1194 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
1195 nbars = (ctrl & PCI_REBAR_CTRL_NBAR_MASK) >>
1196 PCI_REBAR_CTRL_NBAR_SHIFT;
1198 for (i = 0; i < nbars; i++, pos += 8) {
1199 struct resource *res;
1202 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
1203 bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX;
1204 res = pdev->resource + bar_idx;
1205 size = order_base_2((resource_size(res) >> 20) | 1) - 1;
1206 ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE;
1208 pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl);
1213 * pci_restore_state - Restore the saved state of a PCI device
1214 * @dev: - PCI device that we're dealing with
1216 void pci_restore_state(struct pci_dev *dev)
1218 if (!dev->state_saved)
1221 /* PCI Express register must be restored first */
1222 pci_restore_pcie_state(dev);
1223 pci_restore_pasid_state(dev);
1224 pci_restore_pri_state(dev);
1225 pci_restore_ats_state(dev);
1226 pci_restore_vc_state(dev);
1227 pci_restore_rebar_state(dev);
1229 pci_cleanup_aer_error_status_regs(dev);
1231 pci_restore_config_space(dev);
1233 pci_restore_pcix_state(dev);
1234 pci_restore_msi_state(dev);
1236 /* Restore ACS and IOV configuration state */
1237 pci_enable_acs(dev);
1238 pci_restore_iov_state(dev);
1240 dev->state_saved = false;
1242 EXPORT_SYMBOL(pci_restore_state);
1244 struct pci_saved_state {
1245 u32 config_space[16];
1246 struct pci_cap_saved_data cap[0];
1250 * pci_store_saved_state - Allocate and return an opaque struct containing
1251 * the device saved state.
1252 * @dev: PCI device that we're dealing with
1254 * Return NULL if no state or error.
1256 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
1258 struct pci_saved_state *state;
1259 struct pci_cap_saved_state *tmp;
1260 struct pci_cap_saved_data *cap;
1263 if (!dev->state_saved)
1266 size = sizeof(*state) + sizeof(struct pci_cap_saved_data);
1268 hlist_for_each_entry(tmp, &dev->saved_cap_space, next)
1269 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1271 state = kzalloc(size, GFP_KERNEL);
1275 memcpy(state->config_space, dev->saved_config_space,
1276 sizeof(state->config_space));
1279 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) {
1280 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1281 memcpy(cap, &tmp->cap, len);
1282 cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
1284 /* Empty cap_save terminates list */
1288 EXPORT_SYMBOL_GPL(pci_store_saved_state);
1291 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1292 * @dev: PCI device that we're dealing with
1293 * @state: Saved state returned from pci_store_saved_state()
1295 int pci_load_saved_state(struct pci_dev *dev,
1296 struct pci_saved_state *state)
1298 struct pci_cap_saved_data *cap;
1300 dev->state_saved = false;
1305 memcpy(dev->saved_config_space, state->config_space,
1306 sizeof(state->config_space));
1310 struct pci_cap_saved_state *tmp;
1312 tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended);
1313 if (!tmp || tmp->cap.size != cap->size)
1316 memcpy(tmp->cap.data, cap->data, tmp->cap.size);
1317 cap = (struct pci_cap_saved_data *)((u8 *)cap +
1318 sizeof(struct pci_cap_saved_data) + cap->size);
1321 dev->state_saved = true;
1324 EXPORT_SYMBOL_GPL(pci_load_saved_state);
1327 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1328 * and free the memory allocated for it.
1329 * @dev: PCI device that we're dealing with
1330 * @state: Pointer to saved state returned from pci_store_saved_state()
1332 int pci_load_and_free_saved_state(struct pci_dev *dev,
1333 struct pci_saved_state **state)
1335 int ret = pci_load_saved_state(dev, *state);
1340 EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);
1342 int __weak pcibios_enable_device(struct pci_dev *dev, int bars)
1344 return pci_enable_resources(dev, bars);
1347 static int do_pci_enable_device(struct pci_dev *dev, int bars)
1350 struct pci_dev *bridge;
1354 err = pci_set_power_state(dev, PCI_D0);
1355 if (err < 0 && err != -EIO)
1358 bridge = pci_upstream_bridge(dev);
1360 pcie_aspm_powersave_config_link(bridge);
1362 err = pcibios_enable_device(dev, bars);
1365 pci_fixup_device(pci_fixup_enable, dev);
1367 if (dev->msi_enabled || dev->msix_enabled)
1370 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1372 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1373 if (cmd & PCI_COMMAND_INTX_DISABLE)
1374 pci_write_config_word(dev, PCI_COMMAND,
1375 cmd & ~PCI_COMMAND_INTX_DISABLE);
1382 * pci_reenable_device - Resume abandoned device
1383 * @dev: PCI device to be resumed
1385 * Note this function is a backend of pci_default_resume and is not supposed
1386 * to be called by normal code, write proper resume handler and use it instead.
1388 int pci_reenable_device(struct pci_dev *dev)
1390 if (pci_is_enabled(dev))
1391 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
1394 EXPORT_SYMBOL(pci_reenable_device);
1396 static void pci_enable_bridge(struct pci_dev *dev)
1398 struct pci_dev *bridge;
1401 bridge = pci_upstream_bridge(dev);
1403 pci_enable_bridge(bridge);
1405 if (pci_is_enabled(dev)) {
1406 if (!dev->is_busmaster)
1407 pci_set_master(dev);
1411 retval = pci_enable_device(dev);
1413 pci_err(dev, "Error enabling bridge (%d), continuing\n",
1415 pci_set_master(dev);
1418 static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags)
1420 struct pci_dev *bridge;
1425 * Power state could be unknown at this point, either due to a fresh
1426 * boot or a device removal call. So get the current power state
1427 * so that things like MSI message writing will behave as expected
1428 * (e.g. if the device really is in D0 at enable time).
1432 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1433 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1436 if (atomic_inc_return(&dev->enable_cnt) > 1)
1437 return 0; /* already enabled */
1439 bridge = pci_upstream_bridge(dev);
1441 pci_enable_bridge(bridge);
1443 /* only skip sriov related */
1444 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
1445 if (dev->resource[i].flags & flags)
1447 for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++)
1448 if (dev->resource[i].flags & flags)
1451 err = do_pci_enable_device(dev, bars);
1453 atomic_dec(&dev->enable_cnt);
1458 * pci_enable_device_io - Initialize a device for use with IO space
1459 * @dev: PCI device to be initialized
1461 * Initialize device before it's used by a driver. Ask low-level code
1462 * to enable I/O resources. Wake up the device if it was suspended.
1463 * Beware, this function can fail.
1465 int pci_enable_device_io(struct pci_dev *dev)
1467 return pci_enable_device_flags(dev, IORESOURCE_IO);
1469 EXPORT_SYMBOL(pci_enable_device_io);
1472 * pci_enable_device_mem - Initialize a device for use with Memory space
1473 * @dev: PCI device to be initialized
1475 * Initialize device before it's used by a driver. Ask low-level code
1476 * to enable Memory resources. Wake up the device if it was suspended.
1477 * Beware, this function can fail.
1479 int pci_enable_device_mem(struct pci_dev *dev)
1481 return pci_enable_device_flags(dev, IORESOURCE_MEM);
1483 EXPORT_SYMBOL(pci_enable_device_mem);
1486 * pci_enable_device - Initialize device before it's used by a driver.
1487 * @dev: PCI device to be initialized
1489 * Initialize device before it's used by a driver. Ask low-level code
1490 * to enable I/O and memory. Wake up the device if it was suspended.
1491 * Beware, this function can fail.
1493 * Note we don't actually enable the device many times if we call
1494 * this function repeatedly (we just increment the count).
1496 int pci_enable_device(struct pci_dev *dev)
1498 return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
1500 EXPORT_SYMBOL(pci_enable_device);
1503 * Managed PCI resources. This manages device on/off, intx/msi/msix
1504 * on/off and BAR regions. pci_dev itself records msi/msix status, so
1505 * there's no need to track it separately. pci_devres is initialized
1506 * when a device is enabled using managed PCI device enable interface.
1509 unsigned int enabled:1;
1510 unsigned int pinned:1;
1511 unsigned int orig_intx:1;
1512 unsigned int restore_intx:1;
1517 static void pcim_release(struct device *gendev, void *res)
1519 struct pci_dev *dev = to_pci_dev(gendev);
1520 struct pci_devres *this = res;
1523 if (dev->msi_enabled)
1524 pci_disable_msi(dev);
1525 if (dev->msix_enabled)
1526 pci_disable_msix(dev);
1528 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1529 if (this->region_mask & (1 << i))
1530 pci_release_region(dev, i);
1535 if (this->restore_intx)
1536 pci_intx(dev, this->orig_intx);
1538 if (this->enabled && !this->pinned)
1539 pci_disable_device(dev);
1542 static struct pci_devres *get_pci_dr(struct pci_dev *pdev)
1544 struct pci_devres *dr, *new_dr;
1546 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
1550 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
1553 return devres_get(&pdev->dev, new_dr, NULL, NULL);
1556 static struct pci_devres *find_pci_dr(struct pci_dev *pdev)
1558 if (pci_is_managed(pdev))
1559 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
1564 * pcim_enable_device - Managed pci_enable_device()
1565 * @pdev: PCI device to be initialized
1567 * Managed pci_enable_device().
1569 int pcim_enable_device(struct pci_dev *pdev)
1571 struct pci_devres *dr;
1574 dr = get_pci_dr(pdev);
1580 rc = pci_enable_device(pdev);
1582 pdev->is_managed = 1;
1587 EXPORT_SYMBOL(pcim_enable_device);
1590 * pcim_pin_device - Pin managed PCI device
1591 * @pdev: PCI device to pin
1593 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1594 * driver detach. @pdev must have been enabled with
1595 * pcim_enable_device().
1597 void pcim_pin_device(struct pci_dev *pdev)
1599 struct pci_devres *dr;
1601 dr = find_pci_dr(pdev);
1602 WARN_ON(!dr || !dr->enabled);
1606 EXPORT_SYMBOL(pcim_pin_device);
1609 * pcibios_add_device - provide arch specific hooks when adding device dev
1610 * @dev: the PCI device being added
1612 * Permits the platform to provide architecture specific functionality when
1613 * devices are added. This is the default implementation. Architecture
1614 * implementations can override this.
1616 int __weak pcibios_add_device(struct pci_dev *dev)
1622 * pcibios_release_device - provide arch specific hooks when releasing device dev
1623 * @dev: the PCI device being released
1625 * Permits the platform to provide architecture specific functionality when
1626 * devices are released. This is the default implementation. Architecture
1627 * implementations can override this.
1629 void __weak pcibios_release_device(struct pci_dev *dev) {}
1632 * pcibios_disable_device - disable arch specific PCI resources for device dev
1633 * @dev: the PCI device to disable
1635 * Disables architecture specific PCI resources for the device. This
1636 * is the default implementation. Architecture implementations can
1639 void __weak pcibios_disable_device(struct pci_dev *dev) {}
1642 * pcibios_penalize_isa_irq - penalize an ISA IRQ
1643 * @irq: ISA IRQ to penalize
1644 * @active: IRQ active or not
1646 * Permits the platform to provide architecture-specific functionality when
1647 * penalizing ISA IRQs. This is the default implementation. Architecture
1648 * implementations can override this.
1650 void __weak pcibios_penalize_isa_irq(int irq, int active) {}
1652 static void do_pci_disable_device(struct pci_dev *dev)
1656 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
1657 if (pci_command & PCI_COMMAND_MASTER) {
1658 pci_command &= ~PCI_COMMAND_MASTER;
1659 pci_write_config_word(dev, PCI_COMMAND, pci_command);
1662 pcibios_disable_device(dev);
1666 * pci_disable_enabled_device - Disable device without updating enable_cnt
1667 * @dev: PCI device to disable
1669 * NOTE: This function is a backend of PCI power management routines and is
1670 * not supposed to be called drivers.
1672 void pci_disable_enabled_device(struct pci_dev *dev)
1674 if (pci_is_enabled(dev))
1675 do_pci_disable_device(dev);
1679 * pci_disable_device - Disable PCI device after use
1680 * @dev: PCI device to be disabled
1682 * Signal to the system that the PCI device is not in use by the system
1683 * anymore. This only involves disabling PCI bus-mastering, if active.
1685 * Note we don't actually disable the device until all callers of
1686 * pci_enable_device() have called pci_disable_device().
1688 void pci_disable_device(struct pci_dev *dev)
1690 struct pci_devres *dr;
1692 dr = find_pci_dr(dev);
1696 dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0,
1697 "disabling already-disabled device");
1699 if (atomic_dec_return(&dev->enable_cnt) != 0)
1702 do_pci_disable_device(dev);
1704 dev->is_busmaster = 0;
1706 EXPORT_SYMBOL(pci_disable_device);
1709 * pcibios_set_pcie_reset_state - set reset state for device dev
1710 * @dev: the PCIe device reset
1711 * @state: Reset state to enter into
1714 * Sets the PCIe reset state for the device. This is the default
1715 * implementation. Architecture implementations can override this.
1717 int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,
1718 enum pcie_reset_state state)
1724 * pci_set_pcie_reset_state - set reset state for device dev
1725 * @dev: the PCIe device reset
1726 * @state: Reset state to enter into
1729 * Sets the PCI reset state for the device.
1731 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1733 return pcibios_set_pcie_reset_state(dev, state);
1735 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);
1738 * pcie_clear_root_pme_status - Clear root port PME interrupt status.
1739 * @dev: PCIe root port or event collector.
1741 void pcie_clear_root_pme_status(struct pci_dev *dev)
1743 pcie_capability_set_dword(dev, PCI_EXP_RTSTA, PCI_EXP_RTSTA_PME);
1747 * pci_check_pme_status - Check if given device has generated PME.
1748 * @dev: Device to check.
1750 * Check the PME status of the device and if set, clear it and clear PME enable
1751 * (if set). Return 'true' if PME status and PME enable were both set or
1752 * 'false' otherwise.
1754 bool pci_check_pme_status(struct pci_dev *dev)
1763 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
1764 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
1765 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
1768 /* Clear PME status. */
1769 pmcsr |= PCI_PM_CTRL_PME_STATUS;
1770 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
1771 /* Disable PME to avoid interrupt flood. */
1772 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1776 pci_write_config_word(dev, pmcsr_pos, pmcsr);
1782 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
1783 * @dev: Device to handle.
1784 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
1786 * Check if @dev has generated PME and queue a resume request for it in that
1789 static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset)
1791 if (pme_poll_reset && dev->pme_poll)
1792 dev->pme_poll = false;
1794 if (pci_check_pme_status(dev)) {
1795 pci_wakeup_event(dev);
1796 pm_request_resume(&dev->dev);
1802 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
1803 * @bus: Top bus of the subtree to walk.
1805 void pci_pme_wakeup_bus(struct pci_bus *bus)
1808 pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
1813 * pci_pme_capable - check the capability of PCI device to generate PME#
1814 * @dev: PCI device to handle.
1815 * @state: PCI state from which device will issue PME#.
1817 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
1822 return !!(dev->pme_support & (1 << state));
1824 EXPORT_SYMBOL(pci_pme_capable);
1826 static void pci_pme_list_scan(struct work_struct *work)
1828 struct pci_pme_device *pme_dev, *n;
1830 mutex_lock(&pci_pme_list_mutex);
1831 list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) {
1832 if (pme_dev->dev->pme_poll) {
1833 struct pci_dev *bridge;
1835 bridge = pme_dev->dev->bus->self;
1837 * If bridge is in low power state, the
1838 * configuration space of subordinate devices
1839 * may be not accessible
1841 if (bridge && bridge->current_state != PCI_D0)
1843 pci_pme_wakeup(pme_dev->dev, NULL);
1845 list_del(&pme_dev->list);
1849 if (!list_empty(&pci_pme_list))
1850 queue_delayed_work(system_freezable_wq, &pci_pme_work,
1851 msecs_to_jiffies(PME_TIMEOUT));
1852 mutex_unlock(&pci_pme_list_mutex);
1855 static void __pci_pme_active(struct pci_dev *dev, bool enable)
1859 if (!dev->pme_support)
1862 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1863 /* Clear PME_Status by writing 1 to it and enable PME# */
1864 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1866 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1868 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1872 * pci_pme_restore - Restore PME configuration after config space restore.
1873 * @dev: PCI device to update.
1875 void pci_pme_restore(struct pci_dev *dev)
1879 if (!dev->pme_support)
1882 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1883 if (dev->wakeup_prepared) {
1884 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
1885 pmcsr &= ~PCI_PM_CTRL_PME_STATUS;
1887 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1888 pmcsr |= PCI_PM_CTRL_PME_STATUS;
1890 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1894 * pci_pme_active - enable or disable PCI device's PME# function
1895 * @dev: PCI device to handle.
1896 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1898 * The caller must verify that the device is capable of generating PME# before
1899 * calling this function with @enable equal to 'true'.
1901 void pci_pme_active(struct pci_dev *dev, bool enable)
1903 __pci_pme_active(dev, enable);
1906 * PCI (as opposed to PCIe) PME requires that the device have
1907 * its PME# line hooked up correctly. Not all hardware vendors
1908 * do this, so the PME never gets delivered and the device
1909 * remains asleep. The easiest way around this is to
1910 * periodically walk the list of suspended devices and check
1911 * whether any have their PME flag set. The assumption is that
1912 * we'll wake up often enough anyway that this won't be a huge
1913 * hit, and the power savings from the devices will still be a
1916 * Although PCIe uses in-band PME message instead of PME# line
1917 * to report PME, PME does not work for some PCIe devices in
1918 * reality. For example, there are devices that set their PME
1919 * status bits, but don't really bother to send a PME message;
1920 * there are PCI Express Root Ports that don't bother to
1921 * trigger interrupts when they receive PME messages from the
1922 * devices below. So PME poll is used for PCIe devices too.
1925 if (dev->pme_poll) {
1926 struct pci_pme_device *pme_dev;
1928 pme_dev = kmalloc(sizeof(struct pci_pme_device),
1931 pci_warn(dev, "can't enable PME#\n");
1935 mutex_lock(&pci_pme_list_mutex);
1936 list_add(&pme_dev->list, &pci_pme_list);
1937 if (list_is_singular(&pci_pme_list))
1938 queue_delayed_work(system_freezable_wq,
1940 msecs_to_jiffies(PME_TIMEOUT));
1941 mutex_unlock(&pci_pme_list_mutex);
1943 mutex_lock(&pci_pme_list_mutex);
1944 list_for_each_entry(pme_dev, &pci_pme_list, list) {
1945 if (pme_dev->dev == dev) {
1946 list_del(&pme_dev->list);
1951 mutex_unlock(&pci_pme_list_mutex);
1955 pci_dbg(dev, "PME# %s\n", enable ? "enabled" : "disabled");
1957 EXPORT_SYMBOL(pci_pme_active);
1960 * __pci_enable_wake - enable PCI device as wakeup event source
1961 * @dev: PCI device affected
1962 * @state: PCI state from which device will issue wakeup events
1963 * @enable: True to enable event generation; false to disable
1965 * This enables the device as a wakeup event source, or disables it.
1966 * When such events involves platform-specific hooks, those hooks are
1967 * called automatically by this routine.
1969 * Devices with legacy power management (no standard PCI PM capabilities)
1970 * always require such platform hooks.
1973 * 0 is returned on success
1974 * -EINVAL is returned if device is not supposed to wake up the system
1975 * Error code depending on the platform is returned if both the platform and
1976 * the native mechanism fail to enable the generation of wake-up events
1978 static int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable)
1983 * Bridges can only signal wakeup on behalf of subordinate devices,
1984 * but that is set up elsewhere, so skip them.
1986 if (pci_has_subordinate(dev))
1989 /* Don't do the same thing twice in a row for one device. */
1990 if (!!enable == !!dev->wakeup_prepared)
1994 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1995 * Anderson we should be doing PME# wake enable followed by ACPI wake
1996 * enable. To disable wake-up we call the platform first, for symmetry.
2002 if (pci_pme_capable(dev, state))
2003 pci_pme_active(dev, true);
2006 error = platform_pci_set_wakeup(dev, true);
2010 dev->wakeup_prepared = true;
2012 platform_pci_set_wakeup(dev, false);
2013 pci_pme_active(dev, false);
2014 dev->wakeup_prepared = false;
2021 * pci_enable_wake - change wakeup settings for a PCI device
2022 * @pci_dev: Target device
2023 * @state: PCI state from which device will issue wakeup events
2024 * @enable: Whether or not to enable event generation
2026 * If @enable is set, check device_may_wakeup() for the device before calling
2027 * __pci_enable_wake() for it.
2029 int pci_enable_wake(struct pci_dev *pci_dev, pci_power_t state, bool enable)
2031 if (enable && !device_may_wakeup(&pci_dev->dev))
2034 return __pci_enable_wake(pci_dev, state, enable);
2036 EXPORT_SYMBOL(pci_enable_wake);
2039 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
2040 * @dev: PCI device to prepare
2041 * @enable: True to enable wake-up event generation; false to disable
2043 * Many drivers want the device to wake up the system from D3_hot or D3_cold
2044 * and this function allows them to set that up cleanly - pci_enable_wake()
2045 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
2046 * ordering constraints.
2048 * This function only returns error code if the device is not allowed to wake
2049 * up the system from sleep or it is not capable of generating PME# from both
2050 * D3_hot and D3_cold and the platform is unable to enable wake-up power for it.
2052 int pci_wake_from_d3(struct pci_dev *dev, bool enable)
2054 return pci_pme_capable(dev, PCI_D3cold) ?
2055 pci_enable_wake(dev, PCI_D3cold, enable) :
2056 pci_enable_wake(dev, PCI_D3hot, enable);
2058 EXPORT_SYMBOL(pci_wake_from_d3);
2061 * pci_target_state - find an appropriate low power state for a given PCI dev
2063 * @wakeup: Whether or not wakeup functionality will be enabled for the device.
2065 * Use underlying platform code to find a supported low power state for @dev.
2066 * If the platform can't manage @dev, return the deepest state from which it
2067 * can generate wake events, based on any available PME info.
2069 static pci_power_t pci_target_state(struct pci_dev *dev, bool wakeup)
2071 pci_power_t target_state = PCI_D3hot;
2073 if (platform_pci_power_manageable(dev)) {
2075 * Call the platform to find the target state for the device.
2077 pci_power_t state = platform_pci_choose_state(dev);
2080 case PCI_POWER_ERROR:
2085 if (pci_no_d1d2(dev))
2088 target_state = state;
2091 return target_state;
2095 target_state = PCI_D0;
2098 * If the device is in D3cold even though it's not power-manageable by
2099 * the platform, it may have been powered down by non-standard means.
2100 * Best to let it slumber.
2102 if (dev->current_state == PCI_D3cold)
2103 target_state = PCI_D3cold;
2107 * Find the deepest state from which the device can generate
2110 if (dev->pme_support) {
2112 && !(dev->pme_support & (1 << target_state)))
2117 return target_state;
2121 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
2122 * @dev: Device to handle.
2124 * Choose the power state appropriate for the device depending on whether
2125 * it can wake up the system and/or is power manageable by the platform
2126 * (PCI_D3hot is the default) and put the device into that state.
2128 int pci_prepare_to_sleep(struct pci_dev *dev)
2130 bool wakeup = device_may_wakeup(&dev->dev);
2131 pci_power_t target_state = pci_target_state(dev, wakeup);
2134 if (target_state == PCI_POWER_ERROR)
2137 pci_enable_wake(dev, target_state, wakeup);
2139 error = pci_set_power_state(dev, target_state);
2142 pci_enable_wake(dev, target_state, false);
2146 EXPORT_SYMBOL(pci_prepare_to_sleep);
2149 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
2150 * @dev: Device to handle.
2152 * Disable device's system wake-up capability and put it into D0.
2154 int pci_back_from_sleep(struct pci_dev *dev)
2156 pci_enable_wake(dev, PCI_D0, false);
2157 return pci_set_power_state(dev, PCI_D0);
2159 EXPORT_SYMBOL(pci_back_from_sleep);
2162 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
2163 * @dev: PCI device being suspended.
2165 * Prepare @dev to generate wake-up events at run time and put it into a low
2168 int pci_finish_runtime_suspend(struct pci_dev *dev)
2170 pci_power_t target_state;
2173 target_state = pci_target_state(dev, device_can_wakeup(&dev->dev));
2174 if (target_state == PCI_POWER_ERROR)
2177 dev->runtime_d3cold = target_state == PCI_D3cold;
2179 __pci_enable_wake(dev, target_state, pci_dev_run_wake(dev));
2181 error = pci_set_power_state(dev, target_state);
2184 pci_enable_wake(dev, target_state, false);
2185 dev->runtime_d3cold = false;
2192 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
2193 * @dev: Device to check.
2195 * Return true if the device itself is capable of generating wake-up events
2196 * (through the platform or using the native PCIe PME) or if the device supports
2197 * PME and one of its upstream bridges can generate wake-up events.
2199 bool pci_dev_run_wake(struct pci_dev *dev)
2201 struct pci_bus *bus = dev->bus;
2203 if (!dev->pme_support)
2206 /* PME-capable in principle, but not from the target power state */
2207 if (!pci_pme_capable(dev, pci_target_state(dev, true)))
2210 if (device_can_wakeup(&dev->dev))
2213 while (bus->parent) {
2214 struct pci_dev *bridge = bus->self;
2216 if (device_can_wakeup(&bridge->dev))
2222 /* We have reached the root bus. */
2224 return device_can_wakeup(bus->bridge);
2228 EXPORT_SYMBOL_GPL(pci_dev_run_wake);
2231 * pci_dev_keep_suspended - Check if the device can stay in the suspended state.
2232 * @pci_dev: Device to check.
2234 * Return 'true' if the device is runtime-suspended, it doesn't have to be
2235 * reconfigured due to wakeup settings difference between system and runtime
2236 * suspend and the current power state of it is suitable for the upcoming
2237 * (system) transition.
2239 * If the device is not configured for system wakeup, disable PME for it before
2240 * returning 'true' to prevent it from waking up the system unnecessarily.
2242 bool pci_dev_keep_suspended(struct pci_dev *pci_dev)
2244 struct device *dev = &pci_dev->dev;
2245 bool wakeup = device_may_wakeup(dev);
2247 if (!pm_runtime_suspended(dev)
2248 || pci_target_state(pci_dev, wakeup) != pci_dev->current_state
2249 || platform_pci_need_resume(pci_dev))
2253 * At this point the device is good to go unless it's been configured
2254 * to generate PME at the runtime suspend time, but it is not supposed
2255 * to wake up the system. In that case, simply disable PME for it
2256 * (it will have to be re-enabled on exit from system resume).
2258 * If the device's power state is D3cold and the platform check above
2259 * hasn't triggered, the device's configuration is suitable and we don't
2260 * need to manipulate it at all.
2262 spin_lock_irq(&dev->power.lock);
2264 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold &&
2266 __pci_pme_active(pci_dev, false);
2268 spin_unlock_irq(&dev->power.lock);
2273 * pci_dev_complete_resume - Finalize resume from system sleep for a device.
2274 * @pci_dev: Device to handle.
2276 * If the device is runtime suspended and wakeup-capable, enable PME for it as
2277 * it might have been disabled during the prepare phase of system suspend if
2278 * the device was not configured for system wakeup.
2280 void pci_dev_complete_resume(struct pci_dev *pci_dev)
2282 struct device *dev = &pci_dev->dev;
2284 if (!pci_dev_run_wake(pci_dev))
2287 spin_lock_irq(&dev->power.lock);
2289 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold)
2290 __pci_pme_active(pci_dev, true);
2292 spin_unlock_irq(&dev->power.lock);
2295 void pci_config_pm_runtime_get(struct pci_dev *pdev)
2297 struct device *dev = &pdev->dev;
2298 struct device *parent = dev->parent;
2301 pm_runtime_get_sync(parent);
2302 pm_runtime_get_noresume(dev);
2304 * pdev->current_state is set to PCI_D3cold during suspending,
2305 * so wait until suspending completes
2307 pm_runtime_barrier(dev);
2309 * Only need to resume devices in D3cold, because config
2310 * registers are still accessible for devices suspended but
2313 if (pdev->current_state == PCI_D3cold)
2314 pm_runtime_resume(dev);
2317 void pci_config_pm_runtime_put(struct pci_dev *pdev)
2319 struct device *dev = &pdev->dev;
2320 struct device *parent = dev->parent;
2322 pm_runtime_put(dev);
2324 pm_runtime_put_sync(parent);
2328 * pci_bridge_d3_possible - Is it possible to put the bridge into D3
2329 * @bridge: Bridge to check
2331 * This function checks if it is possible to move the bridge to D3.
2332 * Currently we only allow D3 for recent enough PCIe ports.
2334 bool pci_bridge_d3_possible(struct pci_dev *bridge)
2336 if (!pci_is_pcie(bridge))
2339 switch (pci_pcie_type(bridge)) {
2340 case PCI_EXP_TYPE_ROOT_PORT:
2341 case PCI_EXP_TYPE_UPSTREAM:
2342 case PCI_EXP_TYPE_DOWNSTREAM:
2343 if (pci_bridge_d3_disable)
2347 * Hotplug interrupts cannot be delivered if the link is down,
2348 * so parents of a hotplug port must stay awake. In addition,
2349 * hotplug ports handled by firmware in System Management Mode
2350 * may not be put into D3 by the OS (Thunderbolt on non-Macs).
2351 * For simplicity, disallow in general for now.
2353 if (bridge->is_hotplug_bridge)
2356 if (pci_bridge_d3_force)
2360 * It should be safe to put PCIe ports from 2015 or newer
2363 if (dmi_get_bios_year() >= 2015)
2371 static int pci_dev_check_d3cold(struct pci_dev *dev, void *data)
2373 bool *d3cold_ok = data;
2375 if (/* The device needs to be allowed to go D3cold ... */
2376 dev->no_d3cold || !dev->d3cold_allowed ||
2378 /* ... and if it is wakeup capable to do so from D3cold. */
2379 (device_may_wakeup(&dev->dev) &&
2380 !pci_pme_capable(dev, PCI_D3cold)) ||
2382 /* If it is a bridge it must be allowed to go to D3. */
2383 !pci_power_manageable(dev))
2391 * pci_bridge_d3_update - Update bridge D3 capabilities
2392 * @dev: PCI device which is changed
2394 * Update upstream bridge PM capabilities accordingly depending on if the
2395 * device PM configuration was changed or the device is being removed. The
2396 * change is also propagated upstream.
2398 void pci_bridge_d3_update(struct pci_dev *dev)
2400 bool remove = !device_is_registered(&dev->dev);
2401 struct pci_dev *bridge;
2402 bool d3cold_ok = true;
2404 bridge = pci_upstream_bridge(dev);
2405 if (!bridge || !pci_bridge_d3_possible(bridge))
2409 * If D3 is currently allowed for the bridge, removing one of its
2410 * children won't change that.
2412 if (remove && bridge->bridge_d3)
2416 * If D3 is currently allowed for the bridge and a child is added or
2417 * changed, disallowance of D3 can only be caused by that child, so
2418 * we only need to check that single device, not any of its siblings.
2420 * If D3 is currently not allowed for the bridge, checking the device
2421 * first may allow us to skip checking its siblings.
2424 pci_dev_check_d3cold(dev, &d3cold_ok);
2427 * If D3 is currently not allowed for the bridge, this may be caused
2428 * either by the device being changed/removed or any of its siblings,
2429 * so we need to go through all children to find out if one of them
2430 * continues to block D3.
2432 if (d3cold_ok && !bridge->bridge_d3)
2433 pci_walk_bus(bridge->subordinate, pci_dev_check_d3cold,
2436 if (bridge->bridge_d3 != d3cold_ok) {
2437 bridge->bridge_d3 = d3cold_ok;
2438 /* Propagate change to upstream bridges */
2439 pci_bridge_d3_update(bridge);
2444 * pci_d3cold_enable - Enable D3cold for device
2445 * @dev: PCI device to handle
2447 * This function can be used in drivers to enable D3cold from the device
2448 * they handle. It also updates upstream PCI bridge PM capabilities
2451 void pci_d3cold_enable(struct pci_dev *dev)
2453 if (dev->no_d3cold) {
2454 dev->no_d3cold = false;
2455 pci_bridge_d3_update(dev);
2458 EXPORT_SYMBOL_GPL(pci_d3cold_enable);
2461 * pci_d3cold_disable - Disable D3cold for device
2462 * @dev: PCI device to handle
2464 * This function can be used in drivers to disable D3cold from the device
2465 * they handle. It also updates upstream PCI bridge PM capabilities
2468 void pci_d3cold_disable(struct pci_dev *dev)
2470 if (!dev->no_d3cold) {
2471 dev->no_d3cold = true;
2472 pci_bridge_d3_update(dev);
2475 EXPORT_SYMBOL_GPL(pci_d3cold_disable);
2478 * pci_pm_init - Initialize PM functions of given PCI device
2479 * @dev: PCI device to handle.
2481 void pci_pm_init(struct pci_dev *dev)
2486 pm_runtime_forbid(&dev->dev);
2487 pm_runtime_set_active(&dev->dev);
2488 pm_runtime_enable(&dev->dev);
2489 device_enable_async_suspend(&dev->dev);
2490 dev->wakeup_prepared = false;
2493 dev->pme_support = 0;
2495 /* find PCI PM capability in list */
2496 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
2499 /* Check device's ability to generate PME# */
2500 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
2502 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
2503 pci_err(dev, "unsupported PM cap regs version (%u)\n",
2504 pmc & PCI_PM_CAP_VER_MASK);
2509 dev->d3_delay = PCI_PM_D3_WAIT;
2510 dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
2511 dev->bridge_d3 = pci_bridge_d3_possible(dev);
2512 dev->d3cold_allowed = true;
2514 dev->d1_support = false;
2515 dev->d2_support = false;
2516 if (!pci_no_d1d2(dev)) {
2517 if (pmc & PCI_PM_CAP_D1)
2518 dev->d1_support = true;
2519 if (pmc & PCI_PM_CAP_D2)
2520 dev->d2_support = true;
2522 if (dev->d1_support || dev->d2_support)
2523 pci_printk(KERN_DEBUG, dev, "supports%s%s\n",
2524 dev->d1_support ? " D1" : "",
2525 dev->d2_support ? " D2" : "");
2528 pmc &= PCI_PM_CAP_PME_MASK;
2530 pci_printk(KERN_DEBUG, dev, "PME# supported from%s%s%s%s%s\n",
2531 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
2532 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
2533 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
2534 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
2535 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
2536 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
2537 dev->pme_poll = true;
2539 * Make device's PM flags reflect the wake-up capability, but
2540 * let the user space enable it to wake up the system as needed.
2542 device_set_wakeup_capable(&dev->dev, true);
2543 /* Disable the PME# generation functionality */
2544 pci_pme_active(dev, false);
2548 static unsigned long pci_ea_flags(struct pci_dev *dev, u8 prop)
2550 unsigned long flags = IORESOURCE_PCI_FIXED | IORESOURCE_PCI_EA_BEI;
2554 case PCI_EA_P_VF_MEM:
2555 flags |= IORESOURCE_MEM;
2557 case PCI_EA_P_MEM_PREFETCH:
2558 case PCI_EA_P_VF_MEM_PREFETCH:
2559 flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
2562 flags |= IORESOURCE_IO;
2571 static struct resource *pci_ea_get_resource(struct pci_dev *dev, u8 bei,
2574 if (bei <= PCI_EA_BEI_BAR5 && prop <= PCI_EA_P_IO)
2575 return &dev->resource[bei];
2576 #ifdef CONFIG_PCI_IOV
2577 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5 &&
2578 (prop == PCI_EA_P_VF_MEM || prop == PCI_EA_P_VF_MEM_PREFETCH))
2579 return &dev->resource[PCI_IOV_RESOURCES +
2580 bei - PCI_EA_BEI_VF_BAR0];
2582 else if (bei == PCI_EA_BEI_ROM)
2583 return &dev->resource[PCI_ROM_RESOURCE];
2588 /* Read an Enhanced Allocation (EA) entry */
2589 static int pci_ea_read(struct pci_dev *dev, int offset)
2591 struct resource *res;
2592 int ent_size, ent_offset = offset;
2593 resource_size_t start, end;
2594 unsigned long flags;
2595 u32 dw0, bei, base, max_offset;
2597 bool support_64 = (sizeof(resource_size_t) >= 8);
2599 pci_read_config_dword(dev, ent_offset, &dw0);
2602 /* Entry size field indicates DWORDs after 1st */
2603 ent_size = ((dw0 & PCI_EA_ES) + 1) << 2;
2605 if (!(dw0 & PCI_EA_ENABLE)) /* Entry not enabled */
2608 bei = (dw0 & PCI_EA_BEI) >> 4;
2609 prop = (dw0 & PCI_EA_PP) >> 8;
2612 * If the Property is in the reserved range, try the Secondary
2615 if (prop > PCI_EA_P_BRIDGE_IO && prop < PCI_EA_P_MEM_RESERVED)
2616 prop = (dw0 & PCI_EA_SP) >> 16;
2617 if (prop > PCI_EA_P_BRIDGE_IO)
2620 res = pci_ea_get_resource(dev, bei, prop);
2622 pci_err(dev, "Unsupported EA entry BEI: %u\n", bei);
2626 flags = pci_ea_flags(dev, prop);
2628 pci_err(dev, "Unsupported EA properties: %#x\n", prop);
2633 pci_read_config_dword(dev, ent_offset, &base);
2634 start = (base & PCI_EA_FIELD_MASK);
2637 /* Read MaxOffset */
2638 pci_read_config_dword(dev, ent_offset, &max_offset);
2641 /* Read Base MSBs (if 64-bit entry) */
2642 if (base & PCI_EA_IS_64) {
2645 pci_read_config_dword(dev, ent_offset, &base_upper);
2648 flags |= IORESOURCE_MEM_64;
2650 /* entry starts above 32-bit boundary, can't use */
2651 if (!support_64 && base_upper)
2655 start |= ((u64)base_upper << 32);
2658 end = start + (max_offset | 0x03);
2660 /* Read MaxOffset MSBs (if 64-bit entry) */
2661 if (max_offset & PCI_EA_IS_64) {
2662 u32 max_offset_upper;
2664 pci_read_config_dword(dev, ent_offset, &max_offset_upper);
2667 flags |= IORESOURCE_MEM_64;
2669 /* entry too big, can't use */
2670 if (!support_64 && max_offset_upper)
2674 end += ((u64)max_offset_upper << 32);
2678 pci_err(dev, "EA Entry crosses address boundary\n");
2682 if (ent_size != ent_offset - offset) {
2683 pci_err(dev, "EA Entry Size (%d) does not match length read (%d)\n",
2684 ent_size, ent_offset - offset);
2688 res->name = pci_name(dev);
2693 if (bei <= PCI_EA_BEI_BAR5)
2694 pci_printk(KERN_DEBUG, dev, "BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
2696 else if (bei == PCI_EA_BEI_ROM)
2697 pci_printk(KERN_DEBUG, dev, "ROM: %pR (from Enhanced Allocation, properties %#02x)\n",
2699 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5)
2700 pci_printk(KERN_DEBUG, dev, "VF BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
2701 bei - PCI_EA_BEI_VF_BAR0, res, prop);
2703 pci_printk(KERN_DEBUG, dev, "BEI %d res: %pR (from Enhanced Allocation, properties %#02x)\n",
2707 return offset + ent_size;
2710 /* Enhanced Allocation Initialization */
2711 void pci_ea_init(struct pci_dev *dev)
2718 /* find PCI EA capability in list */
2719 ea = pci_find_capability(dev, PCI_CAP_ID_EA);
2723 /* determine the number of entries */
2724 pci_bus_read_config_byte(dev->bus, dev->devfn, ea + PCI_EA_NUM_ENT,
2726 num_ent &= PCI_EA_NUM_ENT_MASK;
2728 offset = ea + PCI_EA_FIRST_ENT;
2730 /* Skip DWORD 2 for type 1 functions */
2731 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
2734 /* parse each EA entry */
2735 for (i = 0; i < num_ent; ++i)
2736 offset = pci_ea_read(dev, offset);
2739 static void pci_add_saved_cap(struct pci_dev *pci_dev,
2740 struct pci_cap_saved_state *new_cap)
2742 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
2746 * _pci_add_cap_save_buffer - allocate buffer for saving given
2747 * capability registers
2748 * @dev: the PCI device
2749 * @cap: the capability to allocate the buffer for
2750 * @extended: Standard or Extended capability ID
2751 * @size: requested size of the buffer
2753 static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap,
2754 bool extended, unsigned int size)
2757 struct pci_cap_saved_state *save_state;
2760 pos = pci_find_ext_capability(dev, cap);
2762 pos = pci_find_capability(dev, cap);
2767 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
2771 save_state->cap.cap_nr = cap;
2772 save_state->cap.cap_extended = extended;
2773 save_state->cap.size = size;
2774 pci_add_saved_cap(dev, save_state);
2779 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size)
2781 return _pci_add_cap_save_buffer(dev, cap, false, size);
2784 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size)
2786 return _pci_add_cap_save_buffer(dev, cap, true, size);
2790 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
2791 * @dev: the PCI device
2793 void pci_allocate_cap_save_buffers(struct pci_dev *dev)
2797 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
2798 PCI_EXP_SAVE_REGS * sizeof(u16));
2800 pci_err(dev, "unable to preallocate PCI Express save buffer\n");
2802 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
2804 pci_err(dev, "unable to preallocate PCI-X save buffer\n");
2806 pci_allocate_vc_save_buffers(dev);
2809 void pci_free_cap_save_buffers(struct pci_dev *dev)
2811 struct pci_cap_saved_state *tmp;
2812 struct hlist_node *n;
2814 hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next)
2819 * pci_configure_ari - enable or disable ARI forwarding
2820 * @dev: the PCI device
2822 * If @dev and its upstream bridge both support ARI, enable ARI in the
2823 * bridge. Otherwise, disable ARI in the bridge.
2825 void pci_configure_ari(struct pci_dev *dev)
2828 struct pci_dev *bridge;
2830 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
2833 bridge = dev->bus->self;
2837 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
2838 if (!(cap & PCI_EXP_DEVCAP2_ARI))
2841 if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) {
2842 pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
2843 PCI_EXP_DEVCTL2_ARI);
2844 bridge->ari_enabled = 1;
2846 pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2,
2847 PCI_EXP_DEVCTL2_ARI);
2848 bridge->ari_enabled = 0;
2852 static int pci_acs_enable;
2855 * pci_request_acs - ask for ACS to be enabled if supported
2857 void pci_request_acs(void)
2863 * pci_std_enable_acs - enable ACS on devices using standard ACS capabilites
2864 * @dev: the PCI device
2866 static void pci_std_enable_acs(struct pci_dev *dev)
2872 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
2876 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
2877 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
2879 /* Source Validation */
2880 ctrl |= (cap & PCI_ACS_SV);
2882 /* P2P Request Redirect */
2883 ctrl |= (cap & PCI_ACS_RR);
2885 /* P2P Completion Redirect */
2886 ctrl |= (cap & PCI_ACS_CR);
2888 /* Upstream Forwarding */
2889 ctrl |= (cap & PCI_ACS_UF);
2891 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
2895 * pci_enable_acs - enable ACS if hardware support it
2896 * @dev: the PCI device
2898 void pci_enable_acs(struct pci_dev *dev)
2900 if (!pci_acs_enable)
2903 if (!pci_dev_specific_enable_acs(dev))
2906 pci_std_enable_acs(dev);
2909 static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags)
2914 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS);
2919 * Except for egress control, capabilities are either required
2920 * or only required if controllable. Features missing from the
2921 * capability field can therefore be assumed as hard-wired enabled.
2923 pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap);
2924 acs_flags &= (cap | PCI_ACS_EC);
2926 pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl);
2927 return (ctrl & acs_flags) == acs_flags;
2931 * pci_acs_enabled - test ACS against required flags for a given device
2932 * @pdev: device to test
2933 * @acs_flags: required PCI ACS flags
2935 * Return true if the device supports the provided flags. Automatically
2936 * filters out flags that are not implemented on multifunction devices.
2938 * Note that this interface checks the effective ACS capabilities of the
2939 * device rather than the actual capabilities. For instance, most single
2940 * function endpoints are not required to support ACS because they have no
2941 * opportunity for peer-to-peer access. We therefore return 'true'
2942 * regardless of whether the device exposes an ACS capability. This makes
2943 * it much easier for callers of this function to ignore the actual type
2944 * or topology of the device when testing ACS support.
2946 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
2950 ret = pci_dev_specific_acs_enabled(pdev, acs_flags);
2955 * Conventional PCI and PCI-X devices never support ACS, either
2956 * effectively or actually. The shared bus topology implies that
2957 * any device on the bus can receive or snoop DMA.
2959 if (!pci_is_pcie(pdev))
2962 switch (pci_pcie_type(pdev)) {
2964 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec,
2965 * but since their primary interface is PCI/X, we conservatively
2966 * handle them as we would a non-PCIe device.
2968 case PCI_EXP_TYPE_PCIE_BRIDGE:
2970 * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never
2971 * applicable... must never implement an ACS Extended Capability...".
2972 * This seems arbitrary, but we take a conservative interpretation
2973 * of this statement.
2975 case PCI_EXP_TYPE_PCI_BRIDGE:
2976 case PCI_EXP_TYPE_RC_EC:
2979 * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should
2980 * implement ACS in order to indicate their peer-to-peer capabilities,
2981 * regardless of whether they are single- or multi-function devices.
2983 case PCI_EXP_TYPE_DOWNSTREAM:
2984 case PCI_EXP_TYPE_ROOT_PORT:
2985 return pci_acs_flags_enabled(pdev, acs_flags);
2987 * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be
2988 * implemented by the remaining PCIe types to indicate peer-to-peer
2989 * capabilities, but only when they are part of a multifunction
2990 * device. The footnote for section 6.12 indicates the specific
2991 * PCIe types included here.
2993 case PCI_EXP_TYPE_ENDPOINT:
2994 case PCI_EXP_TYPE_UPSTREAM:
2995 case PCI_EXP_TYPE_LEG_END:
2996 case PCI_EXP_TYPE_RC_END:
2997 if (!pdev->multifunction)
3000 return pci_acs_flags_enabled(pdev, acs_flags);
3004 * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable
3005 * to single function devices with the exception of downstream ports.
3011 * pci_acs_path_enable - test ACS flags from start to end in a hierarchy
3012 * @start: starting downstream device
3013 * @end: ending upstream device or NULL to search to the root bus
3014 * @acs_flags: required flags
3016 * Walk up a device tree from start to end testing PCI ACS support. If
3017 * any step along the way does not support the required flags, return false.
3019 bool pci_acs_path_enabled(struct pci_dev *start,
3020 struct pci_dev *end, u16 acs_flags)
3022 struct pci_dev *pdev, *parent = start;
3027 if (!pci_acs_enabled(pdev, acs_flags))
3030 if (pci_is_root_bus(pdev->bus))
3031 return (end == NULL);
3033 parent = pdev->bus->self;
3034 } while (pdev != end);
3040 * pci_rebar_find_pos - find position of resize ctrl reg for BAR
3044 * Helper to find the position of the ctrl register for a BAR.
3045 * Returns -ENOTSUPP if resizable BARs are not supported at all.
3046 * Returns -ENOENT if no ctrl register for the BAR could be found.
3048 static int pci_rebar_find_pos(struct pci_dev *pdev, int bar)
3050 unsigned int pos, nbars, i;
3053 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR);
3057 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3058 nbars = (ctrl & PCI_REBAR_CTRL_NBAR_MASK) >>
3059 PCI_REBAR_CTRL_NBAR_SHIFT;
3061 for (i = 0; i < nbars; i++, pos += 8) {
3064 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3065 bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX;
3074 * pci_rebar_get_possible_sizes - get possible sizes for BAR
3076 * @bar: BAR to query
3078 * Get the possible sizes of a resizable BAR as bitmask defined in the spec
3079 * (bit 0=1MB, bit 19=512GB). Returns 0 if BAR isn't resizable.
3081 u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar)
3086 pos = pci_rebar_find_pos(pdev, bar);
3090 pci_read_config_dword(pdev, pos + PCI_REBAR_CAP, &cap);
3091 return (cap & PCI_REBAR_CAP_SIZES) >> 4;
3095 * pci_rebar_get_current_size - get the current size of a BAR
3097 * @bar: BAR to set size to
3099 * Read the size of a BAR from the resizable BAR config.
3100 * Returns size if found or negative error code.
3102 int pci_rebar_get_current_size(struct pci_dev *pdev, int bar)
3107 pos = pci_rebar_find_pos(pdev, bar);
3111 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3112 return (ctrl & PCI_REBAR_CTRL_BAR_SIZE) >> 8;
3116 * pci_rebar_set_size - set a new size for a BAR
3118 * @bar: BAR to set size to
3119 * @size: new size as defined in the spec (0=1MB, 19=512GB)
3121 * Set the new size of a BAR as defined in the spec.
3122 * Returns zero if resizing was successful, error code otherwise.
3124 int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size)
3129 pos = pci_rebar_find_pos(pdev, bar);
3133 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3134 ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE;
3136 pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl);
3141 * pci_enable_atomic_ops_to_root - enable AtomicOp requests to root port
3142 * @dev: the PCI device
3143 * @cap_mask: mask of desired AtomicOp sizes, including one or more of:
3144 * PCI_EXP_DEVCAP2_ATOMIC_COMP32
3145 * PCI_EXP_DEVCAP2_ATOMIC_COMP64
3146 * PCI_EXP_DEVCAP2_ATOMIC_COMP128
3148 * Return 0 if all upstream bridges support AtomicOp routing, egress
3149 * blocking is disabled on all upstream ports, and the root port supports
3150 * the requested completion capabilities (32-bit, 64-bit and/or 128-bit
3151 * AtomicOp completion), or negative otherwise.
3153 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask)
3155 struct pci_bus *bus = dev->bus;
3156 struct pci_dev *bridge;
3159 if (!pci_is_pcie(dev))
3163 * Per PCIe r4.0, sec 6.15, endpoints and root ports may be
3164 * AtomicOp requesters. For now, we only support endpoints as
3165 * requesters and root ports as completers. No endpoints as
3166 * completers, and no peer-to-peer.
3169 switch (pci_pcie_type(dev)) {
3170 case PCI_EXP_TYPE_ENDPOINT:
3171 case PCI_EXP_TYPE_LEG_END:
3172 case PCI_EXP_TYPE_RC_END:
3178 while (bus->parent) {
3181 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
3183 switch (pci_pcie_type(bridge)) {
3184 /* Ensure switch ports support AtomicOp routing */
3185 case PCI_EXP_TYPE_UPSTREAM:
3186 case PCI_EXP_TYPE_DOWNSTREAM:
3187 if (!(cap & PCI_EXP_DEVCAP2_ATOMIC_ROUTE))
3191 /* Ensure root port supports all the sizes we care about */
3192 case PCI_EXP_TYPE_ROOT_PORT:
3193 if ((cap & cap_mask) != cap_mask)
3198 /* Ensure upstream ports don't block AtomicOps on egress */
3199 if (!bridge->has_secondary_link) {
3200 pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2,
3202 if (ctl2 & PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK)
3209 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
3210 PCI_EXP_DEVCTL2_ATOMIC_REQ);
3213 EXPORT_SYMBOL(pci_enable_atomic_ops_to_root);
3216 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
3217 * @dev: the PCI device
3218 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)
3220 * Perform INTx swizzling for a device behind one level of bridge. This is
3221 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
3222 * behind bridges on add-in cards. For devices with ARI enabled, the slot
3223 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
3224 * the PCI Express Base Specification, Revision 2.1)
3226 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin)
3230 if (pci_ari_enabled(dev->bus))
3233 slot = PCI_SLOT(dev->devfn);
3235 return (((pin - 1) + slot) % 4) + 1;
3238 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
3246 while (!pci_is_root_bus(dev->bus)) {
3247 pin = pci_swizzle_interrupt_pin(dev, pin);
3248 dev = dev->bus->self;
3255 * pci_common_swizzle - swizzle INTx all the way to root bridge
3256 * @dev: the PCI device
3257 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
3259 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
3260 * bridges all the way up to a PCI root bus.
3262 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
3266 while (!pci_is_root_bus(dev->bus)) {
3267 pin = pci_swizzle_interrupt_pin(dev, pin);
3268 dev = dev->bus->self;
3271 return PCI_SLOT(dev->devfn);
3273 EXPORT_SYMBOL_GPL(pci_common_swizzle);
3276 * pci_release_region - Release a PCI bar
3277 * @pdev: PCI device whose resources were previously reserved by pci_request_region
3278 * @bar: BAR to release
3280 * Releases the PCI I/O and memory resources previously reserved by a
3281 * successful call to pci_request_region. Call this function only
3282 * after all use of the PCI regions has ceased.
3284 void pci_release_region(struct pci_dev *pdev, int bar)
3286 struct pci_devres *dr;
3288 if (pci_resource_len(pdev, bar) == 0)
3290 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
3291 release_region(pci_resource_start(pdev, bar),
3292 pci_resource_len(pdev, bar));
3293 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
3294 release_mem_region(pci_resource_start(pdev, bar),
3295 pci_resource_len(pdev, bar));
3297 dr = find_pci_dr(pdev);
3299 dr->region_mask &= ~(1 << bar);
3301 EXPORT_SYMBOL(pci_release_region);
3304 * __pci_request_region - Reserved PCI I/O and memory resource
3305 * @pdev: PCI device whose resources are to be reserved
3306 * @bar: BAR to be reserved
3307 * @res_name: Name to be associated with resource.
3308 * @exclusive: whether the region access is exclusive or not
3310 * Mark the PCI region associated with PCI device @pdev BR @bar as
3311 * being reserved by owner @res_name. Do not access any
3312 * address inside the PCI regions unless this call returns
3315 * If @exclusive is set, then the region is marked so that userspace
3316 * is explicitly not allowed to map the resource via /dev/mem or
3317 * sysfs MMIO access.
3319 * Returns 0 on success, or %EBUSY on error. A warning
3320 * message is also printed on failure.
3322 static int __pci_request_region(struct pci_dev *pdev, int bar,
3323 const char *res_name, int exclusive)
3325 struct pci_devres *dr;
3327 if (pci_resource_len(pdev, bar) == 0)
3330 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
3331 if (!request_region(pci_resource_start(pdev, bar),
3332 pci_resource_len(pdev, bar), res_name))
3334 } else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
3335 if (!__request_mem_region(pci_resource_start(pdev, bar),
3336 pci_resource_len(pdev, bar), res_name,
3341 dr = find_pci_dr(pdev);
3343 dr->region_mask |= 1 << bar;
3348 pci_warn(pdev, "BAR %d: can't reserve %pR\n", bar,
3349 &pdev->resource[bar]);
3354 * pci_request_region - Reserve PCI I/O and memory resource
3355 * @pdev: PCI device whose resources are to be reserved
3356 * @bar: BAR to be reserved
3357 * @res_name: Name to be associated with resource
3359 * Mark the PCI region associated with PCI device @pdev BAR @bar as
3360 * being reserved by owner @res_name. Do not access any
3361 * address inside the PCI regions unless this call returns
3364 * Returns 0 on success, or %EBUSY on error. A warning
3365 * message is also printed on failure.
3367 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
3369 return __pci_request_region(pdev, bar, res_name, 0);
3371 EXPORT_SYMBOL(pci_request_region);
3374 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
3375 * @pdev: PCI device whose resources are to be reserved
3376 * @bar: BAR to be reserved
3377 * @res_name: Name to be associated with resource.
3379 * Mark the PCI region associated with PCI device @pdev BR @bar as
3380 * being reserved by owner @res_name. Do not access any
3381 * address inside the PCI regions unless this call returns
3384 * Returns 0 on success, or %EBUSY on error. A warning
3385 * message is also printed on failure.
3387 * The key difference that _exclusive makes it that userspace is
3388 * explicitly not allowed to map the resource via /dev/mem or
3391 int pci_request_region_exclusive(struct pci_dev *pdev, int bar,
3392 const char *res_name)
3394 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
3396 EXPORT_SYMBOL(pci_request_region_exclusive);
3399 * pci_release_selected_regions - Release selected PCI I/O and memory resources
3400 * @pdev: PCI device whose resources were previously reserved
3401 * @bars: Bitmask of BARs to be released
3403 * Release selected PCI I/O and memory resources previously reserved.
3404 * Call this function only after all use of the PCI regions has ceased.
3406 void pci_release_selected_regions(struct pci_dev *pdev, int bars)
3410 for (i = 0; i < 6; i++)
3411 if (bars & (1 << i))
3412 pci_release_region(pdev, i);
3414 EXPORT_SYMBOL(pci_release_selected_regions);
3416 static int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
3417 const char *res_name, int excl)
3421 for (i = 0; i < 6; i++)
3422 if (bars & (1 << i))
3423 if (__pci_request_region(pdev, i, res_name, excl))
3429 if (bars & (1 << i))
3430 pci_release_region(pdev, i);
3437 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
3438 * @pdev: PCI device whose resources are to be reserved
3439 * @bars: Bitmask of BARs to be requested
3440 * @res_name: Name to be associated with resource
3442 int pci_request_selected_regions(struct pci_dev *pdev, int bars,
3443 const char *res_name)
3445 return __pci_request_selected_regions(pdev, bars, res_name, 0);
3447 EXPORT_SYMBOL(pci_request_selected_regions);
3449 int pci_request_selected_regions_exclusive(struct pci_dev *pdev, int bars,
3450 const char *res_name)
3452 return __pci_request_selected_regions(pdev, bars, res_name,
3453 IORESOURCE_EXCLUSIVE);
3455 EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
3458 * pci_release_regions - Release reserved PCI I/O and memory resources
3459 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
3461 * Releases all PCI I/O and memory resources previously reserved by a
3462 * successful call to pci_request_regions. Call this function only
3463 * after all use of the PCI regions has ceased.
3466 void pci_release_regions(struct pci_dev *pdev)
3468 pci_release_selected_regions(pdev, (1 << 6) - 1);
3470 EXPORT_SYMBOL(pci_release_regions);
3473 * pci_request_regions - Reserved PCI I/O and memory resources
3474 * @pdev: PCI device whose resources are to be reserved
3475 * @res_name: Name to be associated with resource.
3477 * Mark all PCI regions associated with PCI device @pdev as
3478 * being reserved by owner @res_name. Do not access any
3479 * address inside the PCI regions unless this call returns
3482 * Returns 0 on success, or %EBUSY on error. A warning
3483 * message is also printed on failure.
3485 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
3487 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
3489 EXPORT_SYMBOL(pci_request_regions);
3492 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
3493 * @pdev: PCI device whose resources are to be reserved
3494 * @res_name: Name to be associated with resource.
3496 * Mark all PCI regions associated with PCI device @pdev as
3497 * being reserved by owner @res_name. Do not access any
3498 * address inside the PCI regions unless this call returns
3501 * pci_request_regions_exclusive() will mark the region so that
3502 * /dev/mem and the sysfs MMIO access will not be allowed.
3504 * Returns 0 on success, or %EBUSY on error. A warning
3505 * message is also printed on failure.
3507 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
3509 return pci_request_selected_regions_exclusive(pdev,
3510 ((1 << 6) - 1), res_name);
3512 EXPORT_SYMBOL(pci_request_regions_exclusive);
3515 * Record the PCI IO range (expressed as CPU physical address + size).
3516 * Return a negative value if an error has occured, zero otherwise
3518 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
3519 resource_size_t size)
3523 struct logic_pio_hwaddr *range;
3525 if (!size || addr + size < addr)
3528 range = kzalloc(sizeof(*range), GFP_ATOMIC);
3532 range->fwnode = fwnode;
3534 range->hw_start = addr;
3535 range->flags = LOGIC_PIO_CPU_MMIO;
3537 ret = logic_pio_register_range(range);
3545 phys_addr_t pci_pio_to_address(unsigned long pio)
3547 phys_addr_t address = (phys_addr_t)OF_BAD_ADDR;
3550 if (pio >= MMIO_UPPER_LIMIT)
3553 address = logic_pio_to_hwaddr(pio);
3559 unsigned long __weak pci_address_to_pio(phys_addr_t address)
3562 return logic_pio_trans_cpuaddr(address);
3564 if (address > IO_SPACE_LIMIT)
3565 return (unsigned long)-1;
3567 return (unsigned long) address;
3572 * pci_remap_iospace - Remap the memory mapped I/O space
3573 * @res: Resource describing the I/O space
3574 * @phys_addr: physical address of range to be mapped
3576 * Remap the memory mapped I/O space described by the @res
3577 * and the CPU physical address @phys_addr into virtual address space.
3578 * Only architectures that have memory mapped IO functions defined
3579 * (and the PCI_IOBASE value defined) should call this function.
3581 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr)
3583 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
3584 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
3586 if (!(res->flags & IORESOURCE_IO))
3589 if (res->end > IO_SPACE_LIMIT)
3592 return ioremap_page_range(vaddr, vaddr + resource_size(res), phys_addr,
3593 pgprot_device(PAGE_KERNEL));
3595 /* this architecture does not have memory mapped I/O space,
3596 so this function should never be called */
3597 WARN_ONCE(1, "This architecture does not support memory mapped I/O\n");
3601 EXPORT_SYMBOL(pci_remap_iospace);
3604 * pci_unmap_iospace - Unmap the memory mapped I/O space
3605 * @res: resource to be unmapped
3607 * Unmap the CPU virtual address @res from virtual address space.
3608 * Only architectures that have memory mapped IO functions defined
3609 * (and the PCI_IOBASE value defined) should call this function.
3611 void pci_unmap_iospace(struct resource *res)
3613 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
3614 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
3616 unmap_kernel_range(vaddr, resource_size(res));
3619 EXPORT_SYMBOL(pci_unmap_iospace);
3621 static void devm_pci_unmap_iospace(struct device *dev, void *ptr)
3623 struct resource **res = ptr;
3625 pci_unmap_iospace(*res);
3629 * devm_pci_remap_iospace - Managed pci_remap_iospace()
3630 * @dev: Generic device to remap IO address for
3631 * @res: Resource describing the I/O space
3632 * @phys_addr: physical address of range to be mapped
3634 * Managed pci_remap_iospace(). Map is automatically unmapped on driver
3637 int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
3638 phys_addr_t phys_addr)
3640 const struct resource **ptr;
3643 ptr = devres_alloc(devm_pci_unmap_iospace, sizeof(*ptr), GFP_KERNEL);
3647 error = pci_remap_iospace(res, phys_addr);
3652 devres_add(dev, ptr);
3657 EXPORT_SYMBOL(devm_pci_remap_iospace);
3660 * devm_pci_remap_cfgspace - Managed pci_remap_cfgspace()
3661 * @dev: Generic device to remap IO address for
3662 * @offset: Resource address to map
3663 * @size: Size of map
3665 * Managed pci_remap_cfgspace(). Map is automatically unmapped on driver
3668 void __iomem *devm_pci_remap_cfgspace(struct device *dev,
3669 resource_size_t offset,
3670 resource_size_t size)
3672 void __iomem **ptr, *addr;
3674 ptr = devres_alloc(devm_ioremap_release, sizeof(*ptr), GFP_KERNEL);
3678 addr = pci_remap_cfgspace(offset, size);
3681 devres_add(dev, ptr);
3687 EXPORT_SYMBOL(devm_pci_remap_cfgspace);
3690 * devm_pci_remap_cfg_resource - check, request region and ioremap cfg resource
3691 * @dev: generic device to handle the resource for
3692 * @res: configuration space resource to be handled
3694 * Checks that a resource is a valid memory region, requests the memory
3695 * region and ioremaps with pci_remap_cfgspace() API that ensures the
3696 * proper PCI configuration space memory attributes are guaranteed.
3698 * All operations are managed and will be undone on driver detach.
3700 * Returns a pointer to the remapped memory or an ERR_PTR() encoded error code
3701 * on failure. Usage example::
3703 * res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3704 * base = devm_pci_remap_cfg_resource(&pdev->dev, res);
3706 * return PTR_ERR(base);
3708 void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
3709 struct resource *res)
3711 resource_size_t size;
3713 void __iomem *dest_ptr;
3717 if (!res || resource_type(res) != IORESOURCE_MEM) {
3718 dev_err(dev, "invalid resource\n");
3719 return IOMEM_ERR_PTR(-EINVAL);
3722 size = resource_size(res);
3723 name = res->name ?: dev_name(dev);
3725 if (!devm_request_mem_region(dev, res->start, size, name)) {
3726 dev_err(dev, "can't request region for resource %pR\n", res);
3727 return IOMEM_ERR_PTR(-EBUSY);
3730 dest_ptr = devm_pci_remap_cfgspace(dev, res->start, size);
3732 dev_err(dev, "ioremap failed for resource %pR\n", res);
3733 devm_release_mem_region(dev, res->start, size);
3734 dest_ptr = IOMEM_ERR_PTR(-ENOMEM);
3739 EXPORT_SYMBOL(devm_pci_remap_cfg_resource);
3741 static void __pci_set_master(struct pci_dev *dev, bool enable)
3745 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
3747 cmd = old_cmd | PCI_COMMAND_MASTER;
3749 cmd = old_cmd & ~PCI_COMMAND_MASTER;
3750 if (cmd != old_cmd) {
3751 pci_dbg(dev, "%s bus mastering\n",
3752 enable ? "enabling" : "disabling");
3753 pci_write_config_word(dev, PCI_COMMAND, cmd);
3755 dev->is_busmaster = enable;
3759 * pcibios_setup - process "pci=" kernel boot arguments
3760 * @str: string used to pass in "pci=" kernel boot arguments
3762 * Process kernel boot arguments. This is the default implementation.
3763 * Architecture specific implementations can override this as necessary.
3765 char * __weak __init pcibios_setup(char *str)
3771 * pcibios_set_master - enable PCI bus-mastering for device dev
3772 * @dev: the PCI device to enable
3774 * Enables PCI bus-mastering for the device. This is the default
3775 * implementation. Architecture specific implementations can override
3776 * this if necessary.
3778 void __weak pcibios_set_master(struct pci_dev *dev)
3782 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
3783 if (pci_is_pcie(dev))
3786 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
3788 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
3789 else if (lat > pcibios_max_latency)
3790 lat = pcibios_max_latency;
3794 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
3798 * pci_set_master - enables bus-mastering for device dev
3799 * @dev: the PCI device to enable
3801 * Enables bus-mastering on the device and calls pcibios_set_master()
3802 * to do the needed arch specific settings.
3804 void pci_set_master(struct pci_dev *dev)
3806 __pci_set_master(dev, true);
3807 pcibios_set_master(dev);
3809 EXPORT_SYMBOL(pci_set_master);
3812 * pci_clear_master - disables bus-mastering for device dev
3813 * @dev: the PCI device to disable
3815 void pci_clear_master(struct pci_dev *dev)
3817 __pci_set_master(dev, false);
3819 EXPORT_SYMBOL(pci_clear_master);
3822 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
3823 * @dev: the PCI device for which MWI is to be enabled
3825 * Helper function for pci_set_mwi.
3826 * Originally copied from drivers/net/acenic.c.
3827 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
3829 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3831 int pci_set_cacheline_size(struct pci_dev *dev)
3835 if (!pci_cache_line_size)
3838 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
3839 equal to or multiple of the right value. */
3840 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
3841 if (cacheline_size >= pci_cache_line_size &&
3842 (cacheline_size % pci_cache_line_size) == 0)
3845 /* Write the correct value. */
3846 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
3848 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
3849 if (cacheline_size == pci_cache_line_size)
3852 pci_printk(KERN_DEBUG, dev, "cache line size of %d is not supported\n",
3853 pci_cache_line_size << 2);
3857 EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
3860 * pci_set_mwi - enables memory-write-invalidate PCI transaction
3861 * @dev: the PCI device for which MWI is enabled
3863 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
3865 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3867 int pci_set_mwi(struct pci_dev *dev)
3869 #ifdef PCI_DISABLE_MWI
3875 rc = pci_set_cacheline_size(dev);
3879 pci_read_config_word(dev, PCI_COMMAND, &cmd);
3880 if (!(cmd & PCI_COMMAND_INVALIDATE)) {
3881 pci_dbg(dev, "enabling Mem-Wr-Inval\n");
3882 cmd |= PCI_COMMAND_INVALIDATE;
3883 pci_write_config_word(dev, PCI_COMMAND, cmd);
3888 EXPORT_SYMBOL(pci_set_mwi);
3891 * pcim_set_mwi - a device-managed pci_set_mwi()
3892 * @dev: the PCI device for which MWI is enabled
3894 * Managed pci_set_mwi().
3896 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3898 int pcim_set_mwi(struct pci_dev *dev)
3900 struct pci_devres *dr;
3902 dr = find_pci_dr(dev);
3907 return pci_set_mwi(dev);
3909 EXPORT_SYMBOL(pcim_set_mwi);
3912 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
3913 * @dev: the PCI device for which MWI is enabled
3915 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
3916 * Callers are not required to check the return value.
3918 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3920 int pci_try_set_mwi(struct pci_dev *dev)
3922 #ifdef PCI_DISABLE_MWI
3925 return pci_set_mwi(dev);
3928 EXPORT_SYMBOL(pci_try_set_mwi);
3931 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
3932 * @dev: the PCI device to disable
3934 * Disables PCI Memory-Write-Invalidate transaction on the device
3936 void pci_clear_mwi(struct pci_dev *dev)
3938 #ifndef PCI_DISABLE_MWI
3941 pci_read_config_word(dev, PCI_COMMAND, &cmd);
3942 if (cmd & PCI_COMMAND_INVALIDATE) {
3943 cmd &= ~PCI_COMMAND_INVALIDATE;
3944 pci_write_config_word(dev, PCI_COMMAND, cmd);
3948 EXPORT_SYMBOL(pci_clear_mwi);
3951 * pci_intx - enables/disables PCI INTx for device dev
3952 * @pdev: the PCI device to operate on
3953 * @enable: boolean: whether to enable or disable PCI INTx
3955 * Enables/disables PCI INTx for device dev
3957 void pci_intx(struct pci_dev *pdev, int enable)
3959 u16 pci_command, new;
3961 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
3964 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
3966 new = pci_command | PCI_COMMAND_INTX_DISABLE;
3968 if (new != pci_command) {
3969 struct pci_devres *dr;
3971 pci_write_config_word(pdev, PCI_COMMAND, new);
3973 dr = find_pci_dr(pdev);
3974 if (dr && !dr->restore_intx) {
3975 dr->restore_intx = 1;
3976 dr->orig_intx = !enable;
3980 EXPORT_SYMBOL_GPL(pci_intx);
3982 static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)
3984 struct pci_bus *bus = dev->bus;
3985 bool mask_updated = true;
3986 u32 cmd_status_dword;
3987 u16 origcmd, newcmd;
3988 unsigned long flags;
3992 * We do a single dword read to retrieve both command and status.
3993 * Document assumptions that make this possible.
3995 BUILD_BUG_ON(PCI_COMMAND % 4);
3996 BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS);
3998 raw_spin_lock_irqsave(&pci_lock, flags);
4000 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword);
4002 irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT;
4005 * Check interrupt status register to see whether our device
4006 * triggered the interrupt (when masking) or the next IRQ is
4007 * already pending (when unmasking).
4009 if (mask != irq_pending) {
4010 mask_updated = false;
4014 origcmd = cmd_status_dword;
4015 newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE;
4017 newcmd |= PCI_COMMAND_INTX_DISABLE;
4018 if (newcmd != origcmd)
4019 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd);
4022 raw_spin_unlock_irqrestore(&pci_lock, flags);
4024 return mask_updated;
4028 * pci_check_and_mask_intx - mask INTx on pending interrupt
4029 * @dev: the PCI device to operate on
4031 * Check if the device dev has its INTx line asserted, mask it and
4032 * return true in that case. False is returned if no interrupt was
4035 bool pci_check_and_mask_intx(struct pci_dev *dev)
4037 return pci_check_and_set_intx_mask(dev, true);
4039 EXPORT_SYMBOL_GPL(pci_check_and_mask_intx);
4042 * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
4043 * @dev: the PCI device to operate on
4045 * Check if the device dev has its INTx line asserted, unmask it if not
4046 * and return true. False is returned and the mask remains active if
4047 * there was still an interrupt pending.
4049 bool pci_check_and_unmask_intx(struct pci_dev *dev)
4051 return pci_check_and_set_intx_mask(dev, false);
4053 EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
4056 * pci_wait_for_pending_transaction - waits for pending transaction
4057 * @dev: the PCI device to operate on
4059 * Return 0 if transaction is pending 1 otherwise.
4061 int pci_wait_for_pending_transaction(struct pci_dev *dev)
4063 if (!pci_is_pcie(dev))
4066 return pci_wait_for_pending(dev, pci_pcie_cap(dev) + PCI_EXP_DEVSTA,
4067 PCI_EXP_DEVSTA_TRPND);
4069 EXPORT_SYMBOL(pci_wait_for_pending_transaction);
4071 static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout)
4077 * After reset, the device should not silently discard config
4078 * requests, but it may still indicate that it needs more time by
4079 * responding to them with CRS completions. The Root Port will
4080 * generally synthesize ~0 data to complete the read (except when
4081 * CRS SV is enabled and the read was for the Vendor ID; in that
4082 * case it synthesizes 0x0001 data).
4084 * Wait for the device to return a non-CRS completion. Read the
4085 * Command register instead of Vendor ID so we don't have to
4086 * contend with the CRS SV value.
4088 pci_read_config_dword(dev, PCI_COMMAND, &id);
4090 if (delay > timeout) {
4091 pci_warn(dev, "not ready %dms after %s; giving up\n",
4092 delay - 1, reset_type);
4097 pci_info(dev, "not ready %dms after %s; waiting\n",
4098 delay - 1, reset_type);
4102 pci_read_config_dword(dev, PCI_COMMAND, &id);
4106 pci_info(dev, "ready %dms after %s\n", delay - 1,
4113 * pcie_has_flr - check if a device supports function level resets
4114 * @dev: device to check
4116 * Returns true if the device advertises support for PCIe function level
4119 static bool pcie_has_flr(struct pci_dev *dev)
4123 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET)
4126 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
4127 return cap & PCI_EXP_DEVCAP_FLR;
4131 * pcie_flr - initiate a PCIe function level reset
4132 * @dev: device to reset
4134 * Initiate a function level reset on @dev. The caller should ensure the
4135 * device supports FLR before calling this function, e.g. by using the
4136 * pcie_has_flr() helper.
4138 int pcie_flr(struct pci_dev *dev)
4140 if (!pci_wait_for_pending_transaction(dev))
4141 pci_err(dev, "timed out waiting for pending transaction; performing function level reset anyway\n");
4143 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
4146 * Per PCIe r4.0, sec 6.6.2, a device must complete an FLR within
4147 * 100ms, but may silently discard requests while the FLR is in
4148 * progress. Wait 100ms before trying to access the device.
4152 return pci_dev_wait(dev, "FLR", PCIE_RESET_READY_POLL_MS);
4154 EXPORT_SYMBOL_GPL(pcie_flr);
4156 static int pci_af_flr(struct pci_dev *dev, int probe)
4161 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
4165 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET)
4168 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
4169 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
4176 * Wait for Transaction Pending bit to clear. A word-aligned test
4177 * is used, so we use the conrol offset rather than status and shift
4178 * the test bit to match.
4180 if (!pci_wait_for_pending(dev, pos + PCI_AF_CTRL,
4181 PCI_AF_STATUS_TP << 8))
4182 pci_err(dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n");
4184 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
4187 * Per Advanced Capabilities for Conventional PCI ECN, 13 April 2006,
4188 * updated 27 July 2006; a device must complete an FLR within
4189 * 100ms, but may silently discard requests while the FLR is in
4190 * progress. Wait 100ms before trying to access the device.
4194 return pci_dev_wait(dev, "AF_FLR", PCIE_RESET_READY_POLL_MS);
4198 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
4199 * @dev: Device to reset.
4200 * @probe: If set, only check if the device can be reset this way.
4202 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
4203 * unset, it will be reinitialized internally when going from PCI_D3hot to
4204 * PCI_D0. If that's the case and the device is not in a low-power state
4205 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
4207 * NOTE: This causes the caller to sleep for twice the device power transition
4208 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
4209 * by default (i.e. unless the @dev's d3_delay field has a different value).
4210 * Moreover, only devices in D0 can be reset by this function.
4212 static int pci_pm_reset(struct pci_dev *dev, int probe)
4216 if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET)
4219 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
4220 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
4226 if (dev->current_state != PCI_D0)
4229 csr &= ~PCI_PM_CTRL_STATE_MASK;
4231 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
4232 pci_dev_d3_sleep(dev);
4234 csr &= ~PCI_PM_CTRL_STATE_MASK;
4236 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
4237 pci_dev_d3_sleep(dev);
4239 return pci_dev_wait(dev, "PM D3->D0", PCIE_RESET_READY_POLL_MS);
4242 * pcie_wait_for_link - Wait until link is active or inactive
4243 * @pdev: Bridge device
4244 * @active: waiting for active or inactive?
4246 * Use this to wait till link becomes active or inactive.
4248 bool pcie_wait_for_link(struct pci_dev *pdev, bool active)
4255 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
4256 ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA);
4265 pci_info(pdev, "Data Link Layer Link Active not %s in 1000 msec\n",
4266 active ? "set" : "cleared");
4271 void pci_reset_secondary_bus(struct pci_dev *dev)
4275 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
4276 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
4277 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
4280 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double
4281 * this to 2ms to ensure that we meet the minimum requirement.
4285 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
4286 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
4289 * Trhfa for conventional PCI is 2^25 clock cycles.
4290 * Assuming a minimum 33MHz clock this results in a 1s
4291 * delay before we can consider subordinate devices to
4292 * be re-initialized. PCIe has some ways to shorten this,
4293 * but we don't make use of them yet.
4298 void __weak pcibios_reset_secondary_bus(struct pci_dev *dev)
4300 pci_reset_secondary_bus(dev);
4304 * pci_reset_bridge_secondary_bus - Reset the secondary bus on a PCI bridge.
4305 * @dev: Bridge device
4307 * Use the bridge control register to assert reset on the secondary bus.
4308 * Devices on the secondary bus are left in power-on state.
4310 int pci_reset_bridge_secondary_bus(struct pci_dev *dev)
4312 pcibios_reset_secondary_bus(dev);
4314 return pci_dev_wait(dev, "bus reset", PCIE_RESET_READY_POLL_MS);
4316 EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus);
4318 static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
4320 struct pci_dev *pdev;
4322 if (pci_is_root_bus(dev->bus) || dev->subordinate ||
4323 !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
4326 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
4333 pci_reset_bridge_secondary_bus(dev->bus->self);
4338 static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, int probe)
4342 if (!hotplug || !try_module_get(hotplug->ops->owner))
4345 if (hotplug->ops->reset_slot)
4346 rc = hotplug->ops->reset_slot(hotplug, probe);
4348 module_put(hotplug->ops->owner);
4353 static int pci_dev_reset_slot_function(struct pci_dev *dev, int probe)
4355 struct pci_dev *pdev;
4357 if (dev->subordinate || !dev->slot ||
4358 dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
4361 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
4362 if (pdev != dev && pdev->slot == dev->slot)
4365 return pci_reset_hotplug_slot(dev->slot->hotplug, probe);
4368 static void pci_dev_lock(struct pci_dev *dev)
4370 pci_cfg_access_lock(dev);
4371 /* block PM suspend, driver probe, etc. */
4372 device_lock(&dev->dev);
4375 /* Return 1 on successful lock, 0 on contention */
4376 static int pci_dev_trylock(struct pci_dev *dev)
4378 if (pci_cfg_access_trylock(dev)) {
4379 if (device_trylock(&dev->dev))
4381 pci_cfg_access_unlock(dev);
4387 static void pci_dev_unlock(struct pci_dev *dev)
4389 device_unlock(&dev->dev);
4390 pci_cfg_access_unlock(dev);
4393 static void pci_dev_save_and_disable(struct pci_dev *dev)
4395 const struct pci_error_handlers *err_handler =
4396 dev->driver ? dev->driver->err_handler : NULL;
4399 * dev->driver->err_handler->reset_prepare() is protected against
4400 * races with ->remove() by the device lock, which must be held by
4403 if (err_handler && err_handler->reset_prepare)
4404 err_handler->reset_prepare(dev);
4407 * Wake-up device prior to save. PM registers default to D0 after
4408 * reset and a simple register restore doesn't reliably return
4409 * to a non-D0 state anyway.
4411 pci_set_power_state(dev, PCI_D0);
4413 pci_save_state(dev);
4415 * Disable the device by clearing the Command register, except for
4416 * INTx-disable which is set. This not only disables MMIO and I/O port
4417 * BARs, but also prevents the device from being Bus Master, preventing
4418 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3
4419 * compliant devices, INTx-disable prevents legacy interrupts.
4421 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
4424 static void pci_dev_restore(struct pci_dev *dev)
4426 const struct pci_error_handlers *err_handler =
4427 dev->driver ? dev->driver->err_handler : NULL;
4429 pci_restore_state(dev);
4432 * dev->driver->err_handler->reset_done() is protected against
4433 * races with ->remove() by the device lock, which must be held by
4436 if (err_handler && err_handler->reset_done)
4437 err_handler->reset_done(dev);
4441 * __pci_reset_function_locked - reset a PCI device function while holding
4442 * the @dev mutex lock.
4443 * @dev: PCI device to reset
4445 * Some devices allow an individual function to be reset without affecting
4446 * other functions in the same device. The PCI device must be responsive
4447 * to PCI config space in order to use this function.
4449 * The device function is presumed to be unused and the caller is holding
4450 * the device mutex lock when this function is called.
4451 * Resetting the device will make the contents of PCI configuration space
4452 * random, so any caller of this must be prepared to reinitialise the
4453 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
4456 * Returns 0 if the device function was successfully reset or negative if the
4457 * device doesn't support resetting a single function.
4459 int __pci_reset_function_locked(struct pci_dev *dev)
4466 * A reset method returns -ENOTTY if it doesn't support this device
4467 * and we should try the next method.
4469 * If it returns 0 (success), we're finished. If it returns any
4470 * other error, we're also finished: this indicates that further
4471 * reset mechanisms might be broken on the device.
4473 rc = pci_dev_specific_reset(dev, 0);
4476 if (pcie_has_flr(dev)) {
4481 rc = pci_af_flr(dev, 0);
4484 rc = pci_pm_reset(dev, 0);
4487 rc = pci_dev_reset_slot_function(dev, 0);
4490 return pci_parent_bus_reset(dev, 0);
4492 EXPORT_SYMBOL_GPL(__pci_reset_function_locked);
4495 * pci_probe_reset_function - check whether the device can be safely reset
4496 * @dev: PCI device to reset
4498 * Some devices allow an individual function to be reset without affecting
4499 * other functions in the same device. The PCI device must be responsive
4500 * to PCI config space in order to use this function.
4502 * Returns 0 if the device function can be reset or negative if the
4503 * device doesn't support resetting a single function.
4505 int pci_probe_reset_function(struct pci_dev *dev)
4511 rc = pci_dev_specific_reset(dev, 1);
4514 if (pcie_has_flr(dev))
4516 rc = pci_af_flr(dev, 1);
4519 rc = pci_pm_reset(dev, 1);
4522 rc = pci_dev_reset_slot_function(dev, 1);
4526 return pci_parent_bus_reset(dev, 1);
4530 * pci_reset_function - quiesce and reset a PCI device function
4531 * @dev: PCI device to reset
4533 * Some devices allow an individual function to be reset without affecting
4534 * other functions in the same device. The PCI device must be responsive
4535 * to PCI config space in order to use this function.
4537 * This function does not just reset the PCI portion of a device, but
4538 * clears all the state associated with the device. This function differs
4539 * from __pci_reset_function_locked() in that it saves and restores device state
4540 * over the reset and takes the PCI device lock.
4542 * Returns 0 if the device function was successfully reset or negative if the
4543 * device doesn't support resetting a single function.
4545 int pci_reset_function(struct pci_dev *dev)
4553 pci_dev_save_and_disable(dev);
4555 rc = __pci_reset_function_locked(dev);
4557 pci_dev_restore(dev);
4558 pci_dev_unlock(dev);
4562 EXPORT_SYMBOL_GPL(pci_reset_function);
4565 * pci_reset_function_locked - quiesce and reset a PCI device function
4566 * @dev: PCI device to reset
4568 * Some devices allow an individual function to be reset without affecting
4569 * other functions in the same device. The PCI device must be responsive
4570 * to PCI config space in order to use this function.
4572 * This function does not just reset the PCI portion of a device, but
4573 * clears all the state associated with the device. This function differs
4574 * from __pci_reset_function_locked() in that it saves and restores device state
4575 * over the reset. It also differs from pci_reset_function() in that it
4576 * requires the PCI device lock to be held.
4578 * Returns 0 if the device function was successfully reset or negative if the
4579 * device doesn't support resetting a single function.
4581 int pci_reset_function_locked(struct pci_dev *dev)
4588 pci_dev_save_and_disable(dev);
4590 rc = __pci_reset_function_locked(dev);
4592 pci_dev_restore(dev);
4596 EXPORT_SYMBOL_GPL(pci_reset_function_locked);
4599 * pci_try_reset_function - quiesce and reset a PCI device function
4600 * @dev: PCI device to reset
4602 * Same as above, except return -EAGAIN if unable to lock device.
4604 int pci_try_reset_function(struct pci_dev *dev)
4611 if (!pci_dev_trylock(dev))
4614 pci_dev_save_and_disable(dev);
4615 rc = __pci_reset_function_locked(dev);
4616 pci_dev_restore(dev);
4617 pci_dev_unlock(dev);
4621 EXPORT_SYMBOL_GPL(pci_try_reset_function);
4623 /* Do any devices on or below this bus prevent a bus reset? */
4624 static bool pci_bus_resetable(struct pci_bus *bus)
4626 struct pci_dev *dev;
4629 if (bus->self && (bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET))
4632 list_for_each_entry(dev, &bus->devices, bus_list) {
4633 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
4634 (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
4641 /* Lock devices from the top of the tree down */
4642 static void pci_bus_lock(struct pci_bus *bus)
4644 struct pci_dev *dev;
4646 list_for_each_entry(dev, &bus->devices, bus_list) {
4648 if (dev->subordinate)
4649 pci_bus_lock(dev->subordinate);
4653 /* Unlock devices from the bottom of the tree up */
4654 static void pci_bus_unlock(struct pci_bus *bus)
4656 struct pci_dev *dev;
4658 list_for_each_entry(dev, &bus->devices, bus_list) {
4659 if (dev->subordinate)
4660 pci_bus_unlock(dev->subordinate);
4661 pci_dev_unlock(dev);
4665 /* Return 1 on successful lock, 0 on contention */
4666 static int pci_bus_trylock(struct pci_bus *bus)
4668 struct pci_dev *dev;
4670 list_for_each_entry(dev, &bus->devices, bus_list) {
4671 if (!pci_dev_trylock(dev))
4673 if (dev->subordinate) {
4674 if (!pci_bus_trylock(dev->subordinate)) {
4675 pci_dev_unlock(dev);
4683 list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) {
4684 if (dev->subordinate)
4685 pci_bus_unlock(dev->subordinate);
4686 pci_dev_unlock(dev);
4691 /* Do any devices on or below this slot prevent a bus reset? */
4692 static bool pci_slot_resetable(struct pci_slot *slot)
4694 struct pci_dev *dev;
4696 if (slot->bus->self &&
4697 (slot->bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET))
4700 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4701 if (!dev->slot || dev->slot != slot)
4703 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
4704 (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
4711 /* Lock devices from the top of the tree down */
4712 static void pci_slot_lock(struct pci_slot *slot)
4714 struct pci_dev *dev;
4716 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4717 if (!dev->slot || dev->slot != slot)
4720 if (dev->subordinate)
4721 pci_bus_lock(dev->subordinate);
4725 /* Unlock devices from the bottom of the tree up */
4726 static void pci_slot_unlock(struct pci_slot *slot)
4728 struct pci_dev *dev;
4730 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4731 if (!dev->slot || dev->slot != slot)
4733 if (dev->subordinate)
4734 pci_bus_unlock(dev->subordinate);
4735 pci_dev_unlock(dev);
4739 /* Return 1 on successful lock, 0 on contention */
4740 static int pci_slot_trylock(struct pci_slot *slot)
4742 struct pci_dev *dev;
4744 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4745 if (!dev->slot || dev->slot != slot)
4747 if (!pci_dev_trylock(dev))
4749 if (dev->subordinate) {
4750 if (!pci_bus_trylock(dev->subordinate)) {
4751 pci_dev_unlock(dev);
4759 list_for_each_entry_continue_reverse(dev,
4760 &slot->bus->devices, bus_list) {
4761 if (!dev->slot || dev->slot != slot)
4763 if (dev->subordinate)
4764 pci_bus_unlock(dev->subordinate);
4765 pci_dev_unlock(dev);
4770 /* Save and disable devices from the top of the tree down */
4771 static void pci_bus_save_and_disable(struct pci_bus *bus)
4773 struct pci_dev *dev;
4775 list_for_each_entry(dev, &bus->devices, bus_list) {
4777 pci_dev_save_and_disable(dev);
4778 pci_dev_unlock(dev);
4779 if (dev->subordinate)
4780 pci_bus_save_and_disable(dev->subordinate);
4785 * Restore devices from top of the tree down - parent bridges need to be
4786 * restored before we can get to subordinate devices.
4788 static void pci_bus_restore(struct pci_bus *bus)
4790 struct pci_dev *dev;
4792 list_for_each_entry(dev, &bus->devices, bus_list) {
4794 pci_dev_restore(dev);
4795 pci_dev_unlock(dev);
4796 if (dev->subordinate)
4797 pci_bus_restore(dev->subordinate);
4801 /* Save and disable devices from the top of the tree down */
4802 static void pci_slot_save_and_disable(struct pci_slot *slot)
4804 struct pci_dev *dev;
4806 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4807 if (!dev->slot || dev->slot != slot)
4809 pci_dev_save_and_disable(dev);
4810 if (dev->subordinate)
4811 pci_bus_save_and_disable(dev->subordinate);
4816 * Restore devices from top of the tree down - parent bridges need to be
4817 * restored before we can get to subordinate devices.
4819 static void pci_slot_restore(struct pci_slot *slot)
4821 struct pci_dev *dev;
4823 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4824 if (!dev->slot || dev->slot != slot)
4827 pci_dev_restore(dev);
4828 pci_dev_unlock(dev);
4829 if (dev->subordinate)
4830 pci_bus_restore(dev->subordinate);
4834 static int pci_slot_reset(struct pci_slot *slot, int probe)
4838 if (!slot || !pci_slot_resetable(slot))
4842 pci_slot_lock(slot);
4846 rc = pci_reset_hotplug_slot(slot->hotplug, probe);
4849 pci_slot_unlock(slot);
4855 * pci_probe_reset_slot - probe whether a PCI slot can be reset
4856 * @slot: PCI slot to probe
4858 * Return 0 if slot can be reset, negative if a slot reset is not supported.
4860 int pci_probe_reset_slot(struct pci_slot *slot)
4862 return pci_slot_reset(slot, 1);
4864 EXPORT_SYMBOL_GPL(pci_probe_reset_slot);
4867 * pci_reset_slot - reset a PCI slot
4868 * @slot: PCI slot to reset
4870 * A PCI bus may host multiple slots, each slot may support a reset mechanism
4871 * independent of other slots. For instance, some slots may support slot power
4872 * control. In the case of a 1:1 bus to slot architecture, this function may
4873 * wrap the bus reset to avoid spurious slot related events such as hotplug.
4874 * Generally a slot reset should be attempted before a bus reset. All of the
4875 * function of the slot and any subordinate buses behind the slot are reset
4876 * through this function. PCI config space of all devices in the slot and
4877 * behind the slot is saved before and restored after reset.
4879 * Return 0 on success, non-zero on error.
4881 int pci_reset_slot(struct pci_slot *slot)
4885 rc = pci_slot_reset(slot, 1);
4889 pci_slot_save_and_disable(slot);
4891 rc = pci_slot_reset(slot, 0);
4893 pci_slot_restore(slot);
4897 EXPORT_SYMBOL_GPL(pci_reset_slot);
4900 * pci_try_reset_slot - Try to reset a PCI slot
4901 * @slot: PCI slot to reset
4903 * Same as above except return -EAGAIN if the slot cannot be locked
4905 int pci_try_reset_slot(struct pci_slot *slot)
4909 rc = pci_slot_reset(slot, 1);
4913 pci_slot_save_and_disable(slot);
4915 if (pci_slot_trylock(slot)) {
4917 rc = pci_reset_hotplug_slot(slot->hotplug, 0);
4918 pci_slot_unlock(slot);
4922 pci_slot_restore(slot);
4926 EXPORT_SYMBOL_GPL(pci_try_reset_slot);
4928 static int pci_bus_reset(struct pci_bus *bus, int probe)
4930 if (!bus->self || !pci_bus_resetable(bus))
4940 pci_reset_bridge_secondary_bus(bus->self);
4942 pci_bus_unlock(bus);
4948 * pci_probe_reset_bus - probe whether a PCI bus can be reset
4949 * @bus: PCI bus to probe
4951 * Return 0 if bus can be reset, negative if a bus reset is not supported.
4953 int pci_probe_reset_bus(struct pci_bus *bus)
4955 return pci_bus_reset(bus, 1);
4957 EXPORT_SYMBOL_GPL(pci_probe_reset_bus);
4960 * pci_reset_bus - reset a PCI bus
4961 * @bus: top level PCI bus to reset
4963 * Do a bus reset on the given bus and any subordinate buses, saving
4964 * and restoring state of all devices.
4966 * Return 0 on success, non-zero on error.
4968 int pci_reset_bus(struct pci_bus *bus)
4972 rc = pci_bus_reset(bus, 1);
4976 pci_bus_save_and_disable(bus);
4978 rc = pci_bus_reset(bus, 0);
4980 pci_bus_restore(bus);
4984 EXPORT_SYMBOL_GPL(pci_reset_bus);
4987 * pci_try_reset_bus - Try to reset a PCI bus
4988 * @bus: top level PCI bus to reset
4990 * Same as above except return -EAGAIN if the bus cannot be locked
4992 int pci_try_reset_bus(struct pci_bus *bus)
4996 rc = pci_bus_reset(bus, 1);
5000 pci_bus_save_and_disable(bus);
5002 if (pci_bus_trylock(bus)) {
5004 pci_reset_bridge_secondary_bus(bus->self);
5005 pci_bus_unlock(bus);
5009 pci_bus_restore(bus);
5013 EXPORT_SYMBOL_GPL(pci_try_reset_bus);
5016 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
5017 * @dev: PCI device to query
5019 * Returns mmrbc: maximum designed memory read count in bytes
5020 * or appropriate error value.
5022 int pcix_get_max_mmrbc(struct pci_dev *dev)
5027 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
5031 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
5034 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
5036 EXPORT_SYMBOL(pcix_get_max_mmrbc);
5039 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
5040 * @dev: PCI device to query
5042 * Returns mmrbc: maximum memory read count in bytes
5043 * or appropriate error value.
5045 int pcix_get_mmrbc(struct pci_dev *dev)
5050 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
5054 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
5057 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
5059 EXPORT_SYMBOL(pcix_get_mmrbc);
5062 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
5063 * @dev: PCI device to query
5064 * @mmrbc: maximum memory read count in bytes
5065 * valid values are 512, 1024, 2048, 4096
5067 * If possible sets maximum memory read byte count, some bridges have erratas
5068 * that prevent this.
5070 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
5076 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
5079 v = ffs(mmrbc) - 10;
5081 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
5085 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
5088 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
5091 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
5094 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
5096 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
5099 cmd &= ~PCI_X_CMD_MAX_READ;
5101 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
5106 EXPORT_SYMBOL(pcix_set_mmrbc);
5109 * pcie_get_readrq - get PCI Express read request size
5110 * @dev: PCI device to query
5112 * Returns maximum memory read request in bytes
5113 * or appropriate error value.
5115 int pcie_get_readrq(struct pci_dev *dev)
5119 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
5121 return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
5123 EXPORT_SYMBOL(pcie_get_readrq);
5126 * pcie_set_readrq - set PCI Express maximum memory read request
5127 * @dev: PCI device to query
5128 * @rq: maximum memory read count in bytes
5129 * valid values are 128, 256, 512, 1024, 2048, 4096
5131 * If possible sets maximum memory read request in bytes
5133 int pcie_set_readrq(struct pci_dev *dev, int rq)
5137 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
5141 * If using the "performance" PCIe config, we clamp the
5142 * read rq size to the max packet size to prevent the
5143 * host bridge generating requests larger than we can
5146 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
5147 int mps = pcie_get_mps(dev);
5153 v = (ffs(rq) - 8) << 12;
5155 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
5156 PCI_EXP_DEVCTL_READRQ, v);
5158 EXPORT_SYMBOL(pcie_set_readrq);
5161 * pcie_get_mps - get PCI Express maximum payload size
5162 * @dev: PCI device to query
5164 * Returns maximum payload size in bytes
5166 int pcie_get_mps(struct pci_dev *dev)
5170 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
5172 return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
5174 EXPORT_SYMBOL(pcie_get_mps);
5177 * pcie_set_mps - set PCI Express maximum payload size
5178 * @dev: PCI device to query
5179 * @mps: maximum payload size in bytes
5180 * valid values are 128, 256, 512, 1024, 2048, 4096
5182 * If possible sets maximum payload size
5184 int pcie_set_mps(struct pci_dev *dev, int mps)
5188 if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
5192 if (v > dev->pcie_mpss)
5196 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
5197 PCI_EXP_DEVCTL_PAYLOAD, v);
5199 EXPORT_SYMBOL(pcie_set_mps);
5202 * pcie_bandwidth_available - determine minimum link settings of a PCIe
5203 * device and its bandwidth limitation
5204 * @dev: PCI device to query
5205 * @limiting_dev: storage for device causing the bandwidth limitation
5206 * @speed: storage for speed of limiting device
5207 * @width: storage for width of limiting device
5209 * Walk up the PCI device chain and find the point where the minimum
5210 * bandwidth is available. Return the bandwidth available there and (if
5211 * limiting_dev, speed, and width pointers are supplied) information about
5212 * that point. The bandwidth returned is in Mb/s, i.e., megabits/second of
5215 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
5216 enum pci_bus_speed *speed,
5217 enum pcie_link_width *width)
5220 enum pci_bus_speed next_speed;
5221 enum pcie_link_width next_width;
5225 *speed = PCI_SPEED_UNKNOWN;
5227 *width = PCIE_LNK_WIDTH_UNKNOWN;
5232 pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
5234 next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS];
5235 next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >>
5236 PCI_EXP_LNKSTA_NLW_SHIFT;
5238 next_bw = next_width * PCIE_SPEED2MBS_ENC(next_speed);
5240 /* Check if current device limits the total bandwidth */
5241 if (!bw || next_bw <= bw) {
5245 *limiting_dev = dev;
5247 *speed = next_speed;
5249 *width = next_width;
5252 dev = pci_upstream_bridge(dev);
5257 EXPORT_SYMBOL(pcie_bandwidth_available);
5260 * pcie_get_speed_cap - query for the PCI device's link speed capability
5261 * @dev: PCI device to query
5263 * Query the PCI device speed capability. Return the maximum link speed
5264 * supported by the device.
5266 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev)
5268 u32 lnkcap2, lnkcap;
5271 * PCIe r4.0 sec 7.5.3.18 recommends using the Supported Link
5272 * Speeds Vector in Link Capabilities 2 when supported, falling
5273 * back to Max Link Speed in Link Capabilities otherwise.
5275 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &lnkcap2);
5276 if (lnkcap2) { /* PCIe r3.0-compliant */
5277 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB)
5278 return PCIE_SPEED_16_0GT;
5279 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
5280 return PCIE_SPEED_8_0GT;
5281 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
5282 return PCIE_SPEED_5_0GT;
5283 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
5284 return PCIE_SPEED_2_5GT;
5285 return PCI_SPEED_UNKNOWN;
5288 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
5290 if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB)
5291 return PCIE_SPEED_16_0GT;
5292 else if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB)
5293 return PCIE_SPEED_8_0GT;
5294 else if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB)
5295 return PCIE_SPEED_5_0GT;
5296 else if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB)
5297 return PCIE_SPEED_2_5GT;
5300 return PCI_SPEED_UNKNOWN;
5304 * pcie_get_width_cap - query for the PCI device's link width capability
5305 * @dev: PCI device to query
5307 * Query the PCI device width capability. Return the maximum link width
5308 * supported by the device.
5310 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev)
5314 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
5316 return (lnkcap & PCI_EXP_LNKCAP_MLW) >> 4;
5318 return PCIE_LNK_WIDTH_UNKNOWN;
5322 * pcie_bandwidth_capable - calculate a PCI device's link bandwidth capability
5324 * @speed: storage for link speed
5325 * @width: storage for link width
5327 * Calculate a PCI device's link bandwidth by querying for its link speed
5328 * and width, multiplying them, and applying encoding overhead. The result
5329 * is in Mb/s, i.e., megabits/second of raw bandwidth.
5331 u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
5332 enum pcie_link_width *width)
5334 *speed = pcie_get_speed_cap(dev);
5335 *width = pcie_get_width_cap(dev);
5337 if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN)
5340 return *width * PCIE_SPEED2MBS_ENC(*speed);
5344 * pcie_print_link_status - Report the PCI device's link speed and width
5345 * @dev: PCI device to query
5347 * Report the available bandwidth at the device. If this is less than the
5348 * device is capable of, report the device's maximum possible bandwidth and
5349 * the upstream link that limits its performance to less than that.
5351 void pcie_print_link_status(struct pci_dev *dev)
5353 enum pcie_link_width width, width_cap;
5354 enum pci_bus_speed speed, speed_cap;
5355 struct pci_dev *limiting_dev = NULL;
5356 u32 bw_avail, bw_cap;
5358 bw_cap = pcie_bandwidth_capable(dev, &speed_cap, &width_cap);
5359 bw_avail = pcie_bandwidth_available(dev, &limiting_dev, &speed, &width);
5361 if (bw_avail >= bw_cap)
5362 pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth (%s x%d link)\n",
5363 bw_cap / 1000, bw_cap % 1000,
5364 PCIE_SPEED2STR(speed_cap), width_cap);
5366 pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth, limited by %s x%d link at %s (capable of %u.%03u Gb/s with %s x%d link)\n",
5367 bw_avail / 1000, bw_avail % 1000,
5368 PCIE_SPEED2STR(speed), width,
5369 limiting_dev ? pci_name(limiting_dev) : "<unknown>",
5370 bw_cap / 1000, bw_cap % 1000,
5371 PCIE_SPEED2STR(speed_cap), width_cap);
5373 EXPORT_SYMBOL(pcie_print_link_status);
5376 * pci_select_bars - Make BAR mask from the type of resource
5377 * @dev: the PCI device for which BAR mask is made
5378 * @flags: resource type mask to be selected
5380 * This helper routine makes bar mask from the type of resource.
5382 int pci_select_bars(struct pci_dev *dev, unsigned long flags)
5385 for (i = 0; i < PCI_NUM_RESOURCES; i++)
5386 if (pci_resource_flags(dev, i) & flags)
5390 EXPORT_SYMBOL(pci_select_bars);
5392 /* Some architectures require additional programming to enable VGA */
5393 static arch_set_vga_state_t arch_set_vga_state;
5395 void __init pci_register_set_vga_state(arch_set_vga_state_t func)
5397 arch_set_vga_state = func; /* NULL disables */
5400 static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
5401 unsigned int command_bits, u32 flags)
5403 if (arch_set_vga_state)
5404 return arch_set_vga_state(dev, decode, command_bits,
5410 * pci_set_vga_state - set VGA decode state on device and parents if requested
5411 * @dev: the PCI device
5412 * @decode: true = enable decoding, false = disable decoding
5413 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
5414 * @flags: traverse ancestors and change bridges
5415 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
5417 int pci_set_vga_state(struct pci_dev *dev, bool decode,
5418 unsigned int command_bits, u32 flags)
5420 struct pci_bus *bus;
5421 struct pci_dev *bridge;
5425 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) && (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
5427 /* ARCH specific VGA enables */
5428 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
5432 if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
5433 pci_read_config_word(dev, PCI_COMMAND, &cmd);
5435 cmd |= command_bits;
5437 cmd &= ~command_bits;
5438 pci_write_config_word(dev, PCI_COMMAND, cmd);
5441 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
5448 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
5451 cmd |= PCI_BRIDGE_CTL_VGA;
5453 cmd &= ~PCI_BRIDGE_CTL_VGA;
5454 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
5463 * pci_add_dma_alias - Add a DMA devfn alias for a device
5464 * @dev: the PCI device for which alias is added
5465 * @devfn: alias slot and function
5467 * This helper encodes 8-bit devfn as bit number in dma_alias_mask.
5468 * It should be called early, preferably as PCI fixup header quirk.
5470 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn)
5472 if (!dev->dma_alias_mask)
5473 dev->dma_alias_mask = kcalloc(BITS_TO_LONGS(U8_MAX),
5474 sizeof(long), GFP_KERNEL);
5475 if (!dev->dma_alias_mask) {
5476 pci_warn(dev, "Unable to allocate DMA alias mask\n");
5480 set_bit(devfn, dev->dma_alias_mask);
5481 pci_info(dev, "Enabling fixed DMA alias to %02x.%d\n",
5482 PCI_SLOT(devfn), PCI_FUNC(devfn));
5485 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2)
5487 return (dev1->dma_alias_mask &&
5488 test_bit(dev2->devfn, dev1->dma_alias_mask)) ||
5489 (dev2->dma_alias_mask &&
5490 test_bit(dev1->devfn, dev2->dma_alias_mask));
5493 bool pci_device_is_present(struct pci_dev *pdev)
5497 if (pci_dev_is_disconnected(pdev))
5499 return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0);
5501 EXPORT_SYMBOL_GPL(pci_device_is_present);
5503 void pci_ignore_hotplug(struct pci_dev *dev)
5505 struct pci_dev *bridge = dev->bus->self;
5507 dev->ignore_hotplug = 1;
5508 /* Propagate the "ignore hotplug" setting to the parent bridge. */
5510 bridge->ignore_hotplug = 1;
5512 EXPORT_SYMBOL_GPL(pci_ignore_hotplug);
5514 resource_size_t __weak pcibios_default_alignment(void)
5519 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
5520 static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
5521 static DEFINE_SPINLOCK(resource_alignment_lock);
5524 * pci_specified_resource_alignment - get resource alignment specified by user.
5525 * @dev: the PCI device to get
5526 * @resize: whether or not to change resources' size when reassigning alignment
5528 * RETURNS: Resource alignment if it is specified.
5529 * Zero if it is not specified.
5531 static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev,
5534 int seg, bus, slot, func, align_order, count;
5535 unsigned short vendor, device, subsystem_vendor, subsystem_device;
5536 resource_size_t align = pcibios_default_alignment();
5539 spin_lock(&resource_alignment_lock);
5540 p = resource_alignment_param;
5543 if (pci_has_flag(PCI_PROBE_ONLY)) {
5545 pr_info_once("PCI: Ignoring requested alignments (PCI_PROBE_ONLY)\n");
5551 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
5557 if (strncmp(p, "pci:", 4) == 0) {
5558 /* PCI vendor/device (subvendor/subdevice) ids are specified */
5560 if (sscanf(p, "%hx:%hx:%hx:%hx%n",
5561 &vendor, &device, &subsystem_vendor, &subsystem_device, &count) != 4) {
5562 if (sscanf(p, "%hx:%hx%n", &vendor, &device, &count) != 2) {
5563 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: pci:%s\n",
5567 subsystem_vendor = subsystem_device = 0;
5570 if ((!vendor || (vendor == dev->vendor)) &&
5571 (!device || (device == dev->device)) &&
5572 (!subsystem_vendor || (subsystem_vendor == dev->subsystem_vendor)) &&
5573 (!subsystem_device || (subsystem_device == dev->subsystem_device))) {
5575 if (align_order == -1)
5578 align = 1 << align_order;
5584 if (sscanf(p, "%x:%x:%x.%x%n",
5585 &seg, &bus, &slot, &func, &count) != 4) {
5587 if (sscanf(p, "%x:%x.%x%n",
5588 &bus, &slot, &func, &count) != 3) {
5589 /* Invalid format */
5590 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n",
5596 if (seg == pci_domain_nr(dev->bus) &&
5597 bus == dev->bus->number &&
5598 slot == PCI_SLOT(dev->devfn) &&
5599 func == PCI_FUNC(dev->devfn)) {
5601 if (align_order == -1)
5604 align = 1 << align_order;
5609 if (*p != ';' && *p != ',') {
5610 /* End of param or invalid format */
5616 spin_unlock(&resource_alignment_lock);
5620 static void pci_request_resource_alignment(struct pci_dev *dev, int bar,
5621 resource_size_t align, bool resize)
5623 struct resource *r = &dev->resource[bar];
5624 resource_size_t size;
5626 if (!(r->flags & IORESOURCE_MEM))
5629 if (r->flags & IORESOURCE_PCI_FIXED) {
5630 pci_info(dev, "BAR%d %pR: ignoring requested alignment %#llx\n",
5631 bar, r, (unsigned long long)align);
5635 size = resource_size(r);
5640 * Increase the alignment of the resource. There are two ways we
5643 * 1) Increase the size of the resource. BARs are aligned on their
5644 * size, so when we reallocate space for this resource, we'll
5645 * allocate it with the larger alignment. This also prevents
5646 * assignment of any other BARs inside the alignment region, so
5647 * if we're requesting page alignment, this means no other BARs
5648 * will share the page.
5650 * The disadvantage is that this makes the resource larger than
5651 * the hardware BAR, which may break drivers that compute things
5652 * based on the resource size, e.g., to find registers at a
5653 * fixed offset before the end of the BAR.
5655 * 2) Retain the resource size, but use IORESOURCE_STARTALIGN and
5656 * set r->start to the desired alignment. By itself this
5657 * doesn't prevent other BARs being put inside the alignment
5658 * region, but if we realign *every* resource of every device in
5659 * the system, none of them will share an alignment region.
5661 * When the user has requested alignment for only some devices via
5662 * the "pci=resource_alignment" argument, "resize" is true and we
5663 * use the first method. Otherwise we assume we're aligning all
5664 * devices and we use the second.
5667 pci_info(dev, "BAR%d %pR: requesting alignment to %#llx\n",
5668 bar, r, (unsigned long long)align);
5674 r->flags &= ~IORESOURCE_SIZEALIGN;
5675 r->flags |= IORESOURCE_STARTALIGN;
5677 r->end = r->start + size - 1;
5679 r->flags |= IORESOURCE_UNSET;
5683 * This function disables memory decoding and releases memory resources
5684 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
5685 * It also rounds up size to specified alignment.
5686 * Later on, the kernel will assign page-aligned memory resource back
5689 void pci_reassigndev_resource_alignment(struct pci_dev *dev)
5693 resource_size_t align;
5695 bool resize = false;
5698 * VF BARs are read-only zero according to SR-IOV spec r1.1, sec
5699 * 3.4.1.11. Their resources are allocated from the space
5700 * described by the VF BARx register in the PF's SR-IOV capability.
5701 * We can't influence their alignment here.
5706 /* check if specified PCI is target device to reassign */
5707 align = pci_specified_resource_alignment(dev, &resize);
5711 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
5712 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
5713 pci_warn(dev, "Can't reassign resources to host bridge\n");
5717 pci_read_config_word(dev, PCI_COMMAND, &command);
5718 command &= ~PCI_COMMAND_MEMORY;
5719 pci_write_config_word(dev, PCI_COMMAND, command);
5721 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
5722 pci_request_resource_alignment(dev, i, align, resize);
5725 * Need to disable bridge's resource window,
5726 * to enable the kernel to reassign new resource
5729 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
5730 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
5731 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
5732 r = &dev->resource[i];
5733 if (!(r->flags & IORESOURCE_MEM))
5735 r->flags |= IORESOURCE_UNSET;
5736 r->end = resource_size(r) - 1;
5739 pci_disable_bridge_window(dev);
5743 static ssize_t pci_set_resource_alignment_param(const char *buf, size_t count)
5745 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1)
5746 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1;
5747 spin_lock(&resource_alignment_lock);
5748 strncpy(resource_alignment_param, buf, count);
5749 resource_alignment_param[count] = '\0';
5750 spin_unlock(&resource_alignment_lock);
5754 static ssize_t pci_get_resource_alignment_param(char *buf, size_t size)
5757 spin_lock(&resource_alignment_lock);
5758 count = snprintf(buf, size, "%s", resource_alignment_param);
5759 spin_unlock(&resource_alignment_lock);
5763 static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf)
5765 return pci_get_resource_alignment_param(buf, PAGE_SIZE);
5768 static ssize_t pci_resource_alignment_store(struct bus_type *bus,
5769 const char *buf, size_t count)
5771 return pci_set_resource_alignment_param(buf, count);
5774 static BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show,
5775 pci_resource_alignment_store);
5777 static int __init pci_resource_alignment_sysfs_init(void)
5779 return bus_create_file(&pci_bus_type,
5780 &bus_attr_resource_alignment);
5782 late_initcall(pci_resource_alignment_sysfs_init);
5784 static void pci_no_domains(void)
5786 #ifdef CONFIG_PCI_DOMAINS
5787 pci_domains_supported = 0;
5791 #ifdef CONFIG_PCI_DOMAINS_GENERIC
5792 static atomic_t __domain_nr = ATOMIC_INIT(-1);
5794 static int pci_get_new_domain_nr(void)
5796 return atomic_inc_return(&__domain_nr);
5799 static int of_pci_bus_find_domain_nr(struct device *parent)
5801 static int use_dt_domains = -1;
5805 domain = of_get_pci_domain_nr(parent->of_node);
5807 * Check DT domain and use_dt_domains values.
5809 * If DT domain property is valid (domain >= 0) and
5810 * use_dt_domains != 0, the DT assignment is valid since this means
5811 * we have not previously allocated a domain number by using
5812 * pci_get_new_domain_nr(); we should also update use_dt_domains to
5813 * 1, to indicate that we have just assigned a domain number from
5816 * If DT domain property value is not valid (ie domain < 0), and we
5817 * have not previously assigned a domain number from DT
5818 * (use_dt_domains != 1) we should assign a domain number by
5821 * pci_get_new_domain_nr()
5823 * API and update the use_dt_domains value to keep track of method we
5824 * are using to assign domain numbers (use_dt_domains = 0).
5826 * All other combinations imply we have a platform that is trying
5827 * to mix domain numbers obtained from DT and pci_get_new_domain_nr(),
5828 * which is a recipe for domain mishandling and it is prevented by
5829 * invalidating the domain value (domain = -1) and printing a
5830 * corresponding error.
5832 if (domain >= 0 && use_dt_domains) {
5834 } else if (domain < 0 && use_dt_domains != 1) {
5836 domain = pci_get_new_domain_nr();
5839 pr_err("Node %pOF has ", parent->of_node);
5840 pr_err("Inconsistent \"linux,pci-domain\" property in DT\n");
5847 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent)
5849 return acpi_disabled ? of_pci_bus_find_domain_nr(parent) :
5850 acpi_pci_bus_find_domain_nr(bus);
5855 * pci_ext_cfg_avail - can we access extended PCI config space?
5857 * Returns 1 if we can access PCI extended config space (offsets
5858 * greater than 0xff). This is the default implementation. Architecture
5859 * implementations can override this.
5861 int __weak pci_ext_cfg_avail(void)
5866 void __weak pci_fixup_cardbus(struct pci_bus *bus)
5869 EXPORT_SYMBOL(pci_fixup_cardbus);
5871 static int __init pci_setup(char *str)
5874 char *k = strchr(str, ',');
5877 if (*str && (str = pcibios_setup(str)) && *str) {
5878 if (!strcmp(str, "nomsi")) {
5880 } else if (!strncmp(str, "noats", 5)) {
5881 pr_info("PCIe: ATS is disabled\n");
5882 pcie_ats_disabled = true;
5883 } else if (!strcmp(str, "noaer")) {
5885 } else if (!strncmp(str, "realloc=", 8)) {
5886 pci_realloc_get_opt(str + 8);
5887 } else if (!strncmp(str, "realloc", 7)) {
5888 pci_realloc_get_opt("on");
5889 } else if (!strcmp(str, "nodomains")) {
5891 } else if (!strncmp(str, "noari", 5)) {
5892 pcie_ari_disabled = true;
5893 } else if (!strncmp(str, "cbiosize=", 9)) {
5894 pci_cardbus_io_size = memparse(str + 9, &str);
5895 } else if (!strncmp(str, "cbmemsize=", 10)) {
5896 pci_cardbus_mem_size = memparse(str + 10, &str);
5897 } else if (!strncmp(str, "resource_alignment=", 19)) {
5898 pci_set_resource_alignment_param(str + 19,
5900 } else if (!strncmp(str, "ecrc=", 5)) {
5901 pcie_ecrc_get_policy(str + 5);
5902 } else if (!strncmp(str, "hpiosize=", 9)) {
5903 pci_hotplug_io_size = memparse(str + 9, &str);
5904 } else if (!strncmp(str, "hpmemsize=", 10)) {
5905 pci_hotplug_mem_size = memparse(str + 10, &str);
5906 } else if (!strncmp(str, "hpbussize=", 10)) {
5907 pci_hotplug_bus_size =
5908 simple_strtoul(str + 10, &str, 0);
5909 if (pci_hotplug_bus_size > 0xff)
5910 pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE;
5911 } else if (!strncmp(str, "pcie_bus_tune_off", 17)) {
5912 pcie_bus_config = PCIE_BUS_TUNE_OFF;
5913 } else if (!strncmp(str, "pcie_bus_safe", 13)) {
5914 pcie_bus_config = PCIE_BUS_SAFE;
5915 } else if (!strncmp(str, "pcie_bus_perf", 13)) {
5916 pcie_bus_config = PCIE_BUS_PERFORMANCE;
5917 } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) {
5918 pcie_bus_config = PCIE_BUS_PEER2PEER;
5919 } else if (!strncmp(str, "pcie_scan_all", 13)) {
5920 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
5922 printk(KERN_ERR "PCI: Unknown option `%s'\n",
5930 early_param("pci", pci_setup);