drivers/staging/rtl8723bs/core/rtw_odm.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2013 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  ******************************************************************************/
  15
  16 #include <drv_types.h>
  17 #include <rtw_debug.h>
  18 #include <rtw_odm.h>
  19 #include <hal_data.h>
  20
  21 static const char *odm_comp_str[] = {
  22         /* BIT0 */"ODM_COMP_DIG",
  23         /* BIT1 */"ODM_COMP_RA_MASK",
  24         /* BIT2 */"ODM_COMP_DYNAMIC_TXPWR",
  25         /* BIT3 */"ODM_COMP_FA_CNT",
  26         /* BIT4 */"ODM_COMP_RSSI_MONITOR",
  27         /* BIT5 */"ODM_COMP_CCK_PD",
  28         /* BIT6 */"ODM_COMP_ANT_DIV",
  29         /* BIT7 */"ODM_COMP_PWR_SAVE",
  30         /* BIT8 */"ODM_COMP_PWR_TRAIN",
  31         /* BIT9 */"ODM_COMP_RATE_ADAPTIVE",
  32         /* BIT10 */"ODM_COMP_PATH_DIV",
  33         /* BIT11 */"ODM_COMP_PSD",
  34         /* BIT12 */"ODM_COMP_DYNAMIC_PRICCA",
  35         /* BIT13 */"ODM_COMP_RXHP",
  36         /* BIT14 */"ODM_COMP_MP",
  37         /* BIT15 */"ODM_COMP_DYNAMIC_ATC",
  38         /* BIT16 */"ODM_COMP_EDCA_TURBO",
  39         /* BIT17 */"ODM_COMP_EARLY_MODE",
  40         /* BIT18 */NULL,
  41         /* BIT19 */NULL,
  42         /* BIT20 */NULL,
  43         /* BIT21 */NULL,
  44         /* BIT22 */NULL,
  45         /* BIT23 */NULL,
  46         /* BIT24 */"ODM_COMP_TX_PWR_TRACK",
  47         /* BIT25 */"ODM_COMP_RX_GAIN_TRACK",
  48         /* BIT26 */"ODM_COMP_CALIBRATION",
  49         /* BIT27 */NULL,
  50         /* BIT28 */NULL,
  51         /* BIT29 */NULL,
  52         /* BIT30 */"ODM_COMP_COMMON",
  53         /* BIT31 */"ODM_COMP_INIT",
  54 };
  55
  56 #define RTW_ODM_COMP_MAX 32
  57
  58 static const char *odm_ability_str[] = {
  59         /* BIT0 */"ODM_BB_DIG",
  60         /* BIT1 */"ODM_BB_RA_MASK",
  61         /* BIT2 */"ODM_BB_DYNAMIC_TXPWR",
  62         /* BIT3 */"ODM_BB_FA_CNT",
  63         /* BIT4 */"ODM_BB_RSSI_MONITOR",
  64         /* BIT5 */"ODM_BB_CCK_PD",
  65         /* BIT6 */"ODM_BB_ANT_DIV",
  66         /* BIT7 */"ODM_BB_PWR_SAVE",
  67         /* BIT8 */"ODM_BB_PWR_TRAIN",
  68         /* BIT9 */"ODM_BB_RATE_ADAPTIVE",
  69         /* BIT10 */"ODM_BB_PATH_DIV",
  70         /* BIT11 */"ODM_BB_PSD",
  71         /* BIT12 */"ODM_BB_RXHP",
  72         /* BIT13 */"ODM_BB_ADAPTIVITY",
  73         /* BIT14 */"ODM_BB_DYNAMIC_ATC",
  74         /* BIT15 */NULL,
  75         /* BIT16 */"ODM_MAC_EDCA_TURBO",
  76         /* BIT17 */"ODM_MAC_EARLY_MODE",
  77         /* BIT18 */NULL,
  78         /* BIT19 */NULL,
  79         /* BIT20 */NULL,
  80         /* BIT21 */NULL,
  81         /* BIT22 */NULL,
  82         /* BIT23 */NULL,
  83         /* BIT24 */"ODM_RF_TX_PWR_TRACK",
  84         /* BIT25 */"ODM_RF_RX_GAIN_TRACK",
  85         /* BIT26 */"ODM_RF_CALIBRATION",
  86 };
  87
  88 #define RTW_ODM_ABILITY_MAX 27
  89
  90 static const char *odm_dbg_level_str[] = {
  91         NULL,
  92         "ODM_DBG_OFF",
  93         "ODM_DBG_SERIOUS",
  94         "ODM_DBG_WARNING",
  95         "ODM_DBG_LOUD",
  96         "ODM_DBG_TRACE",
  97 };
  98
  99 #define RTW_ODM_DBG_LEVEL_NUM 6
 100
 101 void rtw_odm_dbg_comp_msg(void *sel, struct adapter *adapter)
 102 {
 103         u64 dbg_comp;
 104         int i;
 105
 106         rtw_hal_get_def_var(adapter, HW_DEF_ODM_DBG_FLAG, &dbg_comp);
 107         DBG_871X_SEL_NL(sel, "odm.DebugComponents = 0x%016llx\n", dbg_comp);
 108         for (i = 0;i<RTW_ODM_COMP_MAX;i++) {
 109                 if (odm_comp_str[i])
 110                 DBG_871X_SEL_NL(sel, "%cBIT%-2d %s\n",
 111                         (BIT0 << i) & dbg_comp ? '+' : ' ', i, odm_comp_str[i]);
 112         }
 113 }
 114
 115 inline void rtw_odm_dbg_comp_set(struct adapter *adapter, u64 comps)
 116 {
 117         rtw_hal_set_def_var(adapter, HW_DEF_ODM_DBG_FLAG, &comps);
 118 }
 119
 120 void rtw_odm_dbg_level_msg(void *sel, struct adapter *adapter)
 121 {
 122         u32 dbg_level;
 123         int i;
 124
 125         rtw_hal_get_def_var(adapter, HW_DEF_ODM_DBG_LEVEL, &dbg_level);
 126         DBG_871X_SEL_NL(sel, "odm.DebugLevel = %u\n", dbg_level);
 127         for (i = 0;i<RTW_ODM_DBG_LEVEL_NUM;i++) {
 128                 if (odm_dbg_level_str[i])
 129                         DBG_871X_SEL_NL(sel, "%u %s\n", i, odm_dbg_level_str[i]);
 130         }
 131 }
 132
 133 inline void rtw_odm_dbg_level_set(struct adapter *adapter, u32 level)
 134 {
 135         rtw_hal_set_def_var(adapter, HW_DEF_ODM_DBG_LEVEL, &level);
 136 }
 137
 138 void rtw_odm_ability_msg(void *sel, struct adapter *adapter)
 139 {
 140         u32 ability = 0;
 141         int i;
 142
 143         rtw_hal_get_hwreg(adapter, HW_VAR_DM_FLAG, (u8 *)&ability);
 144         DBG_871X_SEL_NL(sel, "odm.SupportAbility = 0x%08x\n", ability);
 145         for (i = 0;i<RTW_ODM_ABILITY_MAX;i++) {
 146                 if (odm_ability_str[i])
 147                 DBG_871X_SEL_NL(sel, "%cBIT%-2d %s\n",
 148                         (BIT0 << i) & ability ? '+' : ' ', i, odm_ability_str[i]);
 149         }
 150 }
 151
 152 inline void rtw_odm_ability_set(struct adapter *adapter, u32 ability)
 153 {
 154         rtw_hal_set_hwreg(adapter, HW_VAR_DM_FLAG, (u8 *)&ability);
 155 }
 156
 157 void rtw_odm_adaptivity_parm_msg(void *sel, struct adapter *adapter)
 158 {
 159         struct hal_com_data *pHalData = GET_HAL_DATA(adapter);
 160         DM_ODM_T *odm = &pHalData->odmpriv;
 161
 162         DBG_871X_SEL_NL(sel, "%10s %16s %8s %10s %11s %14s\n"
 163                 , "TH_L2H_ini", "TH_EDCCA_HL_diff", "IGI_Base", "ForceEDCCA", "AdapEn_RSSI", "IGI_LowerBound");
 164         DBG_871X_SEL_NL(sel, "0x%-8x %-16d 0x%-6x %-10d %-11u %-14u\n"
 165                 , (u8)odm->TH_L2H_ini
 166                 , odm->TH_EDCCA_HL_diff
 167                 , odm->IGI_Base
 168                 , odm->ForceEDCCA
 169                 , odm->AdapEn_RSSI
 170                 , odm->IGI_LowerBound
 171         );
 172 }
 173
 174 void rtw_odm_adaptivity_parm_set(struct adapter *adapter, s8 TH_L2H_ini, s8 TH_EDCCA_HL_diff,
 175         s8 IGI_Base, bool ForceEDCCA, u8 AdapEn_RSSI, u8 IGI_LowerBound)
 176 {
 177         struct hal_com_data *pHalData = GET_HAL_DATA(adapter);
 178         DM_ODM_T *odm = &pHalData->odmpriv;
 179
 180         odm->TH_L2H_ini = TH_L2H_ini;
 181         odm->TH_EDCCA_HL_diff = TH_EDCCA_HL_diff;
 182         odm->IGI_Base = IGI_Base;
 183         odm->ForceEDCCA = ForceEDCCA;
 184         odm->AdapEn_RSSI = AdapEn_RSSI;
 185         odm->IGI_LowerBound = IGI_LowerBound;
 186 }
 187
 188 void rtw_odm_get_perpkt_rssi(void *sel, struct adapter *adapter)
 189 {
 190         struct hal_com_data *hal_data = GET_HAL_DATA(adapter);
 191         DM_ODM_T *odm = &(hal_data->odmpriv);
 192
 193         DBG_871X_SEL_NL(sel,"RxRate = %s, RSSI_A = %d(%%), RSSI_B = %d(%%)\n",
 194         HDATA_RATE(odm->RxRate), odm->RSSI_A, odm->RSSI_B);
 195 }