drivers/staging/rtl8723bs/hal/odm_HWConfig.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  ******************************************************************************/
  15
  16
  17 #ifndef __HALHWOUTSRC_H__
  18 #define __HALHWOUTSRC_H__
  19
  20
  21 /*--------------------------Define -------------------------------------------*/
  22 /* define READ_NEXT_PAIR(v1, v2, i) do { i += 2; v1 = Array[i]; v2 = Array[i+1]; } while (0) */
  23 #define AGC_DIFF_CONFIG_MP(ic, band) (ODM_ReadAndConfig_MP_##ic##_AGC_TAB_DIFF(pDM_Odm, Array_MP_##ic##_AGC_TAB_DIFF_##band, \
  24                                                                               sizeof(Array_MP_##ic##_AGC_TAB_DIFF_##band)/sizeof(u32)))
  25 #define AGC_DIFF_CONFIG_TC(ic, band) (ODM_ReadAndConfig_TC_##ic##_AGC_TAB_DIFF(pDM_Odm, Array_TC_##ic##_AGC_TAB_DIFF_##band, \
  26                                                                               sizeof(Array_TC_##ic##_AGC_TAB_DIFF_##band)/sizeof(u32)))
  27
  28 #define AGC_DIFF_CONFIG(ic, band) do {\
  29                                             if (pDM_Odm->bIsMPChip)\
  30                                                     AGC_DIFF_CONFIG_MP(ic, band);\
  31                                             else\
  32                                                 AGC_DIFF_CONFIG_TC(ic, band);\
  33                                     } while (0)
  34
  35
  36 /*  */
  37 /*  structure and define */
  38 /*  */
  39
  40 typedef struct _Phy_Rx_AGC_Info
  41 {
  42         #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
  43                 u8 gain:7, trsw:1;
  44         #else
  45                 u8 trsw:1, gain:7;
  46         #endif
  47 } PHY_RX_AGC_INFO_T,*pPHY_RX_AGC_INFO_T;
  48
  49 typedef struct _Phy_Status_Rpt_8192cd
  50 {
  51         PHY_RX_AGC_INFO_T path_agc[2];
  52         u8 ch_corr[2];
  53         u8 cck_sig_qual_ofdm_pwdb_all;
  54         u8 cck_agc_rpt_ofdm_cfosho_a;
  55         u8 cck_rpt_b_ofdm_cfosho_b;
  56         u8 rsvd_1;/* ch_corr_msb; */
  57         u8 noise_power_db_msb;
  58         s8      path_cfotail[2];
  59         u8 pcts_mask[2];
  60         s8      stream_rxevm[2];
  61         u8 path_rxsnr[2];
  62         u8 noise_power_db_lsb;
  63         u8 rsvd_2[3];
  64         u8 stream_csi[2];
  65         u8 stream_target_csi[2];
  66         s8      sig_evm;
  67         u8 rsvd_3;
  68
  69 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
  70         u8 antsel_rx_keep_2:1;  /* ex_intf_flg:1; */
  71         u8 sgi_en:1;
  72         u8 rxsc:2;
  73         u8 idle_long:1;
  74         u8 r_ant_train_en:1;
  75         u8 ant_sel_b:1;
  76         u8 ant_sel:1;
  77 #else   /*  _BIG_ENDIAN_ */
  78         u8 ant_sel:1;
  79         u8 ant_sel_b:1;
  80         u8 r_ant_train_en:1;
  81         u8 idle_long:1;
  82         u8 rxsc:2;
  83         u8 sgi_en:1;
  84         u8 antsel_rx_keep_2:1;  /* ex_intf_flg:1; */
  85 #endif
  86 } PHY_STATUS_RPT_8192CD_T,*PPHY_STATUS_RPT_8192CD_T;
  87
  88
  89 typedef struct _Phy_Status_Rpt_8812
  90 {
  91         /* 2012.05.24 LukeLee: This structure should take big/little endian in consideration later..... */
  92
  93         /* DWORD 0 */
  94         u8      gain_trsw[2];
  95 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
  96         u16             chl_num:10;
  97         u16             sub_chnl:4;
  98         u16             r_RFMOD:2;
  99 #else   /*  _BIG_ENDIAN_ */
 100         u16             r_RFMOD:2;
 101         u16             sub_chnl:4;
 102         u16             chl_num:10;
 103 #endif
 104
 105         /* DWORD 1 */
 106         u8      pwdb_all;
 107         u8      cfosho[4];      /*  DW 1 byte 1 DW 2 byte 0 */
 108
 109         /* DWORD 2 */
 110         s8                      cfotail[4];     /*  DW 2 byte 1 DW 3 byte 0 */
 111
 112         /* DWORD 3 */
 113         s8                      rxevm[2];       /*  DW 3 byte 1 DW 3 byte 2 */
 114         s8                      rxsnr[2];       /*  DW 3 byte 3 DW 4 byte 0 */
 115
 116         /* DWORD 4 */
 117         u8      PCTS_MSK_RPT[2];
 118         u8      pdsnr[2];       /*  DW 4 byte 3 DW 5 Byte 0 */
 119
 120         /* DWORD 5 */
 121         u8      csi_current[2];
 122         u8      rx_gain_c;
 123
 124         /* DWORD 6 */
 125         u8      rx_gain_d;
 126         s8                      sigevm;
 127         u8      resvd_0;
 128         u8      antidx_anta:3;
 129         u8      antidx_antb:3;
 130         u8      resvd_1:2;
 131 } PHY_STATUS_RPT_8812_T,*PPHY_STATUS_RPT_8812_T;
 132
 133
 134 void
 135 ODM_PhyStatusQuery(
 136         PDM_ODM_T                                       pDM_Odm,
 137         PODM_PHY_INFO_T                 pPhyInfo,
 138         u8 *                                    pPhyStatus,
 139         PODM_PACKET_INFO_T                      pPktinfo
 140         );
 141
 142 HAL_STATUS
 143 ODM_ConfigRFWithTxPwrTrackHeaderFile(
 144 PDM_ODM_T                       pDM_Odm
 145    );
 146
 147 HAL_STATUS
 148 ODM_ConfigRFWithHeaderFile(
 149 PDM_ODM_T                       pDM_Odm,
 150 ODM_RF_Config_Type              ConfigType,
 151 ODM_RF_RADIO_PATH_E     eRFPath
 152         );
 153
 154 HAL_STATUS
 155 ODM_ConfigBBWithHeaderFile(
 156 PDM_ODM_T                       pDM_Odm,
 157 ODM_BB_Config_Type              ConfigType
 158    );
 159
 160 HAL_STATUS
 161 ODM_ConfigMACWithHeaderFile(
 162 PDM_ODM_T       pDM_Odm
 163    );
 164
 165 HAL_STATUS
 166 ODM_ConfigFWWithHeaderFile(
 167 PDM_ODM_T                       pDM_Odm,
 168 ODM_FW_Config_Type      ConfigType,
 169         u8              *pFirmware,
 170         u32                     *pSize
 171         );
 172
 173 s32
 174 odm_SignalScaleMapping(
 175         PDM_ODM_T pDM_Odm,
 176 s32 CurrSig
 177         );
 178
 179 #endif