drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  ******************************************************************************/
  15 #define _RTL8723B_PHYCFG_C_
  16
  17 #include <drv_types.h>
  18 #include <rtw_debug.h>
  19 #include <rtl8723b_hal.h>
  20
  21
  22 /*---------------------------Define Local Constant---------------------------*/
  23 /* Channel switch:The size of command tables for switch channel*/
  24 #define MAX_PRECMD_CNT 16
  25 #define MAX_RFDEPENDCMD_CNT 16
  26 #define MAX_POSTCMD_CNT 16
  27
  28 #define MAX_DOZE_WAITING_TIMES_9x 64
  29
  30 /**
  31 * Function:     phy_CalculateBitShift
  32 *
  33 * OverView:     Get shifted position of the BitMask
  34 *
  35 * Input:
  36 *               u32     BitMask,
  37 *
  38 * Output:       none
  39 * Return:               u32     Return the shift bit bit position of the mask
  40 */
  41 static  u32 phy_CalculateBitShift(u32 BitMask)
  42 {
  43         u32 i;
  44
  45         for (i = 0; i <=31; i++) {
  46                 if (((BitMask>>i) &  0x1) == 1)
  47                         break;
  48         }
  49         return i;
  50 }
  51
  52
  53 /**
  54 * Function:     PHY_QueryBBReg
  55 *
  56 * OverView:     Read "sepcific bits" from BB register
  57 *
  58 * Input:
  59 *               struct adapter *        Adapter,
  60 *               u32             RegAddr,        The target address to be readback
  61 *               u32             BitMask         The target bit position in the target address
  62 *                                                       to be readback
  63 * Output:       None
  64 * Return:               u32             Data            The readback register value
  65 * Note:         This function is equal to "GetRegSetting" in PHY programming guide
  66 */
  67 u32
  68 PHY_QueryBBReg_8723B(
  69 struct adapter *Adapter,
  70 u32     RegAddr,
  71 u32     BitMask
  72         )
  73 {
  74         u32 ReturnValue = 0, OriginalValue, BitShift;
  75
  76 #if (DISABLE_BB_RF == 1)
  77         return 0;
  78 #endif
  79
  80         /* RT_TRACE(COMP_RF, DBG_TRACE, ("--->PHY_QueryBBReg(): RegAddr(%#lx), BitMask(%#lx)\n", RegAddr, BitMask)); */
  81
  82         OriginalValue = rtw_read32(Adapter, RegAddr);
  83         BitShift = phy_CalculateBitShift(BitMask);
  84         ReturnValue = (OriginalValue & BitMask) >> BitShift;
  85
  86         return (ReturnValue);
  87
  88 }
  89
  90
  91 /**
  92 * Function:     PHY_SetBBReg
  93 *
  94 * OverView:     Write "Specific bits" to BB register (page 8~)
  95 *
  96 * Input:
  97 *               struct adapter *        Adapter,
  98 *               u32             RegAddr,        The target address to be modified
  99 *               u32             BitMask         The target bit position in the target address
 100 *                                                               to be modified
 101 *               u32             Data            The new register value in the target bit position
 102 *                                                               of the target address
 103 *
 104 * Output:       None
 105 * Return:               None
 106 * Note:         This function is equal to "PutRegSetting" in PHY programming guide
 107 */
 108
 109 void
 110 PHY_SetBBReg_8723B(
 111 struct adapter *Adapter,
 112 u32     RegAddr,
 113 u32     BitMask,
 114 u32     Data
 115         )
 116 {
 117         /* u16          BBWaitCounter   = 0; */
 118         u32             OriginalValue, BitShift;
 119
 120 #if (DISABLE_BB_RF == 1)
 121         return;
 122 #endif
 123
 124         /* RT_TRACE(COMP_RF, DBG_TRACE, ("--->PHY_SetBBReg(): RegAddr(%#lx), BitMask(%#lx), Data(%#lx)\n", RegAddr, BitMask, Data)); */
 125
 126         if (BitMask!= bMaskDWord) {/* if not "double word" write */
 127                 OriginalValue = rtw_read32(Adapter, RegAddr);
 128                 BitShift = phy_CalculateBitShift(BitMask);
 129                 Data = ((OriginalValue & (~BitMask)) | ((Data << BitShift) & BitMask));
 130         }
 131
 132         rtw_write32(Adapter, RegAddr, Data);
 133
 134 }
 135
 136
 137 /*  */
 138 /*  2. RF register R/W API */
 139 /*  */
 140
 141 static  u32
 142 phy_RFSerialRead_8723B(
 143 struct adapter *                Adapter,
 144 enum RF_PATH                    eRFPath,
 145 u32                     Offset
 146         )
 147 {
 148         u32 retValue = 0;
 149         struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
 150         struct bb_register_def *pPhyReg = &pHalData->PHYRegDef[eRFPath];
 151         u32                                     NewOffset;
 152         u32 tmplong2;
 153         u8                      RfPiEnable = 0;
 154         u32                                     MaskforPhySet = 0;
 155         int i = 0;
 156
 157         /*  */
 158         /*  Make sure RF register offset is correct */
 159         /*  */
 160         Offset &= 0xff;
 161
 162         NewOffset = Offset;
 163
 164         if (eRFPath == RF_PATH_A)
 165         {
 166                 tmplong2 = PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord);;
 167                 tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset<<23) | bLSSIReadEdge;  /* T65 RF */
 168                 PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord, tmplong2&(~bLSSIReadEdge));
 169         }
 170         else
 171         {
 172                 tmplong2 = PHY_QueryBBReg(Adapter, rFPGA0_XB_HSSIParameter2|MaskforPhySet, bMaskDWord);
 173                 tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset<<23) | bLSSIReadEdge;  /* T65 RF */
 174                 PHY_SetBBReg(Adapter, rFPGA0_XB_HSSIParameter2|MaskforPhySet, bMaskDWord, tmplong2&(~bLSSIReadEdge));
 175         }
 176
 177         tmplong2 = PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord);
 178         PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord, tmplong2 & (~bLSSIReadEdge));
 179         PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord, tmplong2 | bLSSIReadEdge);
 180
 181         udelay(10);
 182
 183         for (i = 0;i<2;i++)
 184                 udelay(MAX_STALL_TIME);
 185         udelay(10);
 186
 187         if (eRFPath == RF_PATH_A)
 188                 RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter1|MaskforPhySet, BIT8);
 189         else if (eRFPath == RF_PATH_B)
 190                 RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XB_HSSIParameter1|MaskforPhySet, BIT8);
 191
 192         if (RfPiEnable)
 193         {       /*  Read from BBreg8b8, 12 bits for 8190, 20bits for T65 RF */
 194                 retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBackPi|MaskforPhySet, bLSSIReadBackData);
 195
 196                 /* RT_DISP(FINIT, INIT_RF, ("Readback from RF-PI : 0x%x\n", retValue)); */
 197         }
 198         else
 199         {       /* Read from BBreg8a0, 12 bits for 8190, 20 bits for T65 RF */
 200                 retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBack|MaskforPhySet, bLSSIReadBackData);
 201
 202                 /* RT_DISP(FINIT, INIT_RF, ("Readback from RF-SI : 0x%x\n", retValue)); */
 203         }
 204         return retValue;
 205
 206 }
 207
 208 /**
 209 * Function:     phy_RFSerialWrite_8723B
 210 *
 211 * OverView:     Write data to RF register (page 8~)
 212 *
 213 * Input:
 214 *               struct adapter *        Adapter,
 215 *               RF_PATH                 eRFPath,        Radio path of A/B/C/D
 216 *               u32             Offset,         The target address to be read
 217 *               u32             Data            The new register Data in the target bit position
 218 *                                                               of the target to be read
 219 *
 220 * Output:       None
 221 * Return:               None
 222 * Note:         Threre are three types of serial operations:
 223 *               1. Software serial write
 224 *               2. Hardware LSSI-Low Speed Serial Interface
 225 *               3. Hardware HSSI-High speed
 226 *               serial write. Driver need to implement (1) and (2).
 227 *               This function is equal to the combination of RF_ReadReg() and  RFLSSIRead()
 228  *
 229  * Note:                  For RF8256 only
 230  *               The total count of RTL8256(Zebra4) register is around 36 bit it only employs
 231  *               4-bit RF address. RTL8256 uses "register mode control bit" (Reg00[12], Reg00[10])
 232  *               to access register address bigger than 0xf. See "Appendix-4 in PHY Configuration
 233  *               programming guide" for more details.
 234  *               Thus, we define a sub-finction for RTL8526 register address conversion
 235  *             ===========================================================
 236  *               Register Mode          RegCTL[1]               RegCTL[0]               Note
 237  *                                                      (Reg00[12])             (Reg00[10])
 238  *             ===========================================================
 239  *               Reg_Mode0                              0                               x                       Reg 0 ~15(0x0 ~ 0xf)
 240  *             ------------------------------------------------------------------
 241  *               Reg_Mode1                              1                               0                       Reg 16 ~30(0x1 ~ 0xf)
 242  *             ------------------------------------------------------------------
 243  *               Reg_Mode2                              1                               1                       Reg 31 ~ 45(0x1 ~ 0xf)
 244  *             ------------------------------------------------------------------
 245  *
 246  *2008/09/02    MH      Add 92S RF definition
 247  *
 248  *
 249  *
 250 */
 251 static  void
 252 phy_RFSerialWrite_8723B(
 253 struct adapter *                Adapter,
 254 enum RF_PATH                    eRFPath,
 255 u32                     Offset,
 256 u32                     Data
 257         )
 258 {
 259         u32                                     DataAndAddr = 0;
 260         struct hal_com_data                             *pHalData = GET_HAL_DATA(Adapter);
 261         struct bb_register_def *pPhyReg = &pHalData->PHYRegDef[eRFPath];
 262         u32                                     NewOffset;
 263
 264         Offset &= 0xff;
 265
 266         /*  */
 267         /*  Switch page for 8256 RF IC */
 268         /*  */
 269         NewOffset = Offset;
 270
 271         /*  */
 272         /*  Put write addr in [5:0]  and write data in [31:16] */
 273         /*  */
 274         /* DataAndAddr = (Data<<16) | (NewOffset&0x3f); */
 275         DataAndAddr = ((NewOffset<<20) | (Data&0x000fffff)) & 0x0fffffff;       /*  T65 RF */
 276
 277         /*  */
 278         /*  Write Operation */
 279         /*  */
 280         PHY_SetBBReg(Adapter, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
 281         /* RTPRINT(FPHY, PHY_RFW, ("RFW-%d Addr[0x%lx]= 0x%lx\n", eRFPath, pPhyReg->rf3wireOffset, DataAndAddr)); */
 282
 283 }
 284
 285
 286 /**
 287 * Function:     PHY_QueryRFReg
 288 *
 289 * OverView:     Query "Specific bits" to RF register (page 8~)
 290 *
 291 * Input:
 292 *               struct adapter *        Adapter,
 293 *               RF_PATH                 eRFPath,        Radio path of A/B/C/D
 294 *               u32             RegAddr,        The target address to be read
 295 *               u32             BitMask         The target bit position in the target address
 296 *                                                               to be read
 297 *
 298 * Output:       None
 299 * Return:               u32             Readback value
 300 * Note:         This function is equal to "GetRFRegSetting" in PHY programming guide
 301 */
 302 u32
 303 PHY_QueryRFReg_8723B(
 304 struct adapter *                Adapter,
 305 u8      eRFPath,
 306 u32                     RegAddr,
 307 u32                     BitMask
 308         )
 309 {
 310         u32 Original_Value, Readback_Value, BitShift;
 311
 312 #if (DISABLE_BB_RF == 1)
 313         return 0;
 314 #endif
 315
 316         Original_Value = phy_RFSerialRead_8723B(Adapter, eRFPath, RegAddr);
 317
 318         BitShift =  phy_CalculateBitShift(BitMask);
 319         Readback_Value = (Original_Value & BitMask) >> BitShift;
 320
 321         return (Readback_Value);
 322 }
 323
 324 /**
 325 * Function:     PHY_SetRFReg
 326 *
 327 * OverView:     Write "Specific bits" to RF register (page 8~)
 328 *
 329 * Input:
 330 *               struct adapter *        Adapter,
 331 *               RF_PATH                 eRFPath,        Radio path of A/B/C/D
 332 *               u32             RegAddr,        The target address to be modified
 333 *               u32             BitMask         The target bit position in the target address
 334 *                                                               to be modified
 335 *               u32             Data            The new register Data in the target bit position
 336 *                                                               of the target address
 337 *
 338 * Output:       None
 339 * Return:               None
 340 * Note:         This function is equal to "PutRFRegSetting" in PHY programming guide
 341 */
 342 void
 343 PHY_SetRFReg_8723B(
 344 struct adapter *                Adapter,
 345 u8              eRFPath,
 346 u32                     RegAddr,
 347 u32                     BitMask,
 348 u32                     Data
 349         )
 350 {
 351         u32     Original_Value, BitShift;
 352
 353 #if (DISABLE_BB_RF == 1)
 354         return;
 355 #endif
 356
 357         /*  RF data is 12 bits only */
 358         if (BitMask != bRFRegOffsetMask)
 359         {
 360                 Original_Value = phy_RFSerialRead_8723B(Adapter, eRFPath, RegAddr);
 361                 BitShift =  phy_CalculateBitShift(BitMask);
 362                 Data = ((Original_Value & (~BitMask)) | (Data<< BitShift));
 363         }
 364
 365         phy_RFSerialWrite_8723B(Adapter, eRFPath, RegAddr, Data);
 366 }
 367
 368
 369 /*  */
 370 /*  3. Initial MAC/BB/RF config by reading MAC/BB/RF txt. */
 371 /*  */
 372
 373
 374 /*-----------------------------------------------------------------------------
 375  * Function:    PHY_MACConfig8192C
 376  *
 377  * Overview:    Condig MAC by header file or parameter file.
 378  *
 379  * Input:       NONE
 380  *
 381  * Output:      NONE
 382  *
 383  * Return:      NONE
 384  *
 385  * Revised History:
 386  *  When                Who             Remark
 387  *  08/12/2008  MHC             Create Version 0.
 388  *
 389  *---------------------------------------------------------------------------*/
 390 s32 PHY_MACConfig8723B(struct adapter * Adapter)
 391 {
 392         int             rtStatus = _SUCCESS;
 393         struct hal_com_data     *pHalData = GET_HAL_DATA(Adapter);
 394         s8                      *pszMACRegFile;
 395         s8                      sz8723MACRegFile[] = RTL8723B_PHY_MACREG;
 396
 397
 398         pszMACRegFile = sz8723MACRegFile;
 399
 400         /*  */
 401         /*  Config MAC */
 402         /*  */
 403 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
 404         rtStatus = phy_ConfigMACWithParaFile(Adapter, pszMACRegFile);
 405         if (rtStatus == _FAIL)
 406 #endif
 407         {
 408                 ODM_ConfigMACWithHeaderFile(&pHalData->odmpriv);
 409                 rtStatus = _SUCCESS;
 410         }
 411
 412         return rtStatus;
 413 }
 414
 415 /**
 416 * Function:     phy_InitBBRFRegisterDefinition
 417 *
 418 * OverView:     Initialize Register definition offset for Radio Path A/B/C/D
 419 *
 420 * Input:
 421 *               struct adapter *        Adapter,
 422 *
 423 * Output:       None
 424 * Return:               None
 425 * Note:         The initialization value is constant and it should never be changes
 426 */
 427 static  void
 428 phy_InitBBRFRegisterDefinition(
 429 struct adapter *        Adapter
 430 )
 431 {
 432         struct hal_com_data             *pHalData = GET_HAL_DATA(Adapter);
 433
 434         /*  RF Interface Sowrtware Control */
 435         pHalData->PHYRegDef[ODM_RF_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; /*  16 LSBs if read 32-bit from 0x870 */
 436         pHalData->PHYRegDef[ODM_RF_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; /*  16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */
 437
 438         /*  RF Interface Output (and Enable) */
 439         pHalData->PHYRegDef[ODM_RF_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; /*  16 LSBs if read 32-bit from 0x860 */
 440         pHalData->PHYRegDef[ODM_RF_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; /*  16 LSBs if read 32-bit from 0x864 */
 441
 442         /*  RF Interface (Output and)  Enable */
 443         pHalData->PHYRegDef[ODM_RF_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; /*  16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */
 444         pHalData->PHYRegDef[ODM_RF_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; /*  16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */
 445
 446         pHalData->PHYRegDef[ODM_RF_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; /* LSSI Parameter */
 447         pHalData->PHYRegDef[ODM_RF_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
 448
 449         pHalData->PHYRegDef[ODM_RF_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;  /* wire control parameter2 */
 450         pHalData->PHYRegDef[ODM_RF_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2;  /* wire control parameter2 */
 451
 452         /*  Tranceiver Readback LSSI/HSPI mode */
 453         pHalData->PHYRegDef[ODM_RF_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
 454         pHalData->PHYRegDef[ODM_RF_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
 455         pHalData->PHYRegDef[ODM_RF_PATH_A].rfLSSIReadBackPi = TransceiverA_HSPI_Readback;
 456         pHalData->PHYRegDef[ODM_RF_PATH_B].rfLSSIReadBackPi = TransceiverB_HSPI_Readback;
 457
 458 }
 459
 460 static  int
 461 phy_BB8723b_Config_ParaFile(
 462 struct adapter *Adapter
 463         )
 464 {
 465         struct hal_com_data             *pHalData = GET_HAL_DATA(Adapter);
 466         int                     rtStatus = _SUCCESS;
 467         u8 sz8723BBRegFile[] = RTL8723B_PHY_REG;
 468         u8 sz8723AGCTableFile[] = RTL8723B_AGC_TAB;
 469         u8 sz8723BBBRegPgFile[] = RTL8723B_PHY_REG_PG;
 470         u8 sz8723BBRegMpFile[] = RTL8723B_PHY_REG_MP;
 471         u8 sz8723BRFTxPwrLmtFile[] = RTL8723B_TXPWR_LMT;
 472         u8 *pszBBRegFile = NULL, *pszAGCTableFile = NULL, *pszBBRegPgFile = NULL, *pszBBRegMpFile = NULL, *pszRFTxPwrLmtFile = NULL;
 473
 474         pszBBRegFile = sz8723BBRegFile ;
 475         pszAGCTableFile = sz8723AGCTableFile;
 476         pszBBRegPgFile = sz8723BBBRegPgFile;
 477         pszBBRegMpFile = sz8723BBRegMpFile;
 478         pszRFTxPwrLmtFile = sz8723BRFTxPwrLmtFile;
 479
 480         /*  Read Tx Power Limit File */
 481         PHY_InitTxPowerLimit(Adapter);
 482         if (Adapter->registrypriv.RegEnableTxPowerLimit == 1 ||
 483              (Adapter->registrypriv.RegEnableTxPowerLimit == 2 && pHalData->EEPROMRegulatory == 1))
 484         {
 485 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
 486                 if (PHY_ConfigRFWithPowerLimitTableParaFile(Adapter, pszRFTxPwrLmtFile) == _FAIL)
 487 #endif
 488                 {
 489                         if (HAL_STATUS_SUCCESS != ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv, CONFIG_RF_TXPWR_LMT, (ODM_RF_RADIO_PATH_E)0))
 490                                 rtStatus = _FAIL;
 491                 }
 492
 493                 if (rtStatus != _SUCCESS) {
 494                         DBG_871X("%s():Read Tx power limit fail\n", __func__);
 495                         goto phy_BB8190_Config_ParaFile_Fail;
 496                 }
 497         }
 498
 499         /*  */
 500         /*  1. Read PHY_REG.TXT BB INIT!! */
 501         /*  */
 502 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
 503         if (phy_ConfigBBWithParaFile(Adapter, pszBBRegFile, CONFIG_BB_PHY_REG) == _FAIL)
 504 #endif
 505         {
 506                 if (HAL_STATUS_SUCCESS != ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_PHY_REG))
 507                         rtStatus = _FAIL;
 508         }
 509
 510         if (rtStatus != _SUCCESS) {
 511                 DBG_8192C("%s():Write BB Reg Fail!!", __func__);
 512                 goto phy_BB8190_Config_ParaFile_Fail;
 513         }
 514
 515         /*  If EEPROM or EFUSE autoload OK, We must config by PHY_REG_PG.txt */
 516         PHY_InitTxPowerByRate(Adapter);
 517         if (Adapter->registrypriv.RegEnableTxPowerByRate == 1 ||
 518              (Adapter->registrypriv.RegEnableTxPowerByRate == 2 && pHalData->EEPROMRegulatory != 2))
 519         {
 520 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
 521                 if (phy_ConfigBBWithPgParaFile(Adapter, pszBBRegPgFile) == _FAIL)
 522 #endif
 523                 {
 524                         if (HAL_STATUS_SUCCESS != ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_PHY_REG_PG))
 525                                 rtStatus = _FAIL;
 526                 }
 527
 528                 if (pHalData->odmpriv.PhyRegPgValueType == PHY_REG_PG_EXACT_VALUE)
 529                         PHY_TxPowerByRateConfiguration(Adapter);
 530
 531                 if (Adapter->registrypriv.RegEnableTxPowerLimit == 1 ||
 532                  (Adapter->registrypriv.RegEnableTxPowerLimit == 2 && pHalData->EEPROMRegulatory == 1))
 533                         PHY_ConvertTxPowerLimitToPowerIndex(Adapter);
 534
 535                 if (rtStatus != _SUCCESS) {
 536                         DBG_8192C("%s():BB_PG Reg Fail!!\n", __func__);
 537                 }
 538         }
 539
 540         /*  */
 541         /*  2. Read BB AGC table Initialization */
 542         /*  */
 543 #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
 544         if (phy_ConfigBBWithParaFile(Adapter, pszAGCTableFile, CONFIG_BB_AGC_TAB) == _FAIL)
 545 #endif
 546         {
 547                 if (HAL_STATUS_SUCCESS != ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_AGC_TAB))
 548                         rtStatus = _FAIL;
 549         }
 550
 551         if (rtStatus != _SUCCESS) {
 552                 DBG_8192C("%s():AGC Table Fail\n", __func__);
 553                 goto phy_BB8190_Config_ParaFile_Fail;
 554         }
 555
 556 phy_BB8190_Config_ParaFile_Fail:
 557
 558         return rtStatus;
 559 }
 560
 561
 562 int
 563 PHY_BBConfig8723B(
 564 struct adapter *Adapter
 565         )
 566 {
 567         int     rtStatus = _SUCCESS;
 568         struct hal_com_data     *pHalData = GET_HAL_DATA(Adapter);
 569         u32 RegVal;
 570         u8 CrystalCap;
 571
 572         phy_InitBBRFRegisterDefinition(Adapter);
 573
 574         /*  Enable BB and RF */
 575         RegVal = rtw_read16(Adapter, REG_SYS_FUNC_EN);
 576         rtw_write16(Adapter, REG_SYS_FUNC_EN, (u16)(RegVal|BIT13|BIT0|BIT1));
 577
 578         rtw_write32(Adapter, 0x948, 0x280);     /*  Others use Antenna S1 */
 579
 580         rtw_write8(Adapter, REG_RF_CTRL, RF_EN|RF_RSTB|RF_SDMRSTB);
 581
 582         msleep(1);
 583
 584         PHY_SetRFReg(Adapter, ODM_RF_PATH_A, 0x1, 0xfffff, 0x780);
 585
 586         rtw_write8(Adapter, REG_SYS_FUNC_EN, FEN_PPLL|FEN_PCIEA|FEN_DIO_PCIE|FEN_BB_GLB_RSTn|FEN_BBRSTB);
 587
 588         rtw_write8(Adapter, REG_AFE_XTAL_CTRL+1, 0x80);
 589
 590         /*  */
 591         /*  Config BB and AGC */
 592         /*  */
 593         rtStatus = phy_BB8723b_Config_ParaFile(Adapter);
 594
 595         /*  0x2C[23:18] = 0x2C[17:12] = CrystalCap */
 596         CrystalCap = pHalData->CrystalCap & 0x3F;
 597         PHY_SetBBReg(Adapter, REG_MAC_PHY_CTRL, 0xFFF000, (CrystalCap | (CrystalCap << 6)));
 598
 599         return rtStatus;
 600 }
 601
 602 static void phy_LCK_8723B(
 603 struct adapter *Adapter
 604         )
 605 {
 606         PHY_SetRFReg(Adapter, RF_PATH_A, 0xB0, bRFRegOffsetMask, 0xDFBE0);
 607         PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, 0x8C01);
 608         mdelay(200);
 609         PHY_SetRFReg(Adapter, RF_PATH_A, 0xB0, bRFRegOffsetMask, 0xDFFE0);
 610 }
 611
 612 int
 613 PHY_RFConfig8723B(
 614 struct adapter *Adapter
 615         )
 616 {
 617         int             rtStatus = _SUCCESS;
 618
 619         /*  */
 620         /*  RF config */
 621         /*  */
 622         rtStatus = PHY_RF6052_Config8723B(Adapter);
 623
 624         phy_LCK_8723B(Adapter);
 625         /* PHY_BB8723B_Config_1T(Adapter); */
 626
 627         return rtStatus;
 628 }
 629
 630 /**************************************************************************************************************
 631  *   Description:
 632  *       The low-level interface to set TxAGC , called by both MP and Normal Driver.
 633  *
 634  *                                                                                    <20120830, Kordan>
 635  **************************************************************************************************************/
 636
 637 void
 638 PHY_SetTxPowerIndex_8723B(
 639 struct adapter *                Adapter,
 640 u32                             PowerIndex,
 641 u8                      RFPath,
 642 u8                      Rate
 643         )
 644 {
 645         if (RFPath == ODM_RF_PATH_A || RFPath == ODM_RF_PATH_B)
 646         {
 647                 switch (Rate)
 648                 {
 649                         case MGN_1M:    PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32,      bMaskByte1, PowerIndex); break;
 650                         case MGN_2M:    PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte1, PowerIndex); break;
 651                         case MGN_5_5M:  PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte2, PowerIndex); break;
 652                         case MGN_11M:   PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte3, PowerIndex); break;
 653
 654                         case MGN_6M:    PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskByte0, PowerIndex); break;
 655                         case MGN_9M:    PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskByte1, PowerIndex); break;
 656                         case MGN_12M:   PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskByte2, PowerIndex); break;
 657                         case MGN_18M:   PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskByte3, PowerIndex); break;
 658
 659                         case MGN_24M:   PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskByte0, PowerIndex); break;
 660                         case MGN_36M:   PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskByte1, PowerIndex); break;
 661                         case MGN_48M:   PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskByte2, PowerIndex); break;
 662                         case MGN_54M:   PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskByte3, PowerIndex); break;
 663
 664                         case MGN_MCS0:  PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte0, PowerIndex); break;
 665                         case MGN_MCS1:  PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte1, PowerIndex); break;
 666                         case MGN_MCS2:  PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte2, PowerIndex); break;
 667                         case MGN_MCS3:  PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte3, PowerIndex); break;
 668
 669                         case MGN_MCS4:  PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte0, PowerIndex); break;
 670                         case MGN_MCS5:  PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte1, PowerIndex); break;
 671                         case MGN_MCS6:  PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte2, PowerIndex); break;
 672                         case MGN_MCS7:  PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte3, PowerIndex); break;
 673
 674                         default:
 675                              DBG_871X("Invalid Rate!!\n");
 676                              break;
 677                 }
 678         }
 679         else
 680         {
 681                 RT_TRACE(_module_hal_init_c_, _drv_err_, ("Invalid RFPath!!\n"));
 682         }
 683 }
 684
 685 u8
 686 PHY_GetTxPowerIndex_8723B(
 687 struct adapter *                padapter,
 688 u8                      RFPath,
 689 u8                      Rate,
 690 enum CHANNEL_WIDTH              BandWidth,
 691 u8                      Channel
 692         )
 693 {
 694         struct hal_com_data *   pHalData = GET_HAL_DATA(padapter);
 695         s8                                      txPower = 0, powerDiffByRate = 0, limit = 0;
 696         bool                            bIn24G = false;
 697
 698         /* DBG_871X("===>%s\n", __func__); */
 699
 700         txPower = (s8) PHY_GetTxPowerIndexBase(padapter, RFPath, Rate, BandWidth, Channel, &bIn24G);
 701         powerDiffByRate = PHY_GetTxPowerByRate(padapter, BAND_ON_2_4G, ODM_RF_PATH_A, RF_1TX, Rate);
 702
 703         limit = PHY_GetTxPowerLimit(padapter, padapter->registrypriv.RegPwrTblSel, (u8)(!bIn24G), pHalData->CurrentChannelBW, RFPath, Rate, pHalData->CurrentChannel);
 704
 705         powerDiffByRate = powerDiffByRate > limit ? limit : powerDiffByRate;
 706         txPower += powerDiffByRate;
 707
 708         txPower += PHY_GetTxPowerTrackingOffset(padapter, RFPath, Rate);
 709
 710         if (txPower > MAX_POWER_INDEX)
 711                 txPower = MAX_POWER_INDEX;
 712
 713         /* DBG_871X("Final Tx Power(RF-%c, Channel: %d) = %d(0x%X)\n", ((RFPath == 0)?'A':'B'), Channel, txPower, txPower)); */
 714         return (u8) txPower;
 715 }
 716
 717 void
 718 PHY_SetTxPowerLevel8723B(
 719 struct adapter *        Adapter,
 720 u8              Channel
 721         )
 722 {
 723         struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
 724         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;
 725         pFAT_T                  pDM_FatTable = &pDM_Odm->DM_FatTable;
 726         u8              RFPath = ODM_RF_PATH_A;
 727
 728         if (pHalData->AntDivCfg) {/*  antenna diversity Enable */
 729                 RFPath = ((pDM_FatTable->RxIdleAnt == MAIN_ANT) ? ODM_RF_PATH_A : ODM_RF_PATH_B);
 730         }
 731         else { /*  antenna diversity disable */
 732                 RFPath = pHalData->ant_path;
 733         }
 734
 735         RT_TRACE(_module_hal_init_c_, _drv_info_, ("==>PHY_SetTxPowerLevel8723B()\n"));
 736
 737         PHY_SetTxPowerLevelByPath(Adapter, Channel, RFPath);
 738
 739         RT_TRACE(_module_hal_init_c_, _drv_info_, ("<==PHY_SetTxPowerLevel8723B()\n"));
 740 }
 741
 742 void
 743 PHY_GetTxPowerLevel8723B(
 744 struct adapter *        Adapter,
 745         s32*                    powerlevel
 746         )
 747 {
 748 }
 749
 750 static void
 751 phy_SetRegBW_8723B(
 752 struct adapter *        Adapter,
 753         enum CHANNEL_WIDTH      CurrentBW
 754 )
 755 {
 756         u16 RegRfMod_BW, u2tmp = 0;
 757         RegRfMod_BW = rtw_read16(Adapter, REG_TRXPTCL_CTL_8723B);
 758
 759         switch (CurrentBW)
 760         {
 761                 case CHANNEL_WIDTH_20:
 762                         rtw_write16(Adapter, REG_TRXPTCL_CTL_8723B, (RegRfMod_BW & 0xFE7F)); /*  BIT 7 = 0, BIT 8 = 0 */
 763                         break;
 764
 765                 case CHANNEL_WIDTH_40:
 766                         u2tmp = RegRfMod_BW | BIT7;
 767                         rtw_write16(Adapter, REG_TRXPTCL_CTL_8723B, (u2tmp & 0xFEFF)); /*  BIT 7 = 1, BIT 8 = 0 */
 768                         break;
 769
 770                 case CHANNEL_WIDTH_80:
 771                         u2tmp = RegRfMod_BW | BIT8;
 772                         rtw_write16(Adapter, REG_TRXPTCL_CTL_8723B, (u2tmp & 0xFF7F)); /*  BIT 7 = 0, BIT 8 = 1 */
 773                         break;
 774
 775                 default:
 776                         DBG_871X("phy_PostSetBWMode8723B():     unknown Bandwidth: %#X\n", CurrentBW);
 777                         break;
 778         }
 779 }
 780
 781 static u8
 782 phy_GetSecondaryChnl_8723B(
 783 struct adapter *Adapter
 784 )
 785 {
 786         u8 SCSettingOf40 = 0, SCSettingOf20 = 0;
 787         struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
 788
 789         RT_TRACE(_module_hal_init_c_, _drv_info_, ("SCMapping: VHT Case: pHalData->CurrentChannelBW %d, pHalData->nCur80MhzPrimeSC %d, pHalData->nCur40MhzPrimeSC %d\n", pHalData->CurrentChannelBW, pHalData->nCur80MhzPrimeSC, pHalData->nCur40MhzPrimeSC));
 790         if (pHalData->CurrentChannelBW == CHANNEL_WIDTH_80)
 791         {
 792                 if (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
 793                         SCSettingOf40 = VHT_DATA_SC_40_LOWER_OF_80MHZ;
 794                 else if (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
 795                         SCSettingOf40 = VHT_DATA_SC_40_UPPER_OF_80MHZ;
 796                 else
 797                         RT_TRACE(_module_hal_init_c_, _drv_err_, ("SCMapping: Not Correct Primary40MHz Setting\n"));
 798
 799                 if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER))
 800                         SCSettingOf20 = VHT_DATA_SC_20_LOWEST_OF_80MHZ;
 801                 else if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER))
 802                         SCSettingOf20 = VHT_DATA_SC_20_LOWER_OF_80MHZ;
 803                 else if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER))
 804                         SCSettingOf20 = VHT_DATA_SC_20_UPPER_OF_80MHZ;
 805                 else if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER))
 806                         SCSettingOf20 = VHT_DATA_SC_20_UPPERST_OF_80MHZ;
 807                 else
 808                         RT_TRACE(_module_hal_init_c_, _drv_err_, ("SCMapping: Not Correct Primary40MHz Setting\n"));
 809         }
 810         else if (pHalData->CurrentChannelBW == CHANNEL_WIDTH_40)
 811         {
 812                 RT_TRACE(_module_hal_init_c_, _drv_info_, ("SCMapping: VHT Case: pHalData->CurrentChannelBW %d, pHalData->nCur40MhzPrimeSC %d\n", pHalData->CurrentChannelBW, pHalData->nCur40MhzPrimeSC));
 813
 814                 if (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
 815                         SCSettingOf20 = VHT_DATA_SC_20_UPPER_OF_80MHZ;
 816                 else if (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
 817                         SCSettingOf20 = VHT_DATA_SC_20_LOWER_OF_80MHZ;
 818                 else
 819                         RT_TRACE(_module_hal_init_c_, _drv_err_, ("SCMapping: Not Correct Primary40MHz Setting\n"));
 820         }
 821
 822         RT_TRACE(_module_hal_init_c_, _drv_info_, ("SCMapping: SC Value %x\n", ((SCSettingOf40 << 4) | SCSettingOf20)));
 823         return  ((SCSettingOf40 << 4) | SCSettingOf20);
 824 }
 825
 826 static void
 827 phy_PostSetBwMode8723B(
 828 struct adapter *Adapter
 829 )
 830 {
 831         u8      SubChnlNum = 0;
 832         struct hal_com_data     *pHalData = GET_HAL_DATA(Adapter);
 833
 834
 835         /* 3 Set Reg668 Reg440 BW */
 836         phy_SetRegBW_8723B(Adapter, pHalData->CurrentChannelBW);
 837
 838         /* 3 Set Reg483 */
 839         SubChnlNum = phy_GetSecondaryChnl_8723B(Adapter);
 840         rtw_write8(Adapter, REG_DATA_SC_8723B, SubChnlNum);
 841
 842         /* 3 */
 843         /* 3<2>Set PHY related register */
 844         /* 3 */
 845         switch (pHalData->CurrentChannelBW)
 846         {
 847                 /* 20 MHz channel*/
 848                 case CHANNEL_WIDTH_20:
 849                         PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x0);
 850
 851                         PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x0);
 852
 853 /*                      PHY_SetBBReg(Adapter, rFPGA0_AnalogParameter2, BIT10, 1); */
 854
 855                         PHY_SetBBReg(Adapter, rOFDM0_TxPseudoNoiseWgt, (BIT31|BIT30), 0x0);
 856                         break;
 857
 858
 859                 /* 40 MHz channel*/
 860                 case CHANNEL_WIDTH_40:
 861                         PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x1);
 862
 863                         PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x1);
 864
 865                         /*  Set Control channel to upper or lower. These settings are required only for 40MHz */
 866                         PHY_SetBBReg(Adapter, rCCK0_System, bCCKSideBand, (pHalData->nCur40MhzPrimeSC>>1));
 867
 868                         PHY_SetBBReg(Adapter, rOFDM1_LSTF, 0xC00, pHalData->nCur40MhzPrimeSC);
 869
 870 /*                      PHY_SetBBReg(Adapter, rFPGA0_AnalogParameter2, BIT10, 0); */
 871
 872                         PHY_SetBBReg(Adapter, 0x818, (BIT26|BIT27), (pHalData->nCur40MhzPrimeSC ==HAL_PRIME_CHNL_OFFSET_LOWER)?2:1);
 873
 874                         break;
 875
 876
 877
 878                 default:
 879                         /*RT_TRACE(COMP_DBG, DBG_LOUD, ("phy_SetBWMode8723B(): unknown Bandwidth: %#X\n"\
 880                                                 , pHalData->CurrentChannelBW));*/
 881                         break;
 882
 883         }
 884
 885         /* 3<3>Set RF related register */
 886         PHY_RF6052SetBandwidth8723B(Adapter, pHalData->CurrentChannelBW);
 887 }
 888
 889 static void
 890 phy_SwChnl8723B(
 891 struct adapter *                                padapter
 892         )
 893 {
 894         struct hal_com_data     *pHalData = GET_HAL_DATA(padapter);
 895         u8      channelToSW = pHalData->CurrentChannel;
 896
 897         if (pHalData->rf_chip == RF_PSEUDO_11N)
 898         {
 899                 /* RT_TRACE(COMP_MLME, DBG_LOUD, ("phy_SwChnl8723B: return for PSEUDO\n")); */
 900                 return;
 901         }
 902         pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff00) | channelToSW );
 903         PHY_SetRFReg(padapter, ODM_RF_PATH_A, RF_CHNLBW, 0x3FF, pHalData->RfRegChnlVal[0]);
 904         PHY_SetRFReg(padapter, ODM_RF_PATH_B, RF_CHNLBW, 0x3FF, pHalData->RfRegChnlVal[0]);
 905
 906         DBG_8192C("===>phy_SwChnl8723B: Channel = %d\n", channelToSW);
 907 }
 908
 909 static void
 910 phy_SwChnlAndSetBwMode8723B(
 911         struct adapter *        Adapter
 912 )
 913 {
 914         struct hal_com_data             *pHalData = GET_HAL_DATA(Adapter);
 915
 916         /* RT_TRACE(COMP_SCAN, DBG_LOUD, ("phy_SwChnlAndSetBwMode8723B(): bSwChnl %d, bSetChnlBW %d\n", pHalData->bSwChnl, pHalData->bSetChnlBW)); */
 917         if (Adapter->bNotifyChannelChange)
 918         {
 919                 DBG_871X("[%s] bSwChnl =%d, ch =%d, bSetChnlBW =%d, bw =%d\n",
 920                         __func__,
 921                         pHalData->bSwChnl,
 922                         pHalData->CurrentChannel,
 923                         pHalData->bSetChnlBW,
 924                         pHalData->CurrentChannelBW);
 925         }
 926
 927         if ((Adapter->bDriverStopped) || (Adapter->bSurpriseRemoved))
 928         {
 929                 return;
 930         }
 931
 932         if (pHalData->bSwChnl)
 933         {
 934                 phy_SwChnl8723B(Adapter);
 935                 pHalData->bSwChnl = false;
 936         }
 937
 938         if (pHalData->bSetChnlBW)
 939         {
 940                 phy_PostSetBwMode8723B(Adapter);
 941                 pHalData->bSetChnlBW = false;
 942         }
 943
 944         PHY_SetTxPowerLevel8723B(Adapter, pHalData->CurrentChannel);
 945 }
 946
 947 static void
 948 PHY_HandleSwChnlAndSetBW8723B(
 949 struct adapter *                Adapter,
 950 bool                            bSwitchChannel,
 951 bool                            bSetBandWidth,
 952 u8                      ChannelNum,
 953 enum CHANNEL_WIDTH      ChnlWidth,
 954 enum EXTCHNL_OFFSET     ExtChnlOffsetOf40MHz,
 955 enum EXTCHNL_OFFSET     ExtChnlOffsetOf80MHz,
 956 u8                      CenterFrequencyIndex1
 957 )
 958 {
 959         /* static bool          bInitialzed = false; */
 960         struct hal_com_data *   pHalData = GET_HAL_DATA(Adapter);
 961         u8                      tmpChannel = pHalData->CurrentChannel;
 962         enum CHANNEL_WIDTH      tmpBW = pHalData->CurrentChannelBW;
 963         u8                      tmpnCur40MhzPrimeSC = pHalData->nCur40MhzPrimeSC;
 964         u8                      tmpnCur80MhzPrimeSC = pHalData->nCur80MhzPrimeSC;
 965         u8                      tmpCenterFrequencyIndex1 =pHalData->CurrentCenterFrequencyIndex1;
 966
 967         /* DBG_871X("=> PHY_HandleSwChnlAndSetBW8812: bSwitchChannel %d, bSetBandWidth %d\n", bSwitchChannel, bSetBandWidth); */
 968
 969         /* check is swchnl or setbw */
 970         if (!bSwitchChannel && !bSetBandWidth)
 971         {
 972                 DBG_871X("PHY_HandleSwChnlAndSetBW8812:  not switch channel and not set bandwidth\n");
 973                 return;
 974         }
 975
 976         /* skip change for channel or bandwidth is the same */
 977         if (bSwitchChannel)
 978         {
 979                 /* if (pHalData->CurrentChannel != ChannelNum) */
 980                 {
 981                         if (HAL_IsLegalChannel(Adapter, ChannelNum))
 982                                 pHalData->bSwChnl = true;
 983                 }
 984         }
 985
 986         if (bSetBandWidth)
 987         {
 988                 pHalData->bSetChnlBW = true;
 989         }
 990
 991         if (!pHalData->bSetChnlBW && !pHalData->bSwChnl)
 992         {
 993                 /* DBG_871X("<= PHY_HandleSwChnlAndSetBW8812: bSwChnl %d, bSetChnlBW %d\n", pHalData->bSwChnl, pHalData->bSetChnlBW); */
 994                 return;
 995         }
 996
 997
 998         if (pHalData->bSwChnl)
 999         {
1000                 pHalData->CurrentChannel =ChannelNum;
1001                 pHalData->CurrentCenterFrequencyIndex1 = ChannelNum;
1002         }
1003
1004
1005         if (pHalData->bSetChnlBW)
1006         {
1007                 pHalData->CurrentChannelBW = ChnlWidth;
1008                 pHalData->nCur40MhzPrimeSC = ExtChnlOffsetOf40MHz;
1009                 pHalData->nCur80MhzPrimeSC = ExtChnlOffsetOf80MHz;
1010                 pHalData->CurrentCenterFrequencyIndex1 = CenterFrequencyIndex1;
1011         }
1012
1013         /* Switch workitem or set timer to do switch channel or setbandwidth operation */
1014         if ((!Adapter->bDriverStopped) && (!Adapter->bSurpriseRemoved))
1015         {
1016                 phy_SwChnlAndSetBwMode8723B(Adapter);
1017         }
1018         else
1019         {
1020                 if (pHalData->bSwChnl)
1021                 {
1022                         pHalData->CurrentChannel = tmpChannel;
1023                         pHalData->CurrentCenterFrequencyIndex1 = tmpChannel;
1024                 }
1025                 if (pHalData->bSetChnlBW)
1026                 {
1027                         pHalData->CurrentChannelBW = tmpBW;
1028                         pHalData->nCur40MhzPrimeSC = tmpnCur40MhzPrimeSC;
1029                         pHalData->nCur80MhzPrimeSC = tmpnCur80MhzPrimeSC;
1030                         pHalData->CurrentCenterFrequencyIndex1 = tmpCenterFrequencyIndex1;
1031                 }
1032         }
1033 }
1034
1035 void
1036 PHY_SetBWMode8723B(
1037 struct adapter *                                Adapter,
1038 enum CHANNEL_WIDTH      Bandwidth,      /*  20M or 40M */
1039 unsigned char Offset            /*  Upper, Lower, or Don't care */
1040 )
1041 {
1042         struct hal_com_data *   pHalData = GET_HAL_DATA(Adapter);
1043
1044         PHY_HandleSwChnlAndSetBW8723B(Adapter, false, true, pHalData->CurrentChannel, Bandwidth, Offset, Offset, pHalData->CurrentChannel);
1045 }
1046
1047 void
1048 PHY_SwChnl8723B(/*  Call after initialization */
1049 struct adapter *Adapter,
1050 u8 channel
1051         )
1052 {
1053         PHY_HandleSwChnlAndSetBW8723B(Adapter, true, false, channel, 0, 0, 0, channel);
1054 }
1055
1056 void
1057 PHY_SetSwChnlBWMode8723B(
1058 struct adapter *                Adapter,
1059 u8                      channel,
1060 enum CHANNEL_WIDTH      Bandwidth,
1061 u8                      Offset40,
1062 u8                      Offset80
1063 )
1064 {
1065         /* DBG_871X("%s() ===>\n", __func__); */
1066
1067         PHY_HandleSwChnlAndSetBW8723B(Adapter, true, true, channel, Bandwidth, Offset40, Offset80, channel);
1068
1069         /* DBG_871X("<==%s()\n", __func__); */
1070 }